JP2001346171A - Video attached information decoder circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem that VBI data cannot be detected with high accuracy resulting from a fluctuated phase of the VBI data and a sampling clock on the occurrence of jitter due to elongation or contraction in a synchronizing signal and a superimposed data signal caused by a fluctuated TV signal by jitter of a transmission path and a shake of a tape of a VTR after recording because sampling points of the VBI data to be detected are generated at a prescribed constant interval on the basis of a horizontal synchronizing signal resulting from synchronization separation. SOLUTION: Each switching edge of attached data superimposed on the VBI data is detected and a sampling clock whose phase is set again on the basis of the detected switching edge is generated so as to extract the VBI data with high accuracy without receiving accumulated effects of fluctuation or missing of a synchronizing signal and superimposed data due to jitter of a transmission path and a VTR.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to the detection of various types of additional information superimposed on a retrace period of a TV broadcast.

[0002]

2. Description of the Related Art At present, a vertical retrace period of a TV broadcast includes a closed caption, a CGMS-A identification signal, and PAL_.
It is used for transmitting various additional information such as WSS (hereinafter referred to as “VBI data”). Conventionally, as means for detecting these VBI data, a technical report of the Institute of Television Engineers of Japan,
VOL. 19, NO. 60, pages 7 to 12, a dedicated sampling clock phase-locked to a horizontal synchronization signal synchronously separated from an input video signal is generated, and a desired sampling clock is generated based on the horizontal synchronization signal and the vertical synchronization signal. Has been started to detect VBI data.

[0003]

However, conventionally,
Since the sampling points of the detected VBI data are generated at regular intervals based on the horizontal synchronization signal separated from the synchronization, the TV signal fluctuation due to the jitter in the transmission path and the VTR
In the case where jitter such as extension or contraction occurs in the synchronization signal or superimposed data signal due to shaking of the tape after recording, etc., the phase of the VBI data and the sampling clock fluctuates, and accurate detection is performed. There was a problem that could not be done.

[0004]

The above object is achieved by detecting a switching edge of superimposed additional data and generating a clock whose sampling clock phase is reset based on the detected switching edge. It is possible to extract VBI data with high accuracy without accumulating and receiving the influence of the fluctuation or lack of the synchronization signal or the superimposed data due to the jitter of the path or the VTR.

[0005]

1 and 2 show an embodiment of the present invention.
This will be described with reference to FIG. FIG. 1 is a block diagram for decoding the CGMS-A identification signal superimposed on the 20th line of the NTSC signal flyback period, 101 is a synchronization signal detection circuit, 102 is a synchronization signal separation circuit, and 103 is a line selection. Circuit, 104 a start bit gate generation circuit, 105 a VBI superimposed data slice circuit, 106 a VBI data start bit detection circuit, 107 a sampling clock detection circuit, 108 a VBI superimposed data sampling circuit, 109 a detection data hold circuit, 1
Reference numeral 10 denotes an edge detection circuit, and FIGS.
FIG. 3 is a diagram showing signal timing in each block of FIG.

The VIDEO signal (a) on which the VBI data is superimposed is compared with a synchronization signal slice level by a synchronization signal detection circuit 101 to generate a synchronization signal (b). The synchronizing signal separating circuit 102 separates the vertical synchronizing signal (c) and the horizontal synchronizing signal (d) from the synchronizing signal (b) generated by the synchronizing signal detecting circuit 101, and sends them to the line selecting circuit 103 and the start bit gate generating circuit 104. Supply. The line selection circuit 103 generates a line selection pulse (e) to read the data superimposed on the 20th line. Also,
The start bit gate generation circuit 104 outputs C
To detect a start bit signal (ref data) of the GMS-A identification signal, a start bit gate (f) of T1 ± α is generated. The start bit detection circuit 106
The start bit rising timing of the superimposed data slice output (g) generated by the superimposed data slice circuit 105 is extracted by the start bit gate (f), and the start pulse (h) is output. Further, the edge detection circuit 110 determines the data polarity switching timing of the superimposed data slice signal (g), that is, the point where 0 → 1 or 1 → 0 changes, and generates an edge pulse (i).

In this embodiment, as an example of VBI data, D1
= 0, D2 = 0, D3 = 1, D4 = 1, D5 = 0 ...
, An edge pulse is generated at the switching points of D2 → D3 and D4 → D5.

Next, the sampling clock generation circuit 107
Generates a sampling clock (j) having a period T3 and the number N1 after a delay of the time T2 from the start pulse (h). Here, the sampling clock generation circuit 107 has a counter T3 / 2 for generating a sampling clock for each edge pulse (i) generated by the edge detection circuit 110.
To load.

Note that T1, T2, T3, and N1 are appropriately set according to the format of the VBI data to be detected. In the case of this embodiment, in order to detect CGMS-A,
T1 = 11.2 μs, T2 = 4.5 μs, T3 = 2.2
μs, N1 = 20. The superimposition data sampling circuit 108 samples the superimposition data slice output (g) at the timing of the sampling clock (j) generated by the sampling clock generation circuit 107, generates detection data (k), and receives the detection data When the hold circuit 109 receives a predetermined number of superimposed data, the hold circuit 109 holds the data.

As described above, by reloading the value of the sampling clock generation circuit 107 for each edge pulse (i), a sampling clock (j) with high accuracy with respect to temporal expansion and contraction of VBI data is generated. You can do it.

FIG. 5 is a timing chart showing an example in which the VBI signal of the VIDEO signal is temporally contracted due to deterioration of the transmission path.

As shown in FIG. 1G, when the period of the VBI data is reduced by about 20%, the sampling clock generated by the sampling clock generation circuit 107 is not reloaded. When repeated at T3, the VBI detection data (k '') captured by the sampling clock (j '') cannot capture the data of D4.

However, as shown in this embodiment, the sampling clock generation circuit 107 is reloaded to the value of T3 / 2 every edge pulse (i '), so that the generated sampling clock is (j'). Detection of VBI data can be performed with high accuracy like detection data (k ').

[0014]

According to the present invention, it is possible to extract VBI data with high accuracy even when a synchronization signal or VBI data is temporally shaken or missing due to deterioration of the transmission path of the VIDEO signal.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a pulse timing chart in each block of FIG. 1;

FIG. 3 is a pulse timing chart in each block of FIG. 1;

FIG. 4 is a pulse timing chart in each block of FIG. 1;

FIG. 5 shows VBI of a VIDEO signal due to deterioration of a transmission path.
FIG. 4 is a timing chart showing an example of a case where a signal temporally contracts.

[Explanation of symbols]

101: Synchronous signal detection circuit, 102: Synchronous signal separation circuit, 103: Line selection circuit, 104: Start bit gate generation circuit, 105: Superimposed data slice circuit, 1
06: start bit detection circuit, 107: sampling clock generation circuit, 108: superimposed data detection circuit, 10
9: detection data hold circuit, 110: edge detection circuit, (a): VIDEO signal, (b): synchronization signal,
(C): vertical synchronization signal, (d): horizontal synchronization signal, (e)
... line selection pulse, (f) ... start bit gate,
(G) ... superimposed data slice output, (h) ... start pulse, (i) ... edge pulse, (j) ... sampling clock, (k) ... VBI detection data, (g ') ... superimposed data slice output (signal deterioration) (Time), (h ') ... start pulse (when signal is degraded), (i') ... edge pulse (when signal is degraded), (j ') ... sampling clock (when signal is degraded), (k') ... VBI detection data (During signal degradation),
(J '') ... sampling clock (when signal is degraded)
(K '')... VBI detection data (at the time of signal deterioration).

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04N 7/025 7/03 7/035 (72) Inventor Shinichi Nonaka 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa-ken F-term (reference) in Digital Media Development Division, Hitachi, Ltd. 5C053 HA04 HA40 JA15 JA21 JA26 JA28 JA30 KA17 KA18 5C063 AA02 AA03 CA01 CA14 DA03 DA07 DA13 DB02 EB03 EB13

Claims (3)

[Claims] 1. A circuit for detecting a video composite synchronizing signal from a video signal, a circuit for generating a horizontal synchronizing signal and a vertical synchronizing signal from the detected video composite synchronizing signal, and an arbitrary phase from the horizontal synchronizing signal and the vertical synchronizing signal. A gate pulse generation circuit that generates a gate pulse of the same, a clock generation circuit that generates a sampling clock of an arbitrary period from an arbitrary timing independent of the gate pulse generation circuit, and a sampling clock generated by the clock generation circuit, superimposed on an analog video signal A video additional information decoder circuit having an additional data extraction circuit for extracting the additional information, wherein the clock generation circuit is controlled at a switching timing of a signal output from the additional data extraction circuit. 2. A sampling clock generated by the clock generating circuit according to claim 1, wherein the sampling clock is loaded to a value of Tb at a period Ta and at a switching timing of a signal output from the additional data extracting circuit. Video additional information decoder circuit. 3. A sampling clock generated by the clock generation circuit according to claim 1 having a period Ta and being loaded to a value of Ta / 2 at a switching timing of a signal output from the additional data extraction circuit. A video additional information decoder circuit.