JP3251316B2 - Synchronous signal generation circuit and A / D converter using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing signal generating circuit for generating two new clocks based on a master clock and an A / D converter using the synchronizing signal generating circuit. Synchronous signal generation circuit and clock feed circuit that can set the frequency without loss
The present invention relates to an A / D converter that can reduce the influence of through.

[0002]

2. Description of the Related Art Conventionally, in a measuring / testing system for electric components such as an IC tester, a system clock has a high speed such as about 100 MHz. For this reason, the master clock cannot be used as it is, for example, as an operation clock (for example, on the order of 10 MHz) of the A / D converter. Therefore, the above A /
In order to operate a D converter or the like, it is necessary to use a new clock system that is slower than the master clock.
When such a clock system is generated, (1) a new clock system different from the master clock system is configured by a local oscillator, and (2) the system master clock is frequency-divided to generate a new clock system. , Etc. are adopted.

However, in the method (1), the phase of a new clock is also determined by the local oscillator itself. For this reason, it is necessary to lock the clock with the master clock, so that a peripheral circuit such as a PLL is required, which complicates the circuit and increases the manufacturing cost. The method (2) is generally used in a synchronous system. In this method, as shown in FIG. 5A, two mutually independent new clocks CLK _M and CLK _N (M> N) are generated by the clock MCLK generated by the master clock generating means 10.
Is generated by the first and second frequency dividing means 11 and 12. When it is intended to drive, for example, a successive approximation type A / D converter by these CLK _M and CLK _N ,
The following problems arise.

That is, when CLK _M is used as a trigger for starting A / D conversion and CLK _N is used as an operation clock for the A / D conversion circuit, immediately after CLK _M , depending on how M and N are selected. The time at which CLK _N appears (phase delay time) varies for each sampling.

[0005] FIG. 5B shows a case where M = 1 in FIG.
5 is a time chart showing the relationship between CLK _M and CLK _N when 0, N = 3; in this case, CLK _N
, Three CLK _Ns with different phase relationships (Cases 1 to
3 as shown in FIG. 3). When the phase delay time is periodically shifted as described above, a difference component (beat clock) between the two clocks appears in the measurement result, which adversely affects the fast Fourier transform processing or the like. On the other hand, when M and N are selected so as to be integral multiples of each other, the phase relationship between the clock CLK _M and the clock CLK _N is always constant, but the trigger for starting A / D conversion (CLK _M ) In this case, the selection range of the operation clock (CLK _N ) of the A / D conversion circuit is limited, and the independence of the two is lost.

[0006]

SUMMARY OF THE INVENTION The present invention has been proposed in order to solve the above-mentioned problems, and can divide a master clock to generate two independent new clock systems. An object of the present invention is to provide a synchronization signal generation circuit and an A / D converter using the same, which can improve performance by eliminating the influence of through.

[0007]

SUMMARY OF THE INVENTION A synchronization signal generating circuit according to the present invention
A clock generating unit for generating two new clocks having different frequency division ratios based on the master clock; a first frequency dividing means for generating a clock having a large frequency dividing ratio; A second frequency dividing means for receiving a clock of the frequency divider and resetting a frequency division count value by a driving edge of the clock, and generating a clock having a small frequency division ratio. .

The A / D converter of the present invention uses the synchronizing signal generation circuit, and uses an output clock of the first frequency dividing means to sample / hold (S / H).
The circuit is driven and A is output by the output clock of the second frequency dividing means.
/ D conversion circuit is driven.

In the synchronous signal generating circuit according to the present invention, the first and second frequency dividing means generate a new clock having a different frequency dividing ratio by dividing the high-speed master clock. Then, the count value of the second frequency dividing means is reset by the driving edge of the clock having a large frequency dividing ratio (hereinafter referred to as "first clock") generated by the first frequency dividing means. Accordingly, during a certain period from the driving edge of the first clock, that is, during one cycle period of a clock (hereinafter, referred to as a “second clock”) having a small frequency division ratio generated by the second frequency dividing means, The frequency dividing means 2 does not output the driving edge.

In the A / D converter of the present invention, the above-mentioned synchronizing signal generation circuit is used. In this case, the first and second frequency dividing means may be, for example, a high-speed master
By dividing the clock, new clocks of the order of 10 MHz are generated. The S / H circuit of the A / D converter is driven by a first clock having a large division ratio, and the A / D conversion circuit is driven by a second clock having a small division ratio. At the driving edge of the first clock,
The second frequency dividing means is reset to the count value of the master clock input. Simultaneously with this reset, the second frequency divider restarts counting the master clock input,
After the S / H circuit is driven by the first clock, the drive edge of the second clock drives the A / D converter circuit after the elapse of one cycle period of the second clock. Therefore, a constant interval (that is, one cycle of the second clock) is always provided between the timing of starting the S / H and the timing of starting the A / D conversion. As a result, a clock having a phase shifted periodically does not appear every time during the A / D conversion cycle, so that the influence of feedthrough caused by the clock is reduced.

The synchronization signal generating circuit of the present invention can be used as long as it performs a sample / hold operation. Therefore, it goes without saying that the A / D converter of the present invention can be applied not only to the successive approximation type but also to an A / D converter having a sample / hold circuit such as a flash type, a subranging type, or various integration types.

[0012]

1A and 1B are explanatory diagrams showing an embodiment of a synchronization signal generating circuit according to the present invention. In FIG. 1A, the clock MCL from the master clock generating means 1 is shown.
K is output to the first and second frequency dividing means 2 and 3, which divide the first and second clocks CLK _M and CLK _M with the dividing ratios M and N.
CLK _N is being output. And the output C of the frequency dividing means 2
LK _M are input to the division unit 3, the dividing means 3 inputs CL
The edge input K _M, performs a dividing operation of resetting the count value.

FIG. 3B is a circuit time chart for the case where M = 10 and N = 3, and shows the first clock CLK.
The falling edge of _M (FIG. 1 (B) refer to t _1), how the count value of the second frequency dividing means 3 is reset is shown. The second frequency dividing means resumes counting from the reset state, subsequent to the first clock CLK _M to generate a falling edge (Fig. (B) refer to t _2), the master clock MCLK A frequency division operation is performed in units of three cycles.

FIG. 2A is a specific circuit diagram of the second frequency dividing means 3, which illustrates frequency dividing means for generating a driving clock for the A / D converter. Is a counter (for example, MC10H016 or the like is used) 4
And an AND gate 5. As the counter 4 shown in the figure, a load set value (0 to 15) of the count can be preset and the count can be counted up (here, the load set value of the counter 4 is set to 13). There). Also, MCLK is input to the clock input terminal Cp,
Enable terminal PE (in the figure, a negative logic terminal)
Is supplied with an output of an AND gate 5 described later.

Also, a timing clock output terminal TC
(Similar to the negative logic terminal), a work clock WC obtained by dividing MCLK according to the load set value.
LK is output, and the input terminal of the AND gate 5 receives the work clock WCLK and the converted clock CCLK generated by the first frequency dividing means 2 (not shown) (see FIG. 1A). . Here, WCLK is a so-called pacemaker clock for the A / D conversion operation, and CCLK is a clock for triggering the start of the A / D conversion.

FIG. 2B is a circuit diagram of the circuit shown in FIG.
5 is a time chart showing a state of each terminal when LK is at an H level, wherein a falling edge and a rising edge of WCLK are driven at the rising edge of MCLK, and PCLK is driven by the edge of WCLK.
The state in which the edge of E is driven is shown.

FIG. 3 shows MCLK and CCLK when the load setting value of the circuit in FIG.
FIG. 9 is a diagram showing patterns (cases 1 to 8) where WCLK and WCLK can exist. In the figure, numerical values 10 to 15 indicate the count value of the counter, and R indicates resetting of the counter (preset enable). As can be seen from the figure, in each of these cases, the drive edge of WCLK appears after a certain period (the seventh master clock in the figure) from the drive edge of CCLK, and W is driven by a normal clock. are doing.

FIG. 4A is an explanatory diagram showing a successive approximation type A / D converter using the synchronous signal generation circuit.
FIG. 7B is a diagram showing the relationship between the mode of the S / H circuit 6 and each clock. As shown in FIGS. 4A and 4B,
First, the falling edge of CCLK causes the S / H circuit 6 to transition from the hold mode to the sample mode. At the same time, the second frequency dividing means 3 is reset (preset enable), and the counter 4 restarts counting from the load set value 10. Thereafter, the driving edge of WCLK outputs a conversion start signal to the A / D conversion circuit 7, and thereafter,
The A / D conversion circuit 7 performs a successive comparison of the analog input signal and outputs data based on the CLK. Since the start of A / D conversion is performed a fixed time after the start of all sampling,
No beat clock is generated in the measurement result, and digital processing such as fast Fourier transform is performed with high accuracy.

[0019]

As described above, the present invention has the following advantages. (1) In the A / D converter, the effect of the feed-through of the digital clock on the analog measurement has been eliminated by adjusting the phase of the work clock and the conversion clock on hardware. As a result, there is no restriction on the selection between the work clock and the convert clock, and the degree of freedom in frequency setting is increased, so that the measurement accuracy of A / D conversion can be improved.

(2) Even when the phases of the work clock and the convert clock are not mutually prime, the phase relationship of the work clock with respect to the convert clock is always set to be the same. The uncertainty of the phase with the clock can be eliminated.

[Brief description of the drawings]

FIG. 1A is a block diagram showing an example of a synchronization signal generation circuit of the present invention, and FIG. 1B is a time diagram of the circuit.
It is a chart.

FIG. 2A is a specific circuit diagram of a second frequency dividing means used in the A / D converter of the present invention, and FIG. 2B is a view of each terminal when WCLK is at H level in the circuit; FIG.

FIG. 3 shows a circuit load setting value of FIG.
FIG. 11 is a diagram showing a case where MCLK, CCLK and WCLK can exist when the setting is made to.

FIG. 4A is an explanatory diagram showing an A / D converter using the frequency dividing means, and FIG. 4B is a diagram showing a relationship between a mode of an S / H circuit and each clock.

FIG. 5A is a diagram showing a synchronization signal generation circuit used in a conventional A / D converter, and FIG. 5B is a time chart of the circuit.

[Description of Signs] 1 Master clock generation circuit 2 First frequency dividing means 3 Second frequency dividing means 4 Counter 5 AND gate CCLK Convert clock WCLK Work clock MCLK Master clock

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-3-250924 (JP, A) JP-A-3-18613 (JP, A) JP-A-61-214820 (JP, A) JP-A-57- 194626 (JP, A) JP-A-1-112819 (JP, A) JP-A-3-228473 (JP, A) JP-A-3-83414 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03M 1/00-1/88

Claims (2)

(57) [Claims] 1. Upon receiving an input of a master clock, a new first clock having a different frequency division ratio based on the master clock .
A synchronizing signal generating circuit for generating a pre-second clock, and first frequency dividing means for generating a large first clock division ratio based on the input from the master clock, the master clock and Receiving a clock input from the first frequency dividing means, the master clock is counted.
Divided by the driving edge of the clock from the first frequency dividing means.
Resetting the count value of the circumference, and issuing the second clock edge when the count value reaches a predetermined count value
And a second frequency divider for generating the second clock having a smaller frequency division ratio for resetting a frequency division count value. 2. A method using the synchronization signal generating circuit according to claim 1.
A / D converter, wherein a sample / hold circuit is driven by an output clock of the first frequency dividing means, and an A / D conversion circuit is driven by an output clock of the second frequency dividing means. A / D converter.