JPH10313301A - Phase-locked loop circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain synchronization between a phase signal and a symbol clock by detecting a phase once. SOLUTION: Based on the synchronization between the leading of a received phase signal (PHASE) and a clock (CLK(i)), a detection signal (PHPULSE) denoting the leading of the phase signal is generated by a phase detector 11, and when the leading of the PHPULSE and the leading of the CLK(i) are in matching, the count of the CLK(i) of a counter 12 is reset. At this reset time, a lock generator 13, generates a symbol clock (SYMBOL. CLK). As a result, the synchronization between the phase signal and the symbol clock is obtained in a short time, when a next phase signal is generated after a request of detection of phase.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase synchronization circuit used for a radio or the like.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a conventional phase locked loop circuit. A conventional phase locked loop circuit has a phase signal PHAS
E is a phase comparator 21 connected to the phase comparator 21, a frequency divider 22 having an output of the phase comparator 21 and a clock CLK (ii) having a constant cycle as an input signal, Each of the counters 23 is configured to generate a predetermined clock signal (hereinafter, referred to as “symbol clock SYMB0L.CLK”) using an output as an input signal. The phase comparator 21 outputs a phase delay signal DEC or a phase advance signal INC as a comparison result. Divider 2
2 is a counter clock CNT. CLK is output.

FIG. 4 is a timing chart for explaining the operation of the phase locked loop circuit of FIG. The phase comparator 21 outputs the symbol clock SYMB0L. The rising of CLK is compared with the phase signal PHASE. Symbol clock SYMB0
L. CLK is behind the phase signal PHASE (SY
MB0L. When the rising edge of CLK is in the "H" level section of PHASE), the phase delay signal DEC is output. In addition, the phase signal PHASE is advanced (PH)
B0L. When the rising edge of CLK is within the “L” level section of PHASE), the phase advance signal INC is output. When a phase delay detection signal is received, a frequency-divided clock B having a shorter cycle than the frequency-divided clock A of the frequency divider 22 is output.
When the phase advance detection signal is received, the frequency divider 22 outputs a frequency-divided clock C having a longer cycle than the frequency-divided clock 1.
By inputting the clocks having different frequency division ratios to the counter 23 as the clock CLK (ii), the output counter 2
3 output from the symbol clock SYMB0L. CL
It is possible to synchronize with the phase signal PHASE while changing the cycle of K.

The timing chart of FIG. 5 shows a case where a phase delay has occurred. After the request for the phase detection PD, the phase comparator 21 sets the rising edge of the phase signal PHASE after the symbol clock SYM.
B0L. If there is a rising point of CLK, a phase delay signal DEC is output.

The timing chart of FIG. 6 shows a case where a phase advance has occurred. After the request for the phase detection PD, the phase comparator 21 sets the symbol clock SYM earlier than the rising point of the phase signal PHASE.
B0L. If there is a rising point of CLK, a phase advance signal INC is output.

[0006]

However, according to the conventional phase-locked loop, after the phase signal PDASE is generated several times (four times in FIGS. 5 and 6) after the request for the phase detection PD, Phase signal PHASE and symbol clock SYMB0
L. Since the synchronization of CLK is obtained, it takes time until the synchronization.

An object of the present invention is to provide a phase synchronization circuit which can synchronize a phase signal and a symbol clock by one phase detection.

[0008]

In order to achieve the above object, the present invention provides a phase detector for outputting a detection signal indicating the rising of the phase signal based on a comparison between an input phase signal and a clock. A counter for resetting the count value of the clock when the rise of the detection signal output from the phase comparator coincides with the rise of the clock, and a clock generator for generating a predetermined clock signal at the time when the count of the counter is reset In the phase locked loop circuit.

According to this configuration, when the phase signal and the clock are synchronized, a detection signal indicating the rising of the phase signal is output from the phase detector, and the count value of the clock by the counter is reset based on the detection signal. A predetermined clock signal is generated on condition of this reset. Therefore, after the request for phase detection, synchronization between the phase signal and the symbol clock can be obtained in a short time within one cycle of the phase signal.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a phase locked loop circuit according to the present invention. This phase synchronization circuit includes a phase detector 11, a counter 12, and a clock generator 13. A phase signal PHASE and a clock CLK (i) are input to the phase detector 11, and a rising detection pulse PHPUL of the phase signal is input.
Output SE. The counter 12 has a clock CLK
(I) and the rising detection pulse PHPULSE are input, and the counter value CNT. Outputs VAL. Further, the clock generator 13 outputs the counter value CNT. VAL as an input and the symbol clock SYMB0L. CLK is output. This clock generator 13 operates as a frequency divider.

FIG. 2 is a timing chart showing the operation of the phase locked loop circuit of FIG. The clock CLK (i) is constantly supplied to the phase detector 11. The phase detector 11 outputs a phase signal PHA separately input from the clock CLK (i).
SE, and when the rising of the clock CLK (i) matches the rising of the phase signal PHASE after the request of the phase detection PD, the rising detection pulse PHPUL
Output SE. This rising detection pulse PHPUL
SE is generated until the next clock CLK (i) rises.

The counter 12 has a rising detection pulse P
When the rising edge of HPULSE coincides with the rising edge of clock CLK (i), the counter value at that time (FIG. 2)
Then, the count is reset at the 7th and 9th counts), and the counting is restarted from “0”. The clock generator 13 outputs the counter value CNT. VA
L is detected to be "0", the symbol clock SYMB0L. C
LK is output. The symbol clock SYMB0L. CL
K at the rising edge of the phase signal PHASE and the symbol clock SYMB0L. The rising edges of CLK are coincident, that is, synchronized.

As described above, the phase locked loop circuit of the present invention detects the rising edge of the phase signal PHASE.
2 is reset, and at this point, the symbol clock SYMB
0L. CLK, the symbol clock SY
MB0L. CLK and the rise of the phase signal PHASE are at the same time, that is, they are synchronized. In addition, this synchronization is performed after the request for the phase detection PD
Is obtained at the time when the following occurs, so that phase synchronization can be performed in a short time.

[0014]

As described above, according to the present invention, phase synchronization can be performed at the time when the next phase signal is generated, and the time until the phase signal and the symbol clock are synchronized can be shortened. Become.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a phase locked loop according to the present invention.

FIG. 2 is a timing chart showing an operation of the phase synchronization circuit of FIG.

FIG. 3 is a block diagram showing a conventional phase locked loop.

FIG. 4 is a timing chart illustrating an operation of the phase locked loop circuit of FIG. 3;

FIG. 5 is a timing chart illustrating a state where a phase delay occurs in the phase locked loop circuit of FIG. 3;

FIG. 6 is a timing chart illustrating a state in which a phase advance has occurred in the phase locked loop circuit of FIG. 3;

[Explanation of symbols]

 11 phase detector 12 counter 13 clock generator CLK (i) clock PHASE phase signal PHPULSE rising detection pulse CNT. VAL counter value SYMB0L. CLK Symbol clock

Claims (1)

[Claims] 1. A phase detector for outputting a detection signal indicating a rise of the phase signal based on a comparison between an input phase signal and a clock, and a phase detector for detecting a rise of the detection signal output from the phase comparator and a clock of the clock. A phase synchronization circuit comprising: a counter that resets the count value of the clock when the rising edges coincide with each other; and a clock generator that generates a predetermined clock signal when the count of the counter is reset.