KR950012578B1 - Clock extract circuit of random digital signal - Google Patents

Abstract

an edge detecting unit for generating a change pulse showing a change in data by detecting a raising and dropping point of a digital reception signal to be randomly inputted from outside; a counting unit for counting a phase value of a present signal after counting it from a point of generating the change of the input signal by inputting the change pulse from the edge detecting unit; a phase comparison and control unit for receiving the phase value of a signal generated from the counting unit, comparing the phase difference between the two input signals, and outputting a control pulse to be used for compensating the phase; and a data clock generating and dividing unit for receiving the control pulse and the reception signal, generating a data clock synchronized with the reception signal under control of the phase comparison and control unit, outputting the synchronized reception signal and data clock to the outside, and providing the data clock to the phase comparison and control unit.

Description

Clock extraction circuit of random digital signal and method thereof

1 is an overall configuration diagram of a clock extraction circuit according to the present invention.

2 is a detailed circuit diagram of a clock extraction circuit according to the present invention.

3 is an operation timing diagram.

* Explanation of symbols for main parts of the drawings

1: edge detector 2: counter

3: Phase Comparison and Control Unit 4: Data Clock Generation Divider

The present invention relates to a clock extraction circuit and a method for generating a clock for tracking a sampling point of a random input signal.

Conventional clock extraction circuits have a problem in that stable clocks cannot be extracted by continuous same-level signals or noise because they depend on the level change or zero crossing of the received signal.

Therefore, in order to solve the problems of the prior art, the present invention, after detecting a transition of input data, calculates a phase value with a counter to determine a phase difference with the data clock generation divider, and then the data according to the difference. It is an object of the present invention to provide a clock extraction circuit and a method for centrally sampling input data by delaying or advancing the timing of a sampling clock.

The clock extraction circuit according to the present invention for achieving the above object, in the clock extraction circuit of a randomly input digital signal, a transition indicating a data change by detecting the rising and falling time of the digital reception signal randomly input from the outside Edge detection means for generating a pulse; Counting means for receiving a transition pulse, which is an output of the edge detection means, and starting the counter from the time when the transition of the input signal occurs to calculate and output a phase value of the current signal; A phase comparison and control means for receiving a phase value of a signal having a transition which is an output of the counting means, receiving a data clock, determining a phase difference between the two input signals, and outputting a control pulse for phase compensation; Receives a control pulse that is an output of a control means and receives the received signal to determine a phase comparison time point, and generates a data clock synchronized with the received signal according to the phase comparison and control of the control means to generate a synchronized receive signal and a data clock. It is characterized in that it comprises a data clock generation and distributing means for outputting to the outside, and also provides a data clock to the phase comparison and control means.

In addition, the clock extraction method according to the present invention for achieving the above object by using the clock extraction circuit, in the clock extraction method applied to the clock extraction circuit of a randomly input digital signal, the data clock generation and distribution means initially A first step of free-running and detecting a level change of an input signal; A second step of calculating a phase value after initializing the operation of the counting means after performing the first step; A third step of generating a reference pulse at the center point of the data clock by the data clock generation dispensing means after performing the second step; After performing the third step, the phase comparison and control means compares the phase difference between the data clock and the input signal, and if the phase of the data clock is delayed from the input signal, the data clock generation / distribution means is subjected to period / count aberration (T / N). If the phase of the data clock is more advanced than the input signal, move the data clock generating / distributing means backward by the period / count aberration (T / N). If the phase of the input signal and the data clock is the same, locking A fourth step of treating it as); And a fifth step of continuously detecting the level change of the input signal after the fourth step, and repeatedly performing the second step if there is a level change, and repeatedly performing the third step if there is no level change. It is done.

Hereinafter, with reference to the accompanying drawings will be described an embodiment according to the present invention;

1 is a block diagram showing the overall configuration of a clock extraction circuit according to the present invention, where 1 is an edge detector, 2 is a counter, 3 is a phase comparison and control unit, and 4 is a data clock generation divider.

As shown in the drawing, the present invention provides an edge detector 1 and an edge detector 1 for generating a transition pulse indicating a data change by detecting rising and falling time points of a digitally received signal randomly input from the outside. Counter (2) which receives the input transition pulse and starts the counter from the time when the transition of the input signal occurs, calculates and outputs the phase value of the current signal, and inputs the phase value of the transition signal that is the output of the counter (2). Receive a separate data clock and determine the phase difference between the two input signals to output the control signal for phase compensation and the phase comparison and control unit (3) and the output control pulse of the phase comparison and control unit (3) Receiving the received signal to determine the phase comparison time point, and generates and outputs a data clock synchronized with the received signal according to the phase comparison and the control of the control unit (3) On the other hand, the phase comparison and the control section 3 also has a data clock generation divider 4 that provides a data clock.

In the present invention, the loop speed for tracking the change in the input frequency is +/- T / N depending on the presence or absence of a phase difference for every data transition. Where T is the period and N is the aberration of the counter 2. And even if there is an instantaneous error in the system, the locking is stored for a certain period of time so that the overall phase does not suddenly escape.

The procedure of the clock extraction method applied to the clock extraction circuit configured as described above is as follows.

1) Initially, the data clock generation divider 4 is free-running.

2) Detect changes in the level of the input signal.

3) After the operation of the counter 2 is initialized, the phase value is calculated.

4) In the data clock generation divider 4, a reference pulse is generated at the center of the data clock.

5) Phase comparison and the control section 3 compares the phase difference between the data clock and the input signal.

6) If the phase of the data clock is delayed from the input signal, the data clock generation divider 4 is moved forward by T / N. If the phase of the data clock is advanced from the input signal, the data clock generation divider 4 Move backward by T / N. If the phase of the input signal and the data clock are the same, it is locked.

7) If the level change of the input signal is continuously detected, repeat the procedures of 3), 4), 5), and 6) above. If not, repeat the procedures of 4), 5), and 6).

2 is a detailed circuit diagram of the clock extraction circuit according to the present invention as shown in FIG. 1, and FIG. 3 is a signal timing diagram.

The master clock (MCK) used in the circuit of the present invention shown in the drawing uses the output of a stable local oscillation circuit and has an N multiple relationship with the data clock and locks the data clock extracted according to the N value. Speed is different. Where B is 64, so the data clock width is 64 times the master clock width.

The operation of each functional unit will be described with reference to the circuit diagram of FIG. 2 and the timing diagram of FIG.

The edge detector 1 is composed of a shift register using two D-type F / Fs connected in series, and one XOR gate connected to an output terminal of the two flip-flop outputs, and has a master clock when there is a data transition. It generates a pulse of width synchronous with and whose period and magnitude are the same.

The front D-type flip-flop acts to synchronize the incoming input data to the master clock (Sig1), and the rear-end D-type F / F delays the input data by one clock of the master clock (Sig2). The XOR gate detects rising and falling transitions to output a pulse (TP), which is used as a signal for resetting the counter 2. The circuit of the edge detection unit 1 as described above has a very spaced configuration in which the detection of signal transition is never missed.

The counter (1 $ 1) is composed of a C64BCRD IC chip, and is a circuit for repeating the count from 0 to 63 (N-1), and the clock of the counter is used by using an inverted phase from the edge detector clock. The edge detection signal can be accurately recognized at the center thereof.

The counter 2 may be connected in series to the 74161 in two or other ways, and initially performs free-running operation but restarts whenever there is an edge detection signal TP and repeats the counting operation. Here, when restarting, the initial value is "0" and the N value is 64. (Hereinafter, N = 64 is set and explained.) Each bit output value of the 64 counter (2) Q ₅ .Q ₄ .Q ₃ .Q ₂ . Q ₁ .Q ₀ becomes the phase value of the input data and is passed to the phase comparison and control unit 3.

The judgment of the phase is divided into forward, backward, and center subdivisions based on the value of the counter 2 (QM (5: 0)) of 32. The center point is the logical combination of AND4 and NAND8 by Sig3 (phase value = 32). Make it.

The front is 0 ~ 31 phases and controlled by the logic function of _Sig * _Q _5. The reference pulse (RP) which delays the TC1 signal, which is the output of the data clock generator divider 4, to D flip-flop and the output SIG3 of NAND8. Compare (AND3) to produce a phase control pulse called LAT.

The back is 32 ~ 63 phases and controlled by the logic function of _Sig * _Q _5. Compared with the reference pulse which delayed TC1 signal, which is the output of data clock generator divider 4, with D flip-flop, the output SIG3 of NAND8 was compared. (AND3), produces a phase control pulse called ELY.

The roles of the generated LAT and ELY signals are used to control the upper operation clock SCK input to the data clock generation divider 4 to delay or advance the data clock.

These two signals are input to the circuits AND2 and AND3 for controlling SCK in synchronization with a clock four times faster than the master clock. The operation of this part is shown in (a) and (b) of FIG.

First, if the counter (2) is ahead of the reference pulse, the data clock is faster (forward), so the sampling time of the data clock should be delayed backward.

At this time, the circuit operation becomes LAT = 1, ELY = 0, and both outputs of AND2 and AND3 become "0" while LAT = 1, and as a result, SCK is lost by one clock. Therefore, the data clock is shifted backward by T / 64 (see Fig. 3 (a)). Second, if the counter (2) value is behind the reference pulse, the data clock is delayed (delayed). You have to pull the point in.

At this time, LAT = 0, ELY = 1, MCK is input, AND3 output is "0", and MCK2 input AND2 output is MCK2 signal twice as fast as the master clock. The SCK is inserted one clock. Thus, the data clock is shifted forward by T / 64 (see Figure 3 (b)).

Thirdly, if LAT = 0 and ELY = 0, the result is logically multiplied so that the output of 2 is "0", and the output of AND3 is the master clock used as the upper operation clock (SCK) of the divider and the sampling point of the extracted data clock is It is locked to the input signal.

The data clock generation divider 4 is operated with a divider for dividing the master clock 64 and a logic circuit for generating a sampling time point.

The divider (1 $ 2) consists of a C64RCRD IC chip so that the highest divider value (Q ₅ ) becomes the data clock, and when the divider value (QD (5: 0)) is 63, AND4 and AND6 are logically combined to generate TC1 pulses. A reference pulse (RP) for phase determination is generated by delaying the signal to a master clock (MCK) whose phase is inverted through the D flip flop. The reference pulse is one times the magnitude of the master clock period and is input to the phase determination and control section 3. The reference pulse is the phase at which the phase is judged and the rising point is the sampling point of the data.

The last INV logic gate is used to invert the phase of the data clock to accurately sample the input data.

Since the upper operation clock of the frequency divider is controlled by the phase comparison and the control unit 3, the division operation is delayed or advanced or normal operation is performed accordingly.

Therefore, the duty of the output data is 50% in the locking operation and (50 + -T / N × 100)% in the delay or advance. Since every data moves only + -T / N per clock, if the phase value due to the reference pulse and the normal signal transition is m times the master clock (but m = <N2), m × until the phase difference becomes “0” It takes T time.

Therefore, in the present invention configured and operated as described above, even if the noise smaller than the master clock is caught in the edge detector 1 in advance and the noise larger than the master clock occurs, the clock divider sets the sampling time at the current position at T / 64. It is almost impossible to lose the sampling point or insert or lose data, and once locked, there is an effect of recovering the data clock without missing the sampling point even in the strong shaking of the input data.

Claims (3)

A clock extraction circuit for a digital signal input randomly, comprising: edge detection means (1) for detecting a rising and falling time point of a digital reception signal randomly input from the outside to generate a transition pulse indicating a data change; Counting means (2) for receiving a transition pulse, which is the output of the edge detection means (1), and starting the counter from the time point at which the transition of the input signal occurs to calculate and output the phase value of the current signal; Phase comparison and control means (3) for receiving a phase value of a signal having a transition which is the output of the counting means (2), receiving a data clock, determining a phase difference between the two input signals, and outputting a control pulse for phase compensation (3). ); And a control pulse that is an output of the phase comparison and control means 3, receives the received signal, determines a phase comparison time point, and synchronizes the received signal according to the control of the phase comparison and control means 3. Clock extraction, characterized in that it comprises a data clock generation and distributing means (4) which generates a clock and outputs the synchronized received signal and the data clock to the outside and provides the data clock to the phase comparison and control means (3). Circuit. 2. An edge detector according to claim 1, wherein said edge detection means (1) comprises: a shift register using two D-type F / Fs connected in series; And an XOR gate connected to an input terminal of an output terminal of the two flip-flops. A clock extraction method applied to a clock extraction circuit of a randomly input digital signal, comprising: a first step of initially free-running the data clock generation and distributing means (4) and detecting a level change of an input signal; A second step of calculating a phase value after initializing the operation of the counting means (2) after performing the first step; A third step of generating a reference pulse at the center point of the data clock by the data clock generation and distributing means (4) after performing the second step; After performing the third step, the phase comparison and control means 3 compares the phase difference between the data clock and the input signal, and if the phase of the data clock is delayed from the input signal, the data clock generation / distribution means 4 is cycled / counted. If the phase of the data clock is advanced from the input signal, the data clock generating / distributing means 4 is moved backward by the period / count aberration (T / N) and the input signal A fourth step of treating as locked if the data clocks are in phase; And a fifth step of continuously detecting a level change of an input signal after the fourth step and repeating the step from the second step if there is a level change, and repeating from the third step if there is no level change. Clock extraction method.