JPS6236586A - Digital time counter - Google Patents

Abstract

PURPOSE:To obtain a time-counting apparatus with a very low power consumption, by using two kinds of low-frequency signals to obtain the accuracy the same as would be when a very high frequency signal is used. CONSTITUTION:The output of a first oscillator 1 always oscillating is counted with a first counter 2 and the counts are latched with a first latch circuit 3 by a signal intended to count time. The latch output gives the upper position (approximate value) of the counts. A second oscillator 6 is started by the signal intended to count time to count the output thereof with a second counter 8. The output of the first oscillator is compared in the phase with the output of the second oscillator by a phase comparator 7. When the coincidence or advance in the phase is given, a latch command is provided to a second latch circuit 9, which latches the counts of the second counter 8. The value gives the lower position (precision value) of the counts.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a digital timekeeping device that detects with high precision the time at which a pulse signal arrives. It can be applied to all devices that are being controlled. For example, if the period of the rotary encoder pulses applied to the motor is measured and the motor is controlled based on that value, it becomes possible to control the rotational speed of the motor with extremely high precision.

BACKGROUND OF THE INVENTION FIG. 4 shows an example of a conventional digital timekeeping device. The output pulses of the oscillator 101 are input to a counter 102, and the number of pulses is repeatedly counted. The output of the counter 102 is input to a latch circuit 103. On the other hand, the timed signal is input to the latch circuit 103, and when this signal rises.

The count value of the counter 102 is ratted. Latch circuit 10
As the output of step 3, the clock count value corresponding to the time when the timed signal was input is obtained, so for example, by sequentially finding the difference from the previous latch output, it is easy to find the period of the timed signal. can be realized. Note that when the maximum count value is exceeded, the counter becomes zero and starts counting again, but even in this case, the cycle can be obtained by hypothetically assuming the upper digits and finding the difference in the same way as calculating by hand. Generally, microcomputers and the like operate in this way, so there is no problem in this regard unless the cycle is long beyond the counting range of the counter.

Problems to be Solved by the Invention Now, in conventional odor makers, the timing accuracy is limited by the oscillation frequency of the oscillator 101. That is, the oscillator 10
A time shorter than one signal period cannot be detected. Therefore, if timekeeping accuracy is required, the oscillation frequency of the oscillator 1o1 must be made sufficiently high.

However, when increasing the oscillation frequency, the number of circuit elements that can be used is limited, power consumption increases, and in extreme cases, a cooling device may be required.

Means for Solving the Problems In order to solve the problems in the prior art, the present invention provides a first oscillator with a relatively low frequency, and a frequency close to that of the first oscillator, which starts oscillation by the timed signal. a second oscillator, a means for comparing the output phases of the two oscillators, and a period from when the timed signal is input until the phases of the two signals match by the phase comparison means; A means is provided to count the number of outputs.

Function: It has a counter that counts the output of the first oscillator that is constantly oscillating, and latches the counted value using the timed signal. This latch output becomes an upper value of the time value, that is, an approximate value. Further, the second oscillator is activated in response to the clocked signal, and the output of the second oscillator is counted by the second counter. Furthermore, it has a phase comparator that compares the phase of the first oscillator output with the second oscillator output, and the phase comparator is configured to compare the phase of the first oscillator output with the second oscillator output, and the second oscillator output has a phase comparator that compares the phase of the first oscillator output with the second oscillator output. The second oscillator output is counted, and the counting result is ratted, and is used as a lower value of the time value, that is, a precision value.

If the output period of the first oscillator is TA% and the output period of the second oscillator is TB (TB<TA), the two signal phases shift by TA-TB per period. Therefore, if the second oscillator is started by the timed signal that enters in the middle of the output of the first oscillator, the phase of the Ryogawa force signal will change to the second oscillator.
T per period from the state where the oscillator output is delayed.
The phase approaches A-TB at a time, and finally changes from a delayed state to a coincident state and then to an advanced state. The number of second oscillator output pulses until phase matching corresponds to how many times (TATB) there is a time delay. Therefore, the resolution that can be measured is TA
-TB, and if it is set to TA~TB, the resolution will be significantly improved.

Generally, when the first latch value is n and the second latch value is m, the input time t of the signal under test is given by the following equation.

t=n TA + m (TA "B") but -'
rA>TB Note that t=0 here corresponds to the time at which the first counter becomes zero. To start timekeeping at an arbitrary time, first read the start time, read the end time in the same way, and calculate the time based on the difference.

Embodiment FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a timing chart showing the operating principle of the embodiment.

The first oscillator 1 is always operating, and its output φA is input to the first counter 2 and phase comparator 7, respectively. The first counter 2 repeatedly counts the output of the first oscillator 1. The first one is input to the note circuit 3. That is, the count value of the first counter 2 is ratted based on the clocked signal. Everything up to this point is exactly the same as the conventional example. In other words, it is a timing device having a resolution of the output cycle of the first oscillator 1.

First, the timed signal starts the oscillation of the second oscillators, and is inverted by the inverter 10 to generate the second oscillator.
The count of counter 8 is cleared.

That is, the second counter 9 is kept at zero until the second oscillator 6 starts oscillating. When the timed signal is input, the second oscillator 6 starts oscillating and sends its output signal φB to the second counter 8 and the phase comparator 7. The second counter 8 then starts counting the output φB of the second oscillator 6. The output of the second counter 8 is input to a second latch circuit 9. The phase comparator element is
The phase of the output φB of the second oscillator 6 with respect to the output φB of the first oscillator 1 is compared. When the phases of the output φA and the output φB are equal, or when φB is in an advanced state, the latch circuit 9 outputs a Herat command. Therefore, the latch circuit 9 latches the number of pulses of the output φB of the second oscillator 6 from when the timed signal is input until the phases of the two oscillation outputs match. The output of this latch circuit 9 is
Gives more precise timing values.

FIG. 2 is a timing chart for the configuration of FIG. 1. The first oscillator 1 is always oscillating, and the counter 2 is counting. Here, the period TA is 20
0 n5ec (frequency 6MHz). Here, when the timed signal enters in the middle of the count value (n) of φA, the count value (n) is latched in the first latch circuit 3. At the same time, the second oscillator 6 starts oscillating, and the clear command for the second counter 8 is released. The period TB of the second oscillator 6 is 190 n5ec (therefore, the period is approximately 5.263158 MHz, and
The final resolution will be 10 n5ec. ). The second counter 8 starts counting the output φB. The phase comparator γ compares the phases of the first oscillator output φ and the second oscillator output φB. That is, the count value of the second counter 8 is (0
) to (5), φB was delayed τ, but the count value was (
If the phases match in 6) and the count value becomes (a), φB is advancing. The phase matching signal causes the count value (6) to be changed to the second
The latch circuit 9 is launched.

In this case, the input time of the timed signal is 6X10ns=a after the (n)th pulse is input from the first oscillator 1.
After rtsec.

As described above, by using two oscillation outputs of about 5 MHz, a resolution of 10 nS, that is, the same accuracy as using oscillation outputs equivalent to 100 MHz can be obtained.

By determining the time difference between the two timed signals obtained by this method, it is possible to measure the pulse interval.

In addition, as a specific circuit example in FIG.
The oscillator 6 and τ can be realized by a ringing crystal oscillator or the like.

In FIG. 2, the case where TA>TB was explained, but in FIG. 3, the case where TA<TB is shown. In this case, since the phase of φB lags behind φA, the count value of the second counter can be loaded into the second latch circuit at the timing when the phase changes from an advanced state to a matched or delayed state. .

At this time, the input time t of the timed signal is given by t=(n+1)TA-m(TBTA). (As mentioned above, t=o corresponds to the moment when the first counter becomes zero.) Note that the second oscillator was explained as starting oscillation by the timed signal.
Any oscillator whose oscillation phase is reset by the timed signal may be used.Advantageous Effects of the Invention As explained above, the present invention allows low frequency signals to be
By using different types of clocks, it is a timekeeping device that can achieve the same accuracy as using very high frequency signals, and its effects are extremely significant.

In particular, when using a logic circuit element such as 0MO5, the power consumption increases in degrees Celsius corresponding to the frequency at which the logic is inverted, but in the present invention, the actual frequency at which the logic is inverted is low, so a complicated semiconductor manufacturing process is not required. It is easy to implement and can be configured with extremely low power consumption.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. FIGS. 2 and 3 are timing charts showing the operation of the same embodiment, and FIG. 4 is a block diagram showing the configuration of the conventional example. 1.6...Oscillator, 2,8...Counter, 3゜9...Latte, 7...Phase comparator. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 4

Claims (4)

[Claims] (1) A first oscillator that generates a signal with a period T_A, a first counter that counts the output of this first oscillator, and a first latch means that captures the count value n of this first counter using a timed signal. , the period T_B(
a second oscillator that starts oscillating a signal such that T_B<T_A and non-integer multiples of each other); a second counter that counts the output of the second oscillator; and an output of the second oscillator relative to the output signal of the first oscillator. means for detecting the phase of the signal; the phase detecting means detecting the second oscillator output relative to the first oscillator output;
When the phase of the oscillator output changes from a delayed state to a coincident state or an advanced state, the count value m of the second counter
What is claimed is: 1. A digital timekeeping device, comprising a second latch means for taking in the timed signal, and determining the input time of the timed signal using the following equation: t=nT_A+m(T_A−T_B). (2) The digital timekeeping device according to claim 1, wherein the oscillation phase of the oscillation output of the second oscillator is reset by the timed signal. (3) A first oscillator that generates a signal with period T_A, a first counter that counts the output of the first oscillator, and a first latch unit that captures the counted value n of the first counter using a timed signal. , the period T_B(
a second oscillator that starts oscillating a signal such that T_A<T_B and non-integer multiples of each other); a second counter that counts the output of the second oscillator; and an output of the second oscillator relative to the output signal of the first oscillator. means for detecting the phase of the signal; the phase detecting means detecting the second oscillator output relative to the first oscillator output;
a second latch means that captures the counted value m of the second counter when the phase of the oscillator output signal changes from an advanced state to a coincident state or a delayed state; A digital timekeeping device characterized in that the calculation is performed using the arithmetic expression t=(n+1)T_A+m(T_A-T_B). (4) The digital timekeeping device according to claim 3, wherein the oscillation phase of the oscillation output of the second oscillator is reset by the timed signal.