JP4999232B2 - Test system for analog / digital hybrid IC - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an analog / digital hybrid IC test system for testing an analog / digital hybrid IC equipped with an analog circuit and a digital circuit (logic circuit).
[0002]
[Prior art]
FIG. 2 shows a schematic configuration of a conventional analog / digital hybrid IC test system. The analog / digital hybrid IC test system is equipped with a logic test system (digital test system) 100 and an analog test system 200. These test systems 100 and 200 are placed under the control of the main controller 300 and are tested. Test the operation of the digital and analog circuits of the device DUT. PB represents a performance board that electrically and mechanically supports the device under test DUT.
[0003]
The logic test system 100 includes a pattern generator 101, a waveform formatter 102, a driver 103, an analog comparator 104, a logic comparator 105, a failure analysis memory 106, and the like.
The pattern generator 101 generates digital application pattern data to be applied to the device under test DUT. The waveform formatter 102 converts the pattern data generated by the pattern generator 101 into a pattern signal having an actual waveform, and applies the pattern signal to the digital input terminal of the device under test DUT through the driver 103.
[0004]
The response signal output to the digital output terminal (generally used as an input terminal and an output terminal) of the device under test DUT is a logic signal having a normal L logic voltage and a normal H logic voltage in the analog comparator 104. If the comparison result is good, the logical comparator 105 compares it with the expected value output from the pattern generator 101. If a mismatch is detected, it is determined that the operation is defective. The defect analysis memory 106 is a memory for storing pattern data output from the pattern generator 101 when a mismatch is detected by the logical comparator 105. By reading the pattern data stored in the failure analysis memory 106 after the test is completed, the failure portion of the digital circuit of the device under test DUT is analyzed.
[0005]
The analog test system 200 includes an event sequencer 201, an analog waveform generator 202 composed of a digital-analog converter, and a digitizer 203.
The analog waveform generator 202 and the digitizer 203 are provided corresponding to the number of analog signal input pins and the number of analog signal output pins of the device under test DUT, and the analog waveform generator 202 is connected to the analog signal input pins. Input an analog signal to the signal input pin. Also, a digitizer 203 is connected to the analog signal output pin, the analog signal output from the device under test DUT is received and digitized by the digitizer 203, the digital waveform data obtained by the AD conversion is taken into a memory or the like, and this waveform data Is compared with the expected value to determine whether the analog circuit is good or bad.
[0006]
The main controller 300 is constituted by a computer system, and a main program 301 is installed in this computer system. In the main program 301, a start / stop command 302 of the logic test system 100 and a start / stop command 303 of the analog test system 200 are described, respectively, according to the start / stop commands 302 and 303 described in the main program 301. Start / stop control is performed.
In the activated state, the pattern generator 101 of the logic test system 100 continues to generate test patterns in accordance with the pattern generation program 304 described in the main program 301.
[0007]
In the analog test system 200, start / stop control is performed by inputting a start / stop command from the main controller 300 to a control program 204 provided in the event sequencer 201. During startup, an analog test is executed according to the description of the control program 204.
[0008]
[Problems to be solved by the invention]
As described above, since both the logic test system 100 and the analog test system 200 are controlled to start / stop in accordance with the start / stop commands 302 and 303 described in the main program 301, for example, the analog test and the logic test are started simultaneously. Alternatively, in order to start a logic test in synchronization with a certain timing during the analog test, the analog test system start / stop command 303 and the logic test system start / stop command 302 described in the main program 301 are used. Needs to be corrected (debugged). It takes a lot of time for this correction, and depending on the start / stop commands 302 and 303 of the analog test system and logic test system described in the main program 301, the start and stop timings of the analog test system and logic test system Since it is difficult to accurately match the logic test timing and the analog test timing, the test results are not reliable.
[0009]
The object of the present invention is to enable the start / stop control of the analog test system and the logic test system to be changed with a simple scan, and to synchronize the timing of synchronization between the logic test system and the analog test system with high accuracy. It is intended to provide a test system for digital hybrid IC.
[0010]
[Means for Solving the Problems]
According to the first aspect of the present invention, a logic test system and an analog test system are provided, and the analog test system is equipped with an analog test program for controlling its own operation, and the logic test control program is included in the analog test control program. A test system for analog / digital hybrid ICs is described in which a start / stop command for synchronization that controls start / stop is synchronized, and a logic test system is started / stopped from a control program for analog test. .
[0011]
[Action]
According to the test system for an analog / digital hybrid IC according to the present invention, the start / stop command for synchronization of the logic test system is described in the control program for the analog test system installed in the analog test system, and the logic test system is started. Since the stop control is performed, the logic test system start / stop command can be generated in correspondence with the operation state of the analog test system.
As a result, it becomes easy to synchronize the start and stop operations of the logic test system and the analog test system, and the test reliability can be improved. In addition, since the logic test system start and stop control and analog test system start and stop control can be managed only by the control program provided in the analog test system, the program management is unified and the program management is simplified. The advantage that can be obtained is also obtained.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows an embodiment of a test system for an analog / digital hybrid IC according to the present invention. Parts corresponding to those in FIG. 2 are denoted by the same reference numerals.
In this invention, a part of the control program 204 mounted in the event sequencer 201 constituting the analog test system 200 is synchronized with the operation of the analog test system 200 to start and stop the logic test system 100 and start / stop for synchronization. This is characterized in that the command 501 is described.
[0013]
Since the synchronization start / stop command 501 is written in the program for operating the analog test system 200, it can be executed in synchronization with the operation timing of the analog test system 200 with high accuracy. For example, a start command can be sent to the logic test system 100 in synchronism with the timing at which the analog waveform generation start of the analog test system 200 starts.
Therefore, the analog test and the logic test can be accurately timed, so that the reliability of the test can be improved. In addition, since the program can be unified with the control program 204, an advantage that the management of the program can be simplified can be obtained.
[0014]
【Effect of the invention】
According to the present invention, the synchronization start / stop command 501 for starting / stopping the logic test system in synchronization with the control program 204 installed in the event sequencer 201 is described. Is described in the analog test system control program. As a result, the data is read out in synchronization with the operation of the analog test system 200 with high accuracy and sent to the logic test system 100. It is possible to synchronize the timing of starting the test system 100 with high accuracy, and to obtain an advantage of obtaining highly reliable logic test and analog test results.
[0015]
In addition, since the logic test system 100 and the analog test system 200 are operated in a unified manner with the control program 204, there is an advantage that the management of the program becomes easy.
[Brief description of the drawings]
FIG. 1 is a block diagram for explaining an embodiment of the present invention.
FIG. 2 is a block diagram for explaining a conventional technique.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 100 Logic test system 101 Pattern generator 102 Waveform formatter 103 Driver 104 Analog comparator 105 Logic comparator 106 Defect analysis memory 200 Analog test system 201 Event sequencer 202 Analog waveform generator 203 Digitizer 204 Control program 300 Main controller 301 Main program 302 Logic test system start / stop command 303 Analog test system start / stop command 304 Pattern generation program 501 Synchronization start / stop command

Claims (2)

Applying a digital pattern signal to the device under test, comparing the response signal from the device under test with an expected value, and a logic test system for determining pass / fail of the device under test,
A control program that controls its own operation is installed, an analog signal is applied to the device under test, and the response signal from the device under test is compared with an expected value to determine whether the device under test is good or bad A test system,
A main controller that executes a main program in which the analog test system start / stop commands are described;
With
The said control program, said logic test system to synchronously start / stop control for synchronizing a start / stop command is written, the analog test system executes the control program, a start for the synchronization / A test system for an analog / digital hybrid IC that controls start / stop of the logic test system in synchronization with the execution timing of a stop command . In the control program, the start and stop control of the logic test system and the start and stop control of the analog test system according to the start / stop command of the analog test system are described,
2. The analog / digital hybrid IC test system according to claim 1, wherein the analog test system controls the start and stop of the logic test system and the analog test system by executing the control program.

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