JP2831081B2 - IC test equipment - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC test apparatus for testing whether an IC such as a memory operates normally.

[Prior Art] FIG. 3 shows a configuration of a conventional IC test apparatus. In the figure, 10 is a timing generator, 20 is a pattern generator, 30 is an IC under test,
Numeral 40 indicates a logical comparator, and numeral 50 indicates a delay circuit.

The timing generator 10 outputs various timing signals, the timing signals of the various is provided to the pattern generator 20, a test pattern signal P _a of the pattern generator 20 is applied to the tested IC 30, the logic comparator 40 The expected value pattern signal _Pb to be given is output.

Tested IC30 is temporarily stores the test pattern P _a supplied from the pattern generator 20, and applies the read output to the logic comparator 40.

Logic comparator 40 compares the expected value pattern signal P _b that is output a response output signal output from the test IC30 from the pattern generator 20, good to the output terminal 60, and outputs-determination results.

The above description is a normal operation situation when the IC under test 30 is tested.

The part targeted by the present invention is the configuration of the part that takes in the expected value pattern into the expected value pattern generator 20B provided in the pattern generator 20.

That is, prior to the start of the test, an IC determined to be non-defective is mounted on the mounting portion of the IC under test 30 in advance, and the read output of the IC determined to be non-defective is used as an expected value pattern signal as an expected value pattern signal. An operation (hereinafter referred to as a copy operation) to be taken into 20B is performed.

 The copying operation of the expected value pattern signal will be described below.

In order to perform the copy operation, a wiring 61 is provided from the output terminal 60 to the expected value pattern generator 20B, and the logical comparison result is fed back to the expected value pattern generator 20B through the wiring 61.

As shown in FIG. 4, the expected value pattern generator 20B converts one of the memory data register 21, the data buffer register 22, and one of the data stored in these two registers 21 and 22 to perform the copy operation. It is composed of a multiplexer 23 for selection and an expected value pattern memory 24 for storing data selected by the multiplexer 23 as an expected value pattern.

The control terminal S of the multiplexer 23 is connected to the wiring described above.
61 is connected to supply the judgment output of the logical comparator 40. Here, it is assumed that when the logical comparator 40 outputs a good (matching) determination result, L logic is output, and when a bad (mismatching) determination result is output, H logic is output.

The multiplexer 23 selects the memory data register 21 when the logical comparison output is good, and selects the data buffer register 22 when the logical comparison output is bad, selects the data stored in each, and stores the data in the expected value pattern memory. twenty four
The operation of writing to is performed.

A test pattern signal to be applied to the IC under test 30 is written in advance in the entire area of the expected value pattern memory 24, and its read output is given to the logical comparator 40 as an expected value pattern, and the output is fed back to the memory data register 21. Stored in the memory data register 21.

On the other hand, a pattern signal completely opposite to the test pattern signal is stored in the data buffer register 22. When the logical comparator 40 outputs a determination result of failure, the multiplexer 23 selects the data buffer register 22 and performs a test. A signal opposite to the pattern signal is selected by the multiplexer 23 and written into the expected value pattern memory 24 as an expected value pattern signal.

Thus, the expected value pattern is copied to the expected value pattern memory 24.

FIG. 5 shows a timing chart when the expected value is written in the expected value pattern memory 24. FIG. 5A shows a clock supplied from the timing generator 10 to the pattern generator 20.
Indicates CLK.

By receiving the clock CLK, a write signal WE to be supplied to the expected value pattern memory 24 is generated. The write signal WE is generated from the leading edge of the clock CLK after a delay of DL _3.

In the cycle of the _first clock CLK1 at the start of the copy operation, the test pattern signal has not been given to the IC under test 30 yet. Therefore, the logical comparator 40 does not output the comparison result.
For this reason, for example, assuming that the logical comparator 40 outputs L logic as its comparison output as shown in FIG. 5E, the pattern signal stored in the memory data register 21 is written in the expected value pattern memory 24. However, the pattern signal written at this time is not handled as a regular pattern signal.

A time DL ₃ has elapsed since the _second clock CLK ₂ was generated, and a second write signal WE ₂ is generated. The first cycle is delayed by a delay time DL ₁ from the timing of the trailing edge of the write signal WE _2. The test pattern signal P _A1 is output from the test pattern generator 20A as shown in FIG. 5B and applied to the IC under test 30.

Tested IC30 outputs a response signal P _B1 shown in FIG. 5 C at timing delayed a short time after the given test pattern signal P _A1.

It tested IC30 outputs a response signal P _B1, the response signal PB ₁
At a stable timing, the strobe pulse STB (FIG. 5D) is output, and the strobe pulse STB is supplied to the logical comparator 40. At the timing of the leading edge of the strobe pulse STB, the logical comparator 40 receives the strobe pulse STB from the pattern memory 24. Expected value pattern and response time P output by IC under test 30
_B1 and a comparison result CPD _{1 in the} first cycle shown in FIG. 5E after a delay time of DL ₂ from the leading edge of the strobe pulse STB.
Is output.

Writing to the expected value pattern memory 24 which is performed using the comparison result CPD ₁ of the first cycle is written at the timing of the write signal WE ₂ in the second cycle.

Writing to the expected value pattern memory 24 using the comparison result CPD ₂ in the second cycle is performed by the write signal WE _{3 in the} third cycle.

"Problems to be Solved by the Invention" As described above, in the conventional copy operation, the write signal WE is generated by the clock CLK, and thus the timing of writing to the expected value pattern memory 24 is delayed by one cycle.

As a result, in the last example of the next cycle diagram, the clock is not output in the fourth cycle, so that the write signal WE cannot be generated, and the expected value pattern is copied using the logical comparison result CPD ₃ in the last cycle. The inconvenience that cannot be done arises.

That is, as shown in FIG. 5, assuming that outputs a test pattern of 3 cycles, the clock only be generated until CLK _3. Therefore since the last write signal WE ₄ is not generated, there is a drawback that can not be copy operation expected value pattern using the comparison result of the third cycle.

It is an object of the present invention to eliminate this disadvantage and to provide an IC test apparatus capable of performing a copy operation in the last cycle.

[Means for Solving the Problems] In the present invention, a test pattern is given to an IC having no defect, a response output of the test pattern is compared with an expected value pattern in a logical comparator, and a test pattern is determined in accordance with a match or mismatch of the comparison result. Comparison between the logic comparator and the IC tester that obtains the expected value pattern by selecting whether to copy the same pattern as the signal as the expected value pattern or to copy the pattern opposite to the test pattern as the expected value pattern The present invention proposes an IC test apparatus configured to perform a copy operation in synchronization with a command signal.

According to the IC test apparatus of the present invention, since the copy operation is executed in synchronization with the comparison command signal given to the logical comparator, there is an advantage that the copy operation in the last cycle can be executed reliably.

FIG. 1 shows an embodiment of the present invention. In the figure, parts corresponding to those in FIG. 3 are denoted by the same reference numerals.

In the present invention, the logic comparator
The comparison command signal STB given to 40 is also given to the pattern generator 20, and an operation of taking in the expected value pattern generator 20B in synchronization with the comparison command signal STB, ie, a so-called copy operation is performed.

As shown in FIGS. 2A and 2B, the clock CLK in the first cycle
₁ test pattern signal in the first cycle to be tested IC30 is given at a timing delay time DL ₁ elapsed since given, the response signal of the first cycle shown under test IC30 in Figure 2 C is output.

The comparison command signal STB is supplied from the timing generator 10 to the logical comparator 40 at a timing when the response signal is stabilized.

1 after the lapse of delay time DL ₂ from the leading edge of comparison command signal STB
The comparison result CPD _{1 in the} cycle is output from the logical comparator 40, and the comparison result CPD ₁ is fed back to the pattern generator 20.

In the present invention, as shown in FIGS. 2D and 2F, the write signal WE ₁ is delayed after a delay time of DL ₃ from the leading edge of the comparison command signal STB.
Are generated, that is, the write signals WE _{1 to} WE are synchronized with the comparison command signal STB.
₃ to generate, copying operation with the write signal WE ₁ ~WE _3.

In the copy operation, if the result of the logical comparison is good (coincidence) as described in the background art, the same pattern as the test pattern signal stored in the memory data register 21 shown in FIG. Expected value pattern memory
24 and the result of the logical comparison is not correct (mismatch)
If so, a pattern signal reverse to the test pattern signal stored in the data buffer register 22 (see FIG. 4) is copied to the expected value pattern memory 24. This selection switching is performed by the configuration shown in FIG.

[Effects of the Invention] As described above, according to the present invention, the write signals WE _{1 to} WE ₃
Because it was generated in synchronization with the comparison instruction signal STB, and may generate a write signal WE ₃ at the end of the period of the pattern generation cycle.

Therefore, according to the present invention, all expected value patterns can be copied corresponding to the test pattern from the head to the last. Therefore, there is an advantage that all the results of the test can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the present invention, FIG. 3 is a block diagram for explaining a conventional technique, and FIG. FIG. 5 is a block diagram for explaining the expected value pattern copying operation, and FIG. 5 is a waveform diagram for explaining the operation of the conventional technique. 10: Timing generator, 20: Pattern generator, 20A: Test pattern generator, 20B: Expected value pattern generator, 30: I under test
C, 40: logic comparator, 50: delay circuit.

Claims (1)

(57) [Claims] A. A test pattern signal is given to an IC which has been previously determined to be a non-defective product, a response output signal thereof is compared with the same pattern signal as a test pattern signal prepared as an expected value pattern in a logical comparator, and the comparison is performed. An IC with a function to copy the test pattern signal as an expected value pattern when the result is good, and to copy the reverse pattern of the test pattern signal as the expected value pattern when the comparison result is negative.
B. An IC test apparatus characterized in that the test apparatus is configured to perform the copy operation in synchronization with a comparison command signal given to the logical comparator.