JPH11258308A - Logic pattern judgment circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a logic circuit judgment circuit which can reduce a circuit scale. SOLUTION: A logic pattern judgment circuit is provided with a plurality of judgment units 21 provided with disagreement detection circuits 25 in which the disagreement of an output bit pattern from a semiconductor integrated circuit with a prescribed bit pattern is detected on the basis of the output voltage of a first comparison circuit 23, on the basis of the output voltage of a second comparison circuit 24 and on the basis of the voltage of the prescribed bit pattern and in which its detection result is held. An OR circuit 22 is installed in such a way that it outputs a signal to the effect of a disagreement when one out of the disagreement detection circuits 25 provided at the plurality of judgment units 21 holds the detection result to the effect of the disagreement.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inspection apparatus for a semiconductor integrated circuit such as an LSI, and checks whether an output bit pattern from a semiconductor integrated circuit for a predetermined input bit pattern matches a predetermined bit pattern. And a logic pattern judgment circuit for judging.

[0002]

2. Description of the Related Art A conventional logic pattern judging circuit includes a plurality of judging units 75 each composed of comparing circuits 71 and 72, a detecting circuit 73 and a memory 74 as shown in FIG. One judgment unit 75 is used for one output terminal of the integrated circuit. The comparator 71 compares the high-level threshold voltage input via the terminal 76 with the output voltage from the semiconductor integrated circuit input via the terminal 77,
A low-level threshold voltage input via the terminal 78;
A comparison circuit 72 compares an output voltage from a semiconductor integrated circuit as a test object input through a terminal 77 with a comparison circuit 72, and a detection circuit 73 compares the voltage of a predetermined bit pattern input through a terminal 79 with the comparison circuit Based on the output voltages of 71 and 72, a mismatch between an output bit pattern from the semiconductor integrated circuit and a predetermined bit pattern is detected, and the detected result is bit-synchronized with a strobe signal input via a terminal 80. The memory 74 is stored every time. Then, the CPU (central processing u) of the inspection apparatus
nit), the contents of the memory 74 of each determination unit 75 are read out via the terminal 81 to determine whether or not the semiconductor integrated circuit is non-defective.

However, in the above-described conventional logic pattern determination circuit, the memory 74 is required for each determination unit 75, and the wiring to the terminal 81 and the CPU is required for each determination unit 75. As a result, the manufacturing cost is increased, and the miniaturization of the inspection apparatus is hindered.

[0004]

DISCLOSURE OF THE INVENTION The present invention has been conceived under the circumstances described above, and it is an object of the present invention to provide a logic pattern determination circuit capable of reducing the circuit scale.

In order to solve the above problems, the present invention takes the following technical measures.

According to a first aspect of the present invention, there is provided a logic pattern determination circuit for determining whether an output bit pattern from a semiconductor integrated circuit for a predetermined input bit pattern matches a predetermined bit pattern, A first comparison circuit that compares an output voltage from the semiconductor integrated circuit with a predetermined first threshold voltage and outputs a high-level or low-level voltage according to the comparison result; A second comparison circuit that compares the output voltage with a predetermined second threshold voltage lower than the first threshold voltage, and outputs a high-level or low-level voltage according to the comparison result; And a predetermined bit pattern based on the output voltage of the comparison circuit, the output voltage of the second comparison circuit, and the voltage of the predetermined bit pattern. And a plurality of discrimination units each including a discrepancy detection circuit that holds the detection result, and that any one of the discrepancy detection circuits provided in each of the plurality of discrimination units does not match. Provided is a logic pattern determination circuit, which is provided with an output circuit that outputs a signal indicating mismatch if the detection result is held.

According to this logic pattern determination circuit,
If the mismatch detection circuit holds the detection result and the output circuit holds the detection result indicating that at least one of the mismatch detection circuits provided in the plurality of determination units does not match, a mismatch is detected. Since a signal to the effect is output, there is no need to provide a memory for each determination unit, and it is not necessary to individually connect each determination unit and the CPU, so that the circuit scale can be reduced. Furthermore, the pass / fail of the semiconductor integrated circuit to be inspected can be determined only by measuring the output of one output circuit.

[0008] Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be specifically described below with reference to the drawings.

FIG. 1 is a schematic configuration diagram of an inspection apparatus provided with a logic pattern determination circuit according to the present invention. The inspection apparatus includes an analog tester 1, a test box 2, and a logic unit 3. The test box 2 is provided with a socket 4 into which an LSI (not shown) in which an analog circuit and a digital circuit to be inspected coexist is inserted and removed by a handling device (not shown). Test box 2 and logic unit 3
They are connected to each other by a twisted pair flat cable 5 and a coaxial flat cable 6.

FIG. 2 is a circuit block diagram of the logic unit 3. The logic unit 3 includes an interface 11, a timing generator 12, a control memory 13, a pattern memory 14, a synthesis circuit 15, a voltage conversion circuit 16, and an input / output circuit. 17 and a logic pattern determination circuit 18.

The inspection of the analog circuit built in the LSI inserted in the socket 4 of the test box 2 is performed by the well-known analog tester 1 and the logic unit 3 is not used. When a digital circuit built in an LSI is inspected, each circuit of the logic unit 3 is set by the analog tester 1 via the test box 2 and the inspection is executed by the logic unit 3 to determine whether the product is good or defective. Is transmitted from the logic unit 3 to the analog tester 1 via the test box 2.

That is, 9
Six relays (not shown) are provided. Of these, 16 relays are controlled by the analog tester 1, and 16-bit signals from the relays are logically converted in parallel via the twisted pair flat cable 5. The data is input to the interface 11 of the unit 3. Of these 16-bit signals, 8 bits are setting data, and the remaining 8 bits are addresses of circuits in the logic unit 3. Then, various data are set in 8-bit units in the circuit specified by the 8-bit address.

For example, various bit patterns to be supplied to a plurality of input terminals of the LSI inserted into the socket 4 are set in the pattern memory 14. In the control memory 13, a plurality of types of start addresses and end addresses for reading bit patterns from the pattern memory 14 are set.

A start command is sent from the analog tester 1 via the test box 2 and the twisted pair flat cable 5 to the interface 11 of the logic unit 3.
, The read address of the pattern memory 14 is output from the control memory 13, and the address is incremented by one in synchronization with the clock signal from the timing generator 12. As a result, a predetermined bit pattern is output from the pattern memory 14 to the synthesizing circuit 15. The bit pattern and the timing signal from the timing generator 12 are synthesized by the synthesizing circuit 15 and output to the input / output circuit 17. The synthesized signal is converted to a predetermined voltage level by the voltage conversion circuit 16 and supplied from the input / output circuit 17 to the plurality of input terminals of the LSI inserted into the socket 4 via the coaxial flat cable 6. Of course, the bit patterns supplied to each input terminal of the LSI are different from each other.

Signals from a plurality of output terminals of the LSI inserted into the socket 4 are input in parallel to the input / output circuit 17 of the logic unit 3 via the coaxial flat cable 6, and are supplied to the predetermined voltage level by the voltage conversion circuit 16. And supplied to the logic pattern determination circuit 18. The logic pattern determination circuit 18 compares the bit pattern from the output end of the LSI with a predetermined bit pattern from the pattern memory 14 in synchronization with the strobe signal from the synthesis circuit 15 and compares the determination result with the coaxial flat cable 6.
And outputs it to the analog tester 1 via the test box 2. The operation of the logic pattern determination circuit 18 will be described later in more detail.

FIG. 3 is a circuit block diagram of the logic pattern judgment circuit 18, and the logic pattern judgment circuit 1
8 includes a plurality of determination units 21 and an OR circuit 22. Each determination unit 21 includes a first comparison circuit 23,
A second comparison circuit 24 and a mismatch detection circuit 25 are provided, and one determination unit 21 is used for each output terminal of the LSI.

The judging unit 21 synchronizes a bit pattern from the output terminal of the LSI input via the input / output circuit 17 and a predetermined bit pattern from the pattern memory 14 with a strobe signal from the synthesizing circuit 15. If there is at least one unmatched bit, the OR circuit 2
2 and a high-level signal is output to the OR circuit 22 if all bits match. Of course, bit patterns from different output terminals of the LSI are input to each determination unit 21.

The OR circuit 22 includes all the judgment units 21
If the output from is low, a low-level signal is output to the analog tester 1 via the terminal 31 and the test box 2, and if at least one output from the determination unit 21 is high, the terminal 31 and the Test box 2
And outputs a high-level signal to the analog tester 1 via the.

The first comparison circuit 23 is composed of an operational amplifier, and is connected to the input / output circuit 17 and the terminal 27 from the output terminal of the LSI.
Is higher than the high-level threshold voltage input from the voltage conversion circuit 16 via the input / output circuit 17 and the terminal 26, a high-level signal is output and the output terminal of the LSI Input / output circuit 17 and terminal 27
Is lower than the high-level threshold voltage input from the voltage conversion circuit 16 via the input / output circuit 17 and the terminal 26, a low-level signal is output.

The second comparison circuit 24 is composed of an operational amplifier, and is connected to the input / output circuit 17 and the terminal 27 from the output terminal of the LSI.
Is higher than the low-level threshold voltage input from the voltage conversion circuit 16 via the input / output circuit 17 and the terminal 26, a high-level signal is output, and the output terminal of the LSI Input / output circuit 17 and terminal 27
Is lower than a low-level threshold voltage input from the voltage conversion circuit 16 via the input / output circuit 17 and the terminal 26, a low-level signal is output.

That is, the first comparison circuit 23 and the second comparison circuit 24 constitute a window comparator.

The mismatch detecting circuit 25 includes a first comparing circuit 2
Based on the output voltage of the third and second comparison circuits 24 and the voltage of the predetermined bit pattern input from the pattern memory 14 via the terminal 29, the input from the timing generator 12 via the synthesis circuit 15 and the terminal 30 In synchronization with the received strobe signal STB, it is detected whether or not the output bit pattern of the LSI matches a predetermined bit pattern from the pattern memory 14. If at least one mismatch bit is detected, a high level is detected. And the state is maintained.

FIG. 4 is a circuit diagram of the mismatch detection circuit 25. The mismatch detection circuit 25 includes an XNOR circuit 41,
D circuit 42, NOR circuit 43, OR circuit 44, NAND
A circuit 45, an AND circuit 46, a latch circuit 47 including a JK flip-flop, and an AND circuit 48 are provided.

Now, the judgment unit 21 is connected via a terminal 27.
The output voltage of the LSI input to the non-inverting input terminals of the first comparing circuit 23 and the second comparing circuit 24 is the high level input to the inverting input terminal of the first comparing circuit 23 via the terminal 26. Since the high-level threshold voltage is higher than the low-level threshold voltage, the first
Both the outputs of the comparison circuit 23 and the second comparison circuit 24 become high level. The clear signal input to the clear signal input terminal of the latch circuit 47 via the terminal 53 is at a high level, and the AND circuit 4
8 is at a high level.

A signal supplied from the output terminal of the first comparison circuit 23 to one input terminal of the XNOR circuit 41 and the AND circuit 42 via the terminal 49 of the mismatch detection circuit 25, and the output of the second comparison circuit 24 When both the signal supplied to the other input terminal of the XNOR circuit 41 and one input terminal of the NOR circuit 43 from the terminal through the terminal 51 of the mismatch detection circuit 25 are at a high level, the pattern memory 14 AND circuit 42 and N
When a signal constituting a predetermined bit pattern supplied to the other input terminal of the OR circuit 43 is at a high level, XNO
The outputs of the R circuit 41 and the AND circuit 42 go high, and the output of the NOR circuit 43 goes low. Therefore, the output of the OR circuit 44 becomes high level,
The output of the ND circuit 45 becomes low level. As a result, even if the strobe signal STB input from the timing generator 12 via the synthesizing circuit 15 and the terminal 30 of the determination unit 21 goes high, the output of the AND circuit 46 is low, and the output of the latch circuit 47 is low. Remains at the low level, and the output of the AND circuit 48 is also at the low level.

On the contrary, the AND circuit 42 and the NOR circuit 42 from the pattern memory 14 via the terminal 29 of the judgment unit 21
When the signal constituting the predetermined bit pattern supplied to the other input terminal of the circuit 43 is at a low level, the output of the XNOR circuit 41 goes to a high level, and the outputs of the AND circuit 42 and the NOR circuit 43 go to a low level. Become. Therefore, the output of the OR circuit 44 becomes low level,
The output of the circuit 45 becomes high level. As a result, when the strobe signal STB input from the timing generator 12 via the synthesizing circuit 15 and the terminal 30 of the determination unit 21 goes high, the output of the AND circuit 46 goes high and the output of the latch circuit 47 goes high. Become a level. When the output of the latch circuit 47 becomes high level,
The output of the AND circuit 48 becomes high level,
The output of the circuit 48 is supplied to the OR circuit 22 of the logic pattern determination circuit 18 via the terminal 55,
Output goes high. The output of the OR circuit 22 is supplied to the analog tester 1 via the terminal 31, the coaxial flat cable 6, and the test box 2. The high level output of the latch circuit 47 is held until the clear signal input to the clear signal input terminal of the latch circuit 47 via the terminal 53 becomes low level.

The determination unit 21 is connected via a terminal 27.
The output voltage of the LSI input to the non-inverting input terminals of the first comparing circuit 23 and the second comparing circuit 24 is the low level input to the inverting input terminal of the second comparing circuit 24 via the terminal 28. , The high-level threshold voltage is higher than the low-level threshold voltage, and both the outputs of the first comparison circuit 23 and the second comparison circuit 24 are low.

A signal supplied from the output terminal of the first comparison circuit 23 to one input terminal of the XNOR circuit 41 and the AND circuit 42 via the terminal 49 of the mismatch detection circuit 25, and the output of the second comparison circuit 24 When both the signal supplied to the other input terminal of the XNOR circuit 41 and one input terminal of the NOR circuit 43 from the terminal via the terminal 51 of the mismatch detection circuit 25 are at a low level, the determination unit 21 AND circuit 42 and N
When a signal constituting a predetermined bit pattern supplied to the other input terminal of the OR circuit 43 is at a low level, XNO
The outputs of the R circuit 41 and the NOR circuit 43 go high, and the output of the AND circuit 42 goes low. Therefore, the output of the OR circuit 44 becomes high level,
The output of the ND circuit 45 becomes low level. As a result, even if the strobe signal STB input from the timing generator 12 via the synthesizing circuit 15 and the terminal 30 of the determination unit 21 goes high, the output of the AND circuit 46 is low, and the output of the latch circuit 47 is low. Remains at the low level, and the output of the AND circuit 48 is also at the low level.

On the other hand, the AND circuit 42 and the NOR circuit 42 from the pattern memory 14 via the terminal 29 of the determination unit 21
When the signal constituting the predetermined bit pattern supplied to the other input terminal of the circuit 43 is at a high level, the output of the XNOR circuit 41 goes to a high level, and the outputs of the AND circuit 42 and the NOR circuit 43 go to a low level. Become. Therefore, the output of the OR circuit 44 becomes low level,
The output of the circuit 45 becomes high level. As a result, when the strobe signal STB input from the timing generator 12 via the synthesizing circuit 15 and the terminal 30 of the determination unit 21 goes high, the output of the AND circuit 46 goes high and the output of the latch circuit 47 goes high. Become a level. When the output of the latch circuit 47 becomes high level,
The output of the AND circuit 48 becomes high level,
The output of the circuit 48 is input to the OR circuit 22 of the logic pattern determination circuit 18 via the terminal 55,
Output goes high.

The determination unit 21 is connected via a terminal 27.
The voltage from the LSI input to the non-inverting input terminals of the first comparing circuit 23 and the second comparing circuit 24 is the high level input to the inverting input terminal of the first comparing circuit 23 via the terminal 26. Is lower than the threshold voltage of the second comparison circuit 24 and is equal to or higher than the low-level threshold voltage input to the inverting input terminal of the second comparison circuit 24 via the terminal 28, the output of the first comparison circuit 23 becomes low , The output of the second comparison circuit 24 goes high.

A signal supplied from the output terminal of the first comparison circuit 23 to one input terminal of the XNOR circuit 41 and one input terminal of the AND circuit 42 via the terminal 49 of the mismatch detection circuit 25 is at a low level, and the second comparison circuit When the signal supplied from the output terminal 24 to the other input terminal of the XNOR circuit 41 and one input terminal of the NOR circuit 43 via the terminal 51 of the mismatch detection circuit 25 is at a high level, the output of the XNOR circuit 41 becomes low. Level, so that the AND circuit 42 and the N
The output of the NAND circuit 45 goes high regardless of whether the signal constituting the predetermined bit pattern supplied to the other input terminal of the OR circuit 43 is high or low. As a result, the timing generator 12
When the strobe signal STB input from the synthesizing circuit 15 and the terminal 30 of the determination unit 21 goes high, the output of the AND circuit 46 goes high and the output of the latch circuit 47 goes high. Latch circuit 4
7 goes high, the output of the AND circuit 48 goes high. The output of the AND circuit 48 is supplied to the OR circuit 22 of the logic pattern determination circuit 18 via the terminal 55, The output goes high.

If the mask signal input to one input terminal of the AND circuit 48 via the terminal 54 is set to a low level, a high level signal is not output from the AND circuit 48. When the inspection of one LSI is completed, the clear signal input to the clear signal input terminal of the latch circuit 47 via the terminal 53 is set to a low level, whereby the latch circuit 47 is cleared. 4
7 outputs a low-level signal. Also,
By monitoring the signal output from the terminal 56 of the inconsistency detection circuit 25, the output of the AND circuit 46 can be observed without latching it, so that it is convenient to use it when adjusting each circuit of the inspection apparatus.

The above operation is performed by the determination unit 21 equal to the number of output terminals of the LSI inserted in the socket 4.
And at least one of the judgment units 2
When a high-level signal is output from the OR circuit 22, the OR circuit 22
, A high-level signal is output to the terminal 31.

As described above, when even one bit does not match the bit pattern of the signal output from each output terminal of the LSI and the predetermined bit pattern corresponding to each output terminal,
If the signal output from each output terminal of the LSI is at an intermediate level between the high-level threshold and the low-level threshold even for one bit, a high-level signal is output from the logic pattern determination circuit 18 and the signal is output. Is input to the analog tester 1 via the coaxial flat cable 6 and the test box 2, so that the analog tester 1
The quality of the digital circuit portion of I can be easily determined.

Further, since a memory for storing the determination result of each bit in each determination unit 21 is not required, and the circuit configuration of the logic pattern determination circuit 18 can be favorably simplified, the logic pattern determination circuit 18 can be downsized. In addition, reduction in manufacturing cost can be realized.

Further, since the determination results of all the determination units 21 are combined into one by the OR circuit 22, the L level can be obtained simply by measuring the voltage of the signal output to the terminal 31 with a voltmeter or the like.
The quality of the digital circuit portion of the SI can be determined, and the general-purpose analog tester 1 as in the above embodiment can be used.
At the same time, it is most suitable to be incorporated in the logic unit 3 having a simple configuration capable of realizing the function of the digital tester by using it.

Although the OR circuit 22 is provided as an output circuit in the above embodiment, an AND circuit may be used as the output circuit when the result of the inspection is indicated by a low level signal. Of course, a NOR circuit or a NAND circuit can be used as the output circuit.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of an inspection apparatus including a logic pattern determination circuit according to the present invention.

FIG. 2 is a circuit block diagram of a logic unit provided in the inspection device shown in FIG.

FIG. 3 is a circuit block diagram of a logic pattern determination circuit provided in the logic unit shown in FIG. 2;

4 is a circuit diagram of a mismatch detection circuit provided in the logic pattern determination circuit shown in FIG.

FIG. 5 is a circuit block diagram of a determination unit provided in a conventional logic pattern determination circuit.

[Explanation of symbols]

 Reference Signs List 18 logic pattern judgment circuit 21 judgment unit 22 OR circuit 23 first comparison circuit 24 second comparison circuit 25 mismatch detection circuit

Claims (1)

[Claims] 1. A logic pattern determination circuit for determining whether an output bit pattern from a semiconductor integrated circuit corresponding to a predetermined input bit pattern matches a predetermined bit pattern, the logic pattern determination circuit comprising: an output voltage from the semiconductor integrated circuit; A first comparison circuit that compares a predetermined first threshold voltage and outputs either a high-level voltage or a low-level voltage according to the comparison result; and an output voltage from the semiconductor integrated circuit and the first comparison circuit. A second comparison circuit that compares a predetermined second threshold voltage lower than the threshold voltage and outputs a high-level or low-level voltage according to the comparison result; and an output of the first comparison circuit. An output bit pattern from the semiconductor integrated circuit and the predetermined bit based on a voltage, an output voltage of the second comparison circuit, and a voltage of the predetermined bit pattern; A plurality of discrimination units each including a discrepancy detection circuit that detects a discrepancy with the pattern and retains the detection result, and even one of the discrepancy detection circuits provided in each of the plurality of discrimination units does not match; A logic pattern determination circuit, comprising: an output circuit that outputs a signal indicating a mismatch if the result of the detection is held.