JP3070439U - Semiconductor test equipment - Google Patents

Abstract

(57) Abstract: Provided is a semiconductor test apparatus having a configuration in which, among the hardware resources included in the semiconductor test apparatus, hardware resources required for the operation purpose of the semiconductor test apparatus are mounted. A semiconductor test apparatus is divided into a test apparatus main body and a test station, and a high-speed pulse signal transmitted between the two apparatuses is connected by a predetermined length coaxial cable. Receiving a response signal output from an IC output terminal of a device under test placed on the test station side, comparing a fail signal, which is a pass / fail judgment result detected and compared with an expected value under a predetermined timing condition, for each test cycle And a fail storage means for receiving the fail signal and storing the fail signal in the test station. The fail test means for detecting the fail signal is provided in the test station, and the fail storage means for storing the fail signal in the test station is provided in the test station. Semiconductor test equipment provided on the side.

Description

[Detailed description of the invention]

[0001]

[Technical field to which the invention belongs]

 The present invention relates to a semiconductor test apparatus having a configuration in which, among the hardware resources (hard resources) included in the semiconductor test apparatus, hardware resources required for the operation purpose of the semiconductor test apparatus are mounted. In particular, the present invention relates to a semiconductor test apparatus having a hardware resource configuration capable of reducing the number of signal connections between a test apparatus main body side and a test station side for a mass production semiconductor test apparatus.

[0002]

[Prior art]

 Semiconductor test equipment can be used in two forms: for research and development of devices, evaluation of prototypes, development of device test programs, and mass production IC inspection. On the other hand, semiconductor test equipment for research and development of devices is used for research on new devices and devices with higher speeds, and for measuring and evaluating and analyzing mass-produced devices from various viewpoints while improving circuits, cell layout and pattern wiring. used. Therefore, the test is often performed by fully utilizing various device analysis functions of the FM function unit 80 described later. On the other hand, the mass-production semiconductor test equipment forms a large number of circuit chips on a wafer using a photomask or the like for the mass-production device evaluated above, and tests whether the circuit operation is normal. In this case, the evaluation and analysis from the various viewpoints described above are unnecessary, and a test function that can perform pass / fail judgment and classification by category is usually sufficient. Therefore, it can be said that there is no need to use various device analysis functions of the FM function unit 80 described later in a mass-production semiconductor test apparatus.

[0003] The prior art will be described below with reference to a divided configuration diagram of a conventional semiconductor test device in FIG. 3 and a signal connection diagram between a conventional test device main body and a test station in FIG. The number of test stations (also referred to as test heads) to be connected is one, two, or four in the system configuration. Here, a specific configuration example will be described. Since the semiconductor test apparatus is well-known and well-known in the art, the description of the entire system except for the main part is omitted.

As shown in FIG. 4, a signal line for transmitting a main high-speed pulse is provided between a test apparatus main body side and a test station side as a plurality of P-channel driver patterns DR PAT1 and a plurality of U-channel comparators. An expected value pattern EXP1, a strobe signal STB1 of a plurality of W channels, and a mismatch signal FL1 of a plurality of 2Q channels are connected. These signal lines are described below together with explanations of each element. Note that the number of driver channels P and the number of comparator channels Q may be the same or different depending on the system configuration (logic tester, memory tester, etc.). An example is described below.

[0005] As shown in FIG. 3, the main components of the present application include, as elements shown in FIG. 3, elements built in one test station side: pin electronics of a predetermined number of channels, a first logical comparator DC1, and an expected value generation circuit. And a timing generator TG, a pattern generator PG, a waveform shaper FC, a second logical comparator DC2, and an FM function unit 80. Prepare. In general, the test station is electrically and mechanically connected to an IC handler or an IC prober of a connection partner via a performance board PB (see FIG. 4) on the upper part of the apparatus or a HiFix apparatus for use. . At the time of this connection, the test station is provided with a mechanism capable of moving or rotating the entire apparatus. At this time, a large number of cables (see FIG. 4A) can be moved correspondingly. With a simple sheath structure.

The timing generator TG is provided on the test apparatus main body side and controls various timing edges of various channels defined based on a timing set described in a device test program while performing predetermined control with the PG. Occurs. For example, a V-channel edge signal CLK1 (an edge pulse in a shared tester, edge pulse information in a perpin tester) that supplies a leading edge and a trailing edge of a waveform applied to the DUT is supplied to the FC. As shown in FIG. 4, a W channel strobe signal STB1 is supplied to DC1 on the test station side via a relatively long coaxial cable of several meters (for example, about 5 m).

[0007] The pattern generator PG is provided on the test apparatus main body side, and includes a plurality of S-channel driver patterns PAT1 applied to the DUT IC pins, a plurality of U-channel comparator expected value patterns EXP1, and a pass / fail judgment. , A plurality of T-channel comparator enable signals (comparison enable signals) CPE 1 and other data strings. The logic IC test apparatus PG has a memory called an SQ PG for storing patterns, and generates and outputs the various patterns while reading the contents of the memory. It is called a PG and has an arithmetic means inside, and generates and outputs the above-mentioned various patterns while performing the arithmetic operation. The plurality of T-channel comparator enable signals CPE1 are, for example, T = 16 signals for controlling the pass / fail comparison for each test cycle, and are supplied to the DC2 in the test apparatus main body. Here, assuming that a cycle for judging pass / fail in a cycle of a test cycle (test rate) is a test cycle, the comparator enable signal CPE1 is a signal indicating a desired test cycle. The expected value pattern EXP1 for comparators of the plurality of U channels is a signal for supplying expected value data corresponding to a test cycle, and is supplied to the test station via a coaxial cable of several meters. In this configuration example, since the test station is provided with the expected value generation unit 70, the number of signals is several tens.

[0008] The waveform shaper FC is provided on the test apparatus main body side and shapes and outputs waveforms such as NRZ, RZ, and EOR in a desired time-phase relationship, and outputs the waveform mode. A pulse signal defining the leading edge and trailing edge of the driver pattern DRPAT1 of a plurality of P channels to be output in response to the driver pattern PAT1 from the TG and the edge signal CLK1 corresponding to the A, B and C clocks from the TG. Is output. The plurality of P-channel driver patterns DRPAT1 are supplied to the test station via a coaxial cable of several meters. When the number of test stations to be connected is two or four, the same pattern obtained by splitting the driver pattern DRPAT1 for a plurality of P channels into two or four children is supplied.

The pin electronics PE is provided on the test station side, and has a circuit of a predetermined plurality of channels connected to each IC pin of the DUT for transmitting and receiving signals. Here, the device test items include a DC parameter test for measuring DC characteristics, a dynamic function test that is a test under actual operating conditions of an actual DUT, and a device classification classification mainly. There are AC parametric tests that apply to According to the test items, the test is performed by appropriately utilizing the driver DR, the comparator CP, the changeover switch, and other hardware resources provided in the PE as desired.

[0010] The driver DR in the PE differs depending on the system configuration, but includes a plurality of P channels, for example, 1000 channels or more, and a driver pattern DRPAT1 in which the leading edge and the trailing edge from the FC provided on the test apparatus main body side are defined. And a pulse waveform received through a few meters of coaxial cable and converted to the desired voltage levels (VIH, VIL) to be applied to the IC pins of the DUT.

Although the comparator CP in the PE differs depending on the system configuration, the comparator CP includes a plurality of Q channels, for example, 500 channels or more, and receives a response signal output from an IC pin of the DUT and receives two threshold level voltages. The sense signals Dhi and Dlow of the 2 × Q channel converted into logic signals by (VOH, VOL) are supplied to DC1 in the test station.

The first logical comparator DC1 is provided on the test station side and performs a logical comparison with an expected value at a predetermined timing. As shown in the principle configuration example of FIG. Upon receiving the 2 × Q channel sense signals Dhi and Dlow, receiving the strobe signal STB1 from the test apparatus main body side, latching the sense signal at the edge timing of the strobe, and detecting the plurality of U channels from the test apparatus main body side. The expected value pattern EXP2 of the number of Q channels, which has been converted in a predetermined manner by the expected value generating unit 70, which receives and intermediates the expected value pattern EXP1 for the comparator, is compared with the corresponding signal of the latched result, and the comparison is performed. The resulting mismatch signal FL1 of the plurality of 2Q channels is supplied to the test apparatus main body via a coaxial cable of several meters.

Returning to FIG. 3, the expected value generating section 70 is provided on the test station side and is, for example, a memory having a predetermined capacity for storing expected value data, and a small number of comparators of the U channel. It receives the expected value pattern EXP1 for use at the address input terminal, reads out a large number of expected value patterns EXP2 corresponding to a plurality of Q channels as the contents of the address, and supplies the converted expected value pattern EXP2 to the DC1. Note that some devices do not include the expected value generating unit 70 depending on the system configuration. In this case, the PG directly generates and supplies the expected value pattern EXP2.

The second logical comparator DC2 is provided on the test apparatus main body side and receives a mismatch signal FL1 of a plurality of 2Q channels from the test station side via a coaxial cable of several meters to indicate a test cycle. The non-coincidence signal FL1 of the corresponding group channel is gated in accordance with the T-channel comparator enable signal CPE1, and a fail signal FL2 indicating the obtained judgment failure is supplied to the FM function unit 80.

The FM function unit 80 is provided on the test apparatus main body side, and includes a determination result holding unit FM1, a storage holding unit FM2, and a fail memory unit FM3. The judgment result holding unit FM1 temporarily holds the signal obtained by receiving and adding the fail signal FL2 in units of a desired small test section, and FIG. 5B shows an example of the principle configuration thereof. Here, it is assumed that a start clear signal (START CLEAR) is generated at the start of the measurement in units of a desired small test section in a device test item, and a test pattern end signal is generated at the end of the measurement of the small test section. . At this time, the judgment result holding unit FM1 receives the fail signal FL2 and sets and holds the flip-flop FF when the fail signal FL2 exists at least once in units of a desired small test section in the device test item. This is output as device failure information FL3. As shown in FIG. 5B, the memory holding unit FM2 stores the device failure information FL3 at a predetermined address in the memory in response to the test pattern end signal and updates the next storage address. By repeating this, the device defect information FL3 is sequentially stored in the memory. According to this, for each small test section in the device test item, the contents of the memory holding unit FM2 are determined as to which DUT failed or which IC pin failed among a plurality of simultaneously tested DUTs. You can tell by reading it. In response to the contents, the DUT is classified according to a predetermined category and, for example, the IC handler is notified of the separated transport information for each DUT. However, the details of the test cycle in which the failure occurs are unknown because the flip-flop FF OR-adds the fail signal FL2 between the small test sections.

Returning to FIG. 3, the fail memory unit FM3 mainly enables detailed analysis of the cause of the device failure. For example, the fail memory unit FM3 includes a memory circuit for analyzing the address where the failure has occurred, that is, the AFM unit. , A DFM unit for analyzing a process until a failure occurs, and the like. In particular, a semiconductor test apparatus for testing a memory IC includes an AFM that stores fail information for each memory cell in correspondence with a memory IC that is a DUT. For example, the data width of the DUT is provided corresponding to the × 1 to × 18 bit configuration, the DUT is provided corresponding to the large address space of the DUT, and the configuration is also provided in which the simultaneous measurement number corresponds to 64. I have. Further, it has a configuration corresponding to a high-speed memory IC such as an SDRAM and an ECL. In order to cope with these various DUT configurations, there is no choice but to have a huge circuit scale. Here, the AFM is a memory for storing fail information corresponding to each memory cell, and a storage circuit that can be assigned and changed as desired so as to have the same address space and data width as the DUT is configured. Here, upon receiving the same storage address signal (see FIG. 3A) as the address information given to the DUT by the ALPG, the fail information is stored at the relevant address position. In addition, it is necessary that, for example, 1000 or more fail signals FL2 can be received and stored in parallel. Soon after the device test is completed, it will be used for repair analysis processing to repair defects using these stored information, and for evaluation and analysis such as fail bit map display. Therefore, for example, when simultaneously measuring 64 high-speed 256 Mbit large-capacity memories, it is necessary to provide a large-capacity memory of 16000 Mbit or more. In order to enable testing of a high-speed ECL memory IC, DDRAM, or the like, the internal configuration is realized by, for example, a 16-phase (way) interleave configuration, which has a complicated and vast circuit configuration.

Next, the number of cable connections between the devices in FIG. 4 will be described with reference to a specific example. Here, assuming that the semiconductor test device is a device for testing a memory IC and that the system configuration allows simultaneous measurement of eight DUTs per test station, the driver pins have 72 channels and I / O pins. Is assumed to have 96 channels. In the above case, it is assumed that the number of mismatch signals FL1 of a plurality of 2Q channels supplied from DC1 to DC2 is (96 × 8) × 2 = 1536 per test station. It is also assumed that the number of driver patterns DRPAT1 of a plurality of P channels supplied from the FC to the driver DR is 1344 per test station. Although the number of comparator enable signals CPE1 of a plurality of T channels is 16 for each test station, it is a connection within the test apparatus main body and does not matter. The expected value pattern EXP1 for comparators of a plurality of U channels is about 20 when the expected value generating section 70 is provided, and the number of strobe signals STB1 of the W channel is several. Therefore, the total number is 1536 + 1344 + 20 + several ≒ 2900 (see FIG. 4A). In the case of a system configuration of four test stations, a huge number of cable connections of 2,900 × 4 = 1,1600 are required. Focusing on 1536 non-coincidence signals FL1 among them, since the second logical comparator DC2 and the FM function unit 80 are provided on the test apparatus main body side, they are transmitted to the test apparatus main body side. It turns out that it is necessary. Here, while the circuit scale of one second logical comparator DC2 is small, the circuit scale of the other FM function unit 80 is as described above because the fail memory unit FM3 has a complicated and huge circuit configuration as described above. Because it is difficult to practically store it on the station side, it is provided on the test apparatus main body side.

Most of the signal lines having a length of several meters transmitted above change at a device test speed, and are high-speed signals having a prescribed waveform timing, for example, 500 MHz signals. The edge timing of the pulse transmitted through this line is required to be highly accurate, for example, within ± 100 picoseconds. For this reason, high-quality coaxial cables with excellent transmission characteristics are transmitted in a differential transmission form, and connectors with good characteristics corresponding to coaxial cables are provided at both ends. Further, a differential interface circuit connected to both ends of the coaxial cable for transmitting and receiving signals is realized with a compensation circuit for improving deterioration of high-speed pulse edges caused by the coaxial cable. The board space for mounting these circuits is also required on the board. Also, it is necessary to provide a holding structure for holding the coaxial cable so as not to apply tension stress or the like.

Although the above is a specific example of a system configuration capable of simultaneously measuring eight DUTs per test station, a system configuration capable of simultaneously measuring 16/32 DUTs per test station is also described. Yes, a large number of cables will be required in proportion to this.

[0020]

[Problems to be solved by the invention]

 By the way, there are two operation modes of the semiconductor test apparatus, one for device development and one for mass production. In a mass-production semiconductor test device, it is sufficient if a test for judging the quality of an IC to be mass-produced can be performed. Therefore, the device analysis function of the FM function unit 80 is not required in a semiconductor test apparatus for mass production. As described above, the number of signal connections between the test apparatus main body and the test station is large, and it is necessary to provide high-quality coaxial cables and transmission / reception circuits. Furthermore, as the test station moves or rotates, it is necessary to provide a structure that can flexibly move a large number of bundled thick cable bundles, which makes semiconductor test equipment expensive. There were difficulties. On the other hand, the number of semiconductor test devices to be operated is overwhelmingly large for mass-produced ICs, and the multifunctional device analysis function of the FM function unit 80 is not often used. Further, in a conventional semiconductor test apparatus, the number of cables to be connected is large, and in order to measure a recent high-speed device such as 500 MHz to 1 GHz, it is important to reduce the number of cables. Therefore, the problem to be solved by the present invention is to provide a semiconductor test apparatus having a configuration in which, among the hardware resources included in the semiconductor test apparatus, necessary hardware resources are mounted in accordance with the operation purpose of the semiconductor test apparatus. It is to provide. In particular, paying attention to the fact that the multifunctional device analysis function is not used, the analysis function was deleted, and the number of signal connections between the test equipment body and the test station side could be greatly reduced. The purpose is to provide semiconductor test equipment specialized in semiconductor test equipment.

[0021]

[Means for Solving the Problems]

 First, in order to solve the above problems, a semiconductor test apparatus includes a test apparatus main body and a test station, and a high-speed pulse signal transmitted between the two apparatuses is connected by a predetermined length of coaxial cable. A test apparatus, which receives a response signal output from an IC output terminal of a device under test (referred to as a DUT) mounted on the test station side and detects the response signal by comparing with an expected value under a predetermined timing condition. In a semiconductor test apparatus provided with fail storage means (for example, an FM function unit) for receiving a fail signal (for example, a fail signal FL2) which is a result of the pass / fail judgment for each test cycle (test rate) and storing it in a predetermined storage form, Fail detecting means for detecting a failure signal on the test station side, and storing the fail signal in a predetermined storage form. A semiconductor test apparatus, comprising: a storage unit on the side of the test station, wherein the number of connection cables related to a high-speed pulse signal transmitted between the two apparatuses can be significantly reduced. According to the above invention, among the hardware resources provided on the test apparatus main body side and the test station side of the semiconductor test apparatus, the necessary hardware resources corresponding to the operation purpose of the semiconductor test apparatus are mounted, and in particular, both apparatuses are installed. It is possible to realize a semiconductor test apparatus having a configuration capable of greatly reducing the number of connection cables between them.

FIG. 1 shows a solution according to the present invention. Second, in order to solve the above-mentioned problems, a semiconductor test apparatus includes a test apparatus main body and a test station, and a high-speed pulse signal transmitted between the two apparatuses is connected by a coaxial cable having a predetermined length. In a test apparatus, a device under test (referred to as a DUT) mounted on the test station side transmits a predetermined test signal (for example, a driver pattern DRPAT1) supplied from the test apparatus body to an IC input terminal of the DUT. Receiving the response signal output from the IC output terminal of the DUT, detecting the response signal under predetermined threshold level conditions and timing conditions (for example, strobe signal STB1), and detecting the detected signal with an expected value for comparison (for example, expected value). A fail signal (for example, fail signal FL2), which is a pass / fail judgment result detected by predetermined comparison in pattern EXP2). In a semiconductor test apparatus provided with a fail storage means (for example, an FM function unit) which receives and stores the data in a predetermined storage form for each test cycle (test rate), a fail detection means (for example, a first logical comparator DC1) for detecting the fail signal And a second logical comparator DC2) on the test station side, wherein the fail storage means for storing the fail signal in a predetermined storage form OR-adds the fail signal in a predetermined manner to determine whether the DUT is good or not, or for each category. The test station is provided with the minimum fail information storing means (for example, the judgment result holding unit FM1 and the memory holding unit FM2) which can be classified, and is provided with the above. There is a semiconductor test apparatus characterized in that the number of connection cables can be significantly reduced.

Further, there is the above-mentioned semiconductor test apparatus, wherein the fail detecting means comprises a first logical comparator DC1 and a second logical comparator DC2. In addition, there is the above-described semiconductor test apparatus, wherein the fail storage means includes a determination result holding unit FM1 and a storage holding unit FM2.

Third, in order to solve the above-mentioned problem, when the fail storage means is composed of a judgment result holding unit FM1 and a storage holding unit FM2, the judgment result holding unit FM1 is provided with the fail detection means (for example, Fail signals (for example, a fail signal FL2) output from the first logical comparator DC1 and the second logical comparator DC2) for each test rate are received and OR-added in units of a predetermined small test interval in a device test item. The storage device FM2 includes a small-capacity memory and sequentially receives and stores the device failure information FL3. After the test is completed, the device failure information FL3, which is the content of the memory, is output. Is read by the CPU, and based on this, for example, which test item has failed or which IC pin has failed The above-described semiconductor test apparatus is characterized in that the above-described semiconductor test apparatus is characterized by specifying the DUT and classifying the DUT into a predetermined category, for example, and notifying the IC handler of the separated transport information for each DUT.

Further, there is the above-described semiconductor test apparatus, wherein the fail detecting means and the fail storing means are applied to a semiconductor test apparatus used for inspection of a mass-produced IC.

[0026]

[Embodiment of the invention]

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings together with examples. Further, the scope of claims for utility model registration is not limited by the following description of the embodiments, and the elements and connection relationships described in the embodiments are not necessarily essential to the solution. Absent.

The present invention will be described below with reference to the divided configuration diagram of the semiconductor test device of FIG. 1 and the signal connection diagram between the test device main body and the test station of FIG. Elements corresponding to those of the conventional configuration are denoted by the same reference numerals, and description of overlapping parts is omitted.

As shown in FIG. 1, the essential components of the present application are as follows. Elements included in one test station include pin electronics of a predetermined number of channels, a first logical comparator DC1, and an expected value generator. A unit 70, a second logical comparator DC2, and an FM function unit 90 from which the fail memory unit FM3 is deleted. Elements incorporated in the other test apparatus main body side include a timing generator TG, a pattern generator PG, and a waveform shaper FC. That is, the second logical comparator DC2 and the FM function unit 90 are built in the test station.

The second logical comparator DC2 provided on the test station side is the same as the conventional one and has a small circuit scale, so that it can be practically housed inside the test station side.

The internal configuration of the FM function unit 90 of the present invention includes a determination result holding unit FM1 and a storage holding unit FM2. That is, the configuration is such that the failure memory unit FM3 which is an internal element of the conventional FM function unit 80 shown in FIG. 3 is deleted. According to this, as a result of removing the huge circuit section, it becomes practically possible to accommodate the second logical comparator DC2 inside the test station together with the second logical comparator DC2. Accordingly, the cable connection of the mismatch signal FL1 of the plurality of 2Q channels is eliminated. On the other hand, with the deletion of the fail memory unit FM3, various failure analysis functions of the device disappear. Therefore, the semiconductor test apparatus of the present invention is a dedicated semiconductor test apparatus specialized for quality inspection of mass-production ICs.

Next, the cable connection of FIG. 2 will be described. In this case as well, it is assumed that the conditions are the same as before. The connection signals between the devices and the number of the connection signals change as the above components move. That is, there is no cable, for example, 1536 cables for the mismatch signal FL1 of the plurality of 2Q channels supplied from DC1 to DC2. Instead, a cable for a plurality of T-channel comparator enable signals CPE1 is added, but the number is a small number, for example, 16 cables. As a result, a great advantage can be obtained in that 1,536 cables minus 1620 cables can be reduced. Accordingly, the number of signal connections between the test apparatus main body and the test station is 16 + 1344 + 20 + several ≒ 1400 (see FIG. 2A), assuming the same conditions as in the above-described conventional case. Therefore, the number of cables can be reduced by 1500 compared to 2900 in the related art, and a special advantage that can be reduced to half or less can be obtained. Of course, the connectors for coaxial cables provided at both ends of the cable, the holding structure for holding the cable, the differential interface circuit, the compensation circuit, and the circuit mounting space on the board are halved, and the cost of the test equipment can be reduced. You. In the case of a system configuration of four test stations, the present invention has 1400 × 4 = 5600 lines, whereas the conventional one has 2900 × 4 = 11600 lines, and therefore 11600−5600 = 6000 lines. A significant advantage is that the number of cable connections can be reduced.

[0032]

[Effect of the invention]

 The present invention has the following effects from the above description. As described above, according to the present invention, an FM function unit 90 having an internal configuration in which the fail memory unit FM3 having a large circuit scale is deleted, and a configuration in which the second logical comparator DC2 is built in the test station. As a result, there is no cable connecting between the first logical comparator DC1 and the second logical comparator DC2, and as a result, there is a great advantage that thousands of coaxial cables are connected between devices per test station. can get. In addition, since the huge number of circuits of the failed memory unit FM3 and the number of coaxial cables and the number of transmission / reception circuits and connectors at both ends thereof can be reduced, an advantage that the test apparatus can be realized at lower cost can be obtained. The semiconductor test apparatus of the present invention is a test apparatus which can be applied practically and sufficiently when inspecting the quality of mass-produced ICs. On the other hand, semiconductor test equipment actually operated is overwhelmingly large for semiconductor ICs for mass production. Therefore, the technical effect of the present invention is great, and the industrial economic effect is extremely great.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor test apparatus according to the present invention;

FIG. 2 is a signal connection diagram between a test apparatus main body and a test station according to the present invention.

FIG. 3 is a block diagram of a conventional semiconductor test apparatus.

FIG. 4 is a conventional signal connection diagram between a test apparatus main body and a test station.

FIG. 5A is an example of the principle configuration of a first logical comparator,
(B) is an example of the principle configuration of the determination result holding unit and the storage holding unit.

[Explanation of symbols]

 DC1 First logical comparator FM1 Judgment result holding unit DC2 Second logical comparator FM2 Storage holding unit FM3 Fail memory unit 70 Expected value generation unit 80, 90 FM function unit CP Comparator DR Driver DUT Device under test FC Waveform shaper FF Flip・ Flop PB Performance Board PE Pin Electronics PG Pattern Generator TG Timing Generator

Claims (6)

[Utility model registration claims] A semiconductor test apparatus is a semiconductor test apparatus including a test apparatus main body and a test station, and a device under test (DU) mounted on the test station side.
A fail signal which receives a response signal output from an IC output terminal (referred to as "T") at predetermined test intervals (test rate) upon receiving a fail signal detected at predetermined intervals and stores the fail signal in a predetermined storage form. In a semiconductor test apparatus having storage means, a failure detection means for detecting the failure signal is provided on the test station side, and the failure storage means for storing the failure signal in a predetermined storage form is provided on the test station side. A semiconductor test apparatus comprising: 2. A semiconductor test apparatus comprising a test apparatus main body and a test station, wherein a high-speed pulse signal transmitted between the two apparatuses is connected by a coaxial cable having a predetermined length. A device under test (referred to as a DUT) mounted on the station side applies a predetermined test signal supplied from the test apparatus main body to an IC input terminal of the DUT, and outputs a response signal output from an IC output terminal of the DUT. Receiving a fail signal, which is a pass / fail judgment result detected by comparing the detected signal with a predetermined expected value for comparison and detecting the signal under predetermined threshold level conditions and timing conditions, for each test cycle (test rate). In a semiconductor test apparatus provided with fail storage means for storing data in a predetermined storage form, the fail detection means for detecting the fail signal is provided in the test stage. Provided the Deployment side, the failure storing means for storing said fail signal in a predetermined storage form by OR adding the fail signal to a predetermined DUT
The test station is provided with a minimum fail information storage means that can determine pass / fail or classify by category, and reduce the number of connection cables related to high-speed pulse signals transmitted between the test stations by including the above. Characteristic semiconductor test equipment. 3. The semiconductor test apparatus according to claim 1, wherein said fail detecting means comprises a first logical comparator and a second logical comparator. 4. The semiconductor test apparatus according to claim 1, wherein said fail storage means comprises a judgment result holding unit and a storage holding unit. 5. When the fail storage means comprises a judgment result holding section and a storage holding section, the judgment result holding section receives a fail signal output for each test rate from the fail detection means and performs a device test. Outputting device failure information as a result of OR addition in units of a predetermined small test section in the item; the storage holding unit includes a small-capacity memory and receives and sequentially stores the device failure information; 3. The semiconductor test apparatus according to claim 1, wherein: 6. The semiconductor test apparatus according to claim 1, wherein said fail detecting means and said fail storing means are applied to a semiconductor test apparatus used for mass production IC inspection.