JPH03210480A - Output pulse inspection circuit of ic - Google Patents

Abstract

PURPOSE:To shorten an inspection time by generating the first strobe pulse so as to allow the same to coincide with the shortest time limit of a tolerance range of H or L with respect to the output pulse of the output terminal of an IC and generating the second strobe pulse immediately after the longest time limit of the tolerance range to detect the states of two strobe signals. CONSTITUTION:A strobe pulse generating circuit 7 generates the first strobe pulse S1 in the timing coinciding with the shortest time limit of a tolerance range of 'H' or 'L' with respect to the output pulse generated at the output terminal DOUT of an IC 2 and also generates the second strobe pulse S2 in the timing immediately after the longest time limit of the tolerance range. Subsequently, a judging circuit 8 detects whether the output pulse is in an 'H' or 'L' state corresponding to the first and second strobe pulses S1, S2 and the detected state is compared with the state suitable for specifications by a comparing circuit 5.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an IC output pulse width inspection circuit, and more specifically, a circuit for inspecting whether the width of a pulse obtained from an output terminal of an IC satisfies specifications. The present invention relates to an output pulse width testing circuit that allows testing to be performed in a short time.

[Prior Art] One of the characteristics measurements of manufactured ICs is an inspection to determine whether the pulse width of an output signal output from each output bin is within a specification range. Conventional IC characteristic measurement equipment that performs this inspection uses a number of strobe pulses at a predetermined period over a period longer than the maximum time width of the pulse output from the IC's output pin in synchronization with the IC's output. continues to occur, and changes the output state (HIG) for each strobe pulse.
H level or LOW level) is detected, and the pass/fail of the IC is determined based on this to obtain a passed product that conforms to the specifications.

[Problem to be solved] In this type of determination, the state of the output detected by the strobe pulse is HIGH level (hereinafter referred to as "H") or LOW.
This is done by a so-called binary search, which detects which state the IC is in (hereinafter referred to as "L") and assigns "1" or "0" corresponding to that state.
This method has the disadvantage that the inspection time becomes longer because strobe pulses must continue to be generated for a period longer than the maximum output time width of the output pulses generated at the output terminal of the device. Furthermore, since testing must be performed for each pin, as the number of pins increases, the testing time for one IC increases accordingly.

The present invention solves the problems of the prior art, and aims to provide an IC output pulse width testing circuit that requires a short testing time.

[Means for Solving the Problems] The configuration of the IC output pulse width inspection circuit of the present invention to achieve the above-mentioned object is such that the output pulse width generated at the output terminal of the IC is "H" or "L". The first strobe pulse is generated at a timing that coincides with the shortest time limit of the allowable range, and the second strobe pulse is generated at a timing immediately after the longest time limit of the allowable range, thereby forming the first and second strobe pulses. The output pulse becomes “H” in response to
” or “L” state, and compares the detected state with a state suitable for specifications.

[Function] In this way, the first strobe pulse is generated at a timing that matches the shortest time limit of the allowable range of "H" or "L" for the output pulse generated at the output terminal of the IC, and By generating the second strobe pulse at a timing immediately after the time limit, it is possible to determine whether the pulse width conforms to the specifications simply by detecting the state of the output pulse in the two strobe pulses.

As a result, the inspection time can be shortened to a time close to the generation timing of the second strobe pulse, and the inspection time can be shortened.

[Embodiment] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an IC output pulse width inspection circuit to which the present invention is applied, and FIG. 2 is an explanatory diagram of the timing relationship in the measurement state.

1 is an IC output pulse width inspection circuit, and 2 is an IC to be inspected. 3 is an input data generation circuit, and the input data generated here is m-bit parallel (
(m is an integer of 2 or more) is sent to the input terminal IN of the IC 2 connected via the plurality of pins 4a of the socket 4. I
D OUT of C2 is an n-bit parallel (n is an integer from 2 to 7, fi) (7) which is the output terminal of IC2, and is connected to socket 4.
n-bit parallel output signals are sent to the comparator circuit section 5 via a plurality of pins 4b. In addition, 4c is socket 4
This is a power supply pin for connecting the power supply terminal VDD of the IC2 and a power supply circuit (+VDD, circuit not shown) to supply power of a predetermined voltage to the IC2.

The comparator circuit section 5 consists of comparators 5a, 5b, . V
a, Vb, . . . , Vn are comparison reference voltage generation circuits provided in the comparators 5a, 5b, .

6 is a launch circuit, which includes comparators 5a+5b,
--.5n bits are received in parallel and latched according to the strobe signal.

7 is a strobe pulse generation circuit which generates two strobe pulses Sl at predetermined timing.

S2 is generated and applied to the comparison circuit section 5 (each comparator) as an enable signal, and applied to the latch circuit 5 as a latch signal.

8 is a determination circuit, which includes a strobe pulse generation circuit 7
The latch circuit receives data from the latch circuit in response to the strobe pulses Su and S2 generated at the same time, compares the data with reference data, and determines the state of the output pulse of the IC2 based on the match/mismatch. Note that this circuit may perform the determination through program processing using a microprocessor or the like. Further, the determination circuit 8 generates a start signal to the input data generation circuit 2 and the strobe pulse generation circuit 7 to control the timing of outputting the input data to the IC 2 and the generation timing of the strobe pulse Si + 82.

Next, the determination operation will be explained with reference to FIG. 2, taking one bit of input/output data as an example.
The generation timing of the strobe pulses Si and Sz is as follows.
For example, according to the specifications, "H Strobe pulse S1 is generated at the limit timing of "L" (time Tl from input), and strobe pulse S is generated at the limit timing of "L" (time T2 from input).
Generates 2. In addition, strobe pulse Sl + Sz
The timing may be based on the output data 11.

Here, the time Tl corresponds to the time of the allowable minimum pulse width (see position 12 of O) for maintaining the "H" state determined by the specifications in the pulse generated at the output terminal T of the IC2. Therefore, the time T2 corresponds to the timing of the "L" position immediately after the allowable maximum pulse width of "H" (see position 13 of the circle). Note that at the timing immediately after the latter, the output waveform must be in the "L" state to meet the specifications, and at the former timing, the output waveform must be in the "H" state to meet the specifications. does not satisfy.

Here, for example, if a certain output of D OUT of IC2 becomes "H" at the timing of strobe pulse SR and becomes "L" at the timing of strobe pulse S2, the latch circuit obtained by the first strobe pulse Sl The data of No. 6 is “l”, and the next strobe pulse S2
If the data obtained is not "0", it will not meet the specifications and will not pass. therefore,
The determination reference data in this case is "1" for the strobe pulse St and "0" for the strobe pulse S2.

The above is an example in which the output pulse of the output DOUT of IC2 generates an "H" output, but in the case of generating an "L" output, the "L" state changes to the aforementioned "H" pulse width. ML and H may be interchanged, and the strobe pulses are generated in the same way.

Therefore, in the determination circuit 8, after each strobe pulse is generated in accordance with the timing of these two strobe pulses Sl and Sz, n bits corresponding to n bits of each output are generated.
By comparing the bit-parallel sampled data with n-bit data that conforms to the specifications as a judgment standard, it is possible to determine whether the pulse width generated by IC2 is normal and conforms to the specifications for each bit parallel. The determination can be made simultaneously, and the determination can be made almost at the timing of the second strobe pulse S2.

In addition, in the case 117), the comparison group *'i pressure V a g V
b +...Fist I Vn iL strobe pulse Sl
, Sz can be set to the "H" limit comparison voltage value or the "L" limit comparison voltage value before the respective comparison timings.

In addition, in the embodiment, each comparator 5at5bl...
The same strobe pulse Sl for +5n.

The strobe pulse Sl is added at different timings corresponding to each comparator.
+82 and launch each bit correspondingly. In such a case, the timing at which the determination circuit 8 makes the determination is such that the launch data is collected in accordance with the timing after the last nostroph halse has occurred for the first strobe pulse group, and the first determination is made. The next determination can be made by collecting latch data at the timing after the next strobe pulse is generated.

As explained above, in the embodiment, the input data generation circuit is a circuit independent of the determination circuit, but these are circuits that are configured by a microprocessor, memory, etc., and realized by program processing. There may be.

[Effects of the Invention] As can be understood from the above explanation, in this invention, the output pulse generated at the output terminal of the IC is set at a timing that corresponds to the shortest time limit of the allowable range of H'' or L''. By generating the first strobe pulse and generating the second strobe pulse immediately after the maximum time limit of the allowable range, the pulse width can be adjusted to the specification by simply detecting the state of the output pulse in two strobe pulses. It is possible to judge whether or not it is compatible.

As a result, the inspection time can be shortened to a time close to the generation timing of the second strobe pulse, and the inspection time can be shortened.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an IC output pulse width inspection circuit to which the present invention is applied, and FIG. 2 is an explanatory diagram of the timing relationship in the measurement state. 1... IC output pulse width inspection circuit, 2... IC,
3... Input data generation circuit, 4... Socket, 4a
+ 4bt 4c...Pin of socket 4, 5...
- Comparison circuit section, 5a, 5b, 5n... comparator,
6... Latch circuit, 7... Strobe pulse generation circuit, 8... Judgment circuit.

Claims (1)

[Claims] (1) H for the output pulse generated at the output terminal of the IC
A first strobe pulse is generated at a timing that coincides with the minimum time limit of the allowable range of the IGH level or LOW level, and a second strobe pulse is generated at a timing immediately after the longest time limit of the allowable range. It is characterized by detecting whether the output pulse is at the HIGH level or the LOW level in response to the second strobe pulse, and comparing the detected state with a state set as a specification. IC output pulse width inspection circuit.