JPH09312568A - Digital error detecting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital error detecting device which executes an efficient operation for detecting a digital error and also is effective to error rate evaluation. SOLUTION: Digital data obtained by the envelope operation of an A/D converter 1 is separated into two-system data by a demultiplexer 2 and, after that, the respective separated kinds of data are added in an adder 3. Then, in an error detecting circuit 4, data obtained by adding is compared with data obtained by permitting the data to be latched in a latch circuit 42 so as to be delayed for the portion of one clock and also adding threshold value data in the adder 43 by a comparator 41 so that presence or absence of the generation of the digital error is detected in an error detecting circuit 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital error detecting device for detecting an error in a digital signal, and more particularly to a digital signal generating circuit such as an A / D converter for converting an analog signal into a digital signal, which is output from the circuit. The present invention relates to a digital error detecting device for detecting an error in a digital signal.

[0002]

2. Description of the Related Art In a digital signal generating circuit such as an A / D converter which sequentially outputs digital signals in synchronization with clock pulses, a digital signal whose value is largely different from that of the digital signal to be output is output. A so-called digital error may occur. In order to control the occurrence of such a digital error, first, a digital error detection device capable of accurately detecting the presence or absence of the occurrence of the digital error is required. A conventional example of this digital error detection device is shown in FIG.

In FIG. 5, an A / D converter 51 is a digital signal generation circuit which is an inspection target for the presence or absence of a digital error, and outputs an analog input signal V _IN to a clock CLK.
And is converted into n-bit digital data. This digital data is supplied to the latch circuit 52. In the latch circuit 52, the clock CLK is divided by 1 in the frequency divider 53.
By being divided into 2 ^N and given as a clock input, the digital data from the A / D converter 51 is latched in synchronization with the divided clock, and the latched data is supplied to the error detection circuit 54 in the next stage. To do.

The error detection circuit 54 has a comparator 541 which receives the latched data of the latch circuit 52 as one input A, and a latch which latches the latched data of the latch circuit 52 in synchronization with the frequency-divided clock of the frequency divider 53. The threshold data provided from the outside is added to the latch data of the circuit 542 and the latch circuit 542, and the added data is added to the comparator 5
41 and the adder 543 which is given as the other input B of the input terminal 41. In this error detection circuit 54, A
The digital data from the A / D converter 51 is latched by the latch circuit 52.
In the comparator 541, the data A obtained by thinning out the data is further compared with the data B obtained by delaying this data by one clock in the latch circuit 542 and adding the threshold data.
When A> B, the digital error occurrence is detected.

Normally, the A / D converter is required to evaluate the error rate based on the dynamic characteristics, and therefore, it is generally evaluated by the envelope operation. That is, as shown in FIG. 6, the frequency generated by the synthesizer 61 is, for example, 50 MHz +
The analog signal V _{IN of} 1 kHz is input to the A / D converter 62, and the clock CLK having a frequency of 100 MHz generated by the pulse generator 63 is supplied to the A / D converter 62. Further, the digital data output from the A / D converter 62 is input to the D / A converter 64, and the 50 MHz clock CLK divided by 1/2 by the frequency divider 65 is input to the D / A converter 64. Give to.

The analog signal output from the D / A converter 64 is evaluated by observing it with an oscilloscope 66. FIG. 7 shows the output waveform of each part of FIG.
In FIG. 7, the clock CLK of the analog input signal V _IN
The line connecting the sampling points by is the output waveform of the A / D converter 62, and this is the reproduced waveform of the envelope data. The output waveform of the D / A converter 64 is a reproduced waveform of static characteristic data obtained by thinning out the data.

[0007]

By the way, in the conventional digital error detecting device shown in FIG. 5, as shown in the waveform diagram of FIG. Compare the data before clock Dn-1 and
Since the occurrence of a digital error is detected when n> Dn-1 + β, the precondition is that there is almost no difference between the previous data value and the current data value. In the case of envelope data obtained by the envelope operation described above, it is difficult to detect an error because the difference between the data one clock before and the current data is too large.
Therefore, it is necessary to input the static characteristic data obtained by thinning out the data to the error detection circuit.

However, in the error rate measurement for measuring the error occurrence rate, using thinned data means that the error rate measurement accuracy is lowered. Therefore, in order to obtain accurate measurement data, it takes time twice as many times as thinned data before thinning out data, which takes time to detect a digital error and is inefficient. It was

Further, although the dynamic characteristic data is converted into the static characteristic data by thinning out the data, the data is constantly changing. Therefore, as is clear from the waveform diagram of FIG. 9, noise is changed every time the data changes. generate. This noise is
Shaking the analog input section of the A / D converter also mixes the analog input signal V _{IN with} noise, and the A / D converter A / D-converts the analog input signal V _IN containing this noise. However, there is a drawback that the measurement accuracy of is reduced.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a digital error detecting apparatus capable of efficiently detecting a digital error and being effective for error rate evaluation. To do.

[0011]

A digital error detecting apparatus according to the present invention is a digital error detecting apparatus for detecting an error in digital data corresponding to an envelope waveform output from a digital signal generating circuit, wherein A data separation circuit for separating the wave data and the lower side wave data, an adder for adding the upper side wave data and the lower side wave data separated by this data separation circuit, and a data added by the adder And an error detection circuit for detecting an error.

In the digital error detection device having the above structure, the data separation circuit outputs digital data corresponding to the envelope waveform output from the digital signal generation circuit,
Separate into upper side wave data and lower side wave data. The separated data are added by the adder. As a result, the added data includes an error regardless of whether the error occurs in the upper side wave data or the lower side wave data. The error detection circuit detects whether or not a digital error has occurred based on the added data.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention in the case where an A / D converter is prepared as a digital signal generation circuit and the A / D converter is an inspection target for the presence / absence of a digital error. .

In FIG. 1, an analog signal V _IN is input to the A / D converter 1 and a clock CLK is applied. As the analog signal V _IN , the clock CLK
When the frequency is f _CLK , a signal having a frequency of 1/2 ^N + α of the clock frequency f _CLK is input. In this way, the A / D converter 1 has a clock frequency f _CLK of 1/2 ^N
When the analog signal V _IN is input at the frequency of + α, A / D
The converter 1 performs an envelope operation and outputs n-bit digital data. This digital data is clock CL
It is supplied together with K to the demultiplexer 2 which is a data separation circuit.

The demultiplexer 2 _divides a clock CLK having a frequency f _CLK into 2/2 ^N and a divider 22 that divides the divided clock of the divider 21 into 1/2. And a latch circuit 23 that latches the digital data from the A / D converter 1 in synchronization with the frequency-divided clock of the frequency divider 21, and the latched data of the latch circuit 23 as the frequency-divided clock of the frequency divider 22. It is composed of a latch circuit 24 that latches in synchronization, and a latch circuit 25 that latches digital data from the A / D converter 1 in synchronization with the divided clock of the frequency divider 22.

Each n output from the latch circuits 24 and 25
The bit data is added by the adder 3 and becomes n + 1 bit data, which is supplied to the error detection circuit 4. The error detection circuit 4 includes a comparator 41 that uses the n + 1-bit data from the adder 3 as one comparison input A, and a latch that latches the data from the adder 3 in synchronization with the frequency-divided clock of the frequency divider 22. A circuit 42 and an adder 43 which adds n + 1-bit threshold data externally given to the latch data of the latch circuit 42 and gives the addition data as the other comparison input B of the comparator 41. There is.

The n + 1-bit threshold data is set value data for setting the magnitude of an error, and digital data of an arbitrary value can be manually set, for example, by a setting device (not shown) such as a DIP switch. ). In the error detection circuit 4, the n + 1-bit data A from the adder 3 and the n + 1-bit data are delayed by one clock by the latch circuit 42, and the threshold data is added by the adder 43. The comparator 41 compares the data B with the data B and detects the occurrence of a digital error when A> B.

Next, the circuit operation of the digital error detecting apparatus having the above configuration will be described with reference to the waveform diagrams of FIGS. 2 shows the waveform of each part when the A / D converter 1 is operating normally, and FIG. 3 shows the waveform of each part when the A / D converter 1 is malfunctioning.

First, for the A / D converter 1, the analog signal V having a frequency of 1/2 ^N + α of the clock frequency f _{CLK
When IN} is input, the A / D converter 1 operates as an envelope. Here, a case of N = 1 will be described as an example. By the envelope operation of the A / D converter 1, FIG.
Digital data (hereinafter referred to as envelope data) corresponding to the envelope waveform as shown in (a) is obtained. This envelope data is separated by the demultiplexer 2 and is composed of a frequency component of αHz.
The static characteristic data X and Y of the system are output.

Of the two systems of data X and Y, data X is upper side wave data of envelope data, and data Y is lower side wave data of envelope data. As is clear from FIGS. 2B and 2C, these data X and Y are the same as the static characteristic data obtained when the envelope data is thinned out, when only the data on one side is seen, Looking at the data, the upper side wave data is delayed by one clock by the latch circuit 23, so that the mutual data X and Y are always in an inverted relationship.

The two systems of data X and Y are added in the adder 3. As a result, the adder 3 outputs data with a certain code. This data is A
As long as the / D converter 1 is operating normally, the two systems of data X and Y are always in an inverted relationship.
As shown in, a constant code does not change continuously. Therefore, in the error detection circuit 4, when the current code data A and the code data B one clock before which the threshold value data is added are compared by the comparator 41, the comparison result is always A <B. , It can be seen that no digital error has occurred.

On the other hand, when the A / D converter 1 malfunctions, a digital error caused by the malfunction appears in the envelope data as an error code. At this time, in the conventional digital error detection device shown in FIG.
Since the error detection circuit 54 detects the error based on the data obtained by thinning the envelope data,
For example, if the thinned data is the X side data, the error code generated in the X side data can be detected,
The error code generated on the Y side could not be detected.

On the other hand, in this embodiment, the two systems of data X and Y separated by the demultiplexer 2 are added by the adder 3, and the error detection circuit 4 detects an error based on the added data. Is adopted. Therefore, it is possible to detect the error code generated on either side of X and Y from the data obtained by the addition by the adder 3.

That is, in the envelope data shown in FIG. 3A, when data ,, are error data, the envelope data is demultiplexed by the demultiplexer 2
When the data is separated in, the error data is
As shown in (b), error data ',' is added to the data X.
As a result, the error data appears in the data Y as error data ', as shown in FIG. Then, when the data X and Y of the two systems are added by the adder 3, as shown in FIG. 3D, from the adder 3, error data of the code corresponding to the polarity and the level of the error data ,. Is output.

Therefore, in the error detection circuit 4,
As shown in FIG. 4A, the comparator 41 compares the current code data A with the code data B one clock before which the threshold value data β is added. As shown, when the comparison result is A> B, the comparator 4
An error detection signal of “H” level is output from 1 and A /
It can be seen that a digital error has occurred due to the malfunction of the D converter 1. Here, the threshold value data β is set value data for setting the magnitude of the error, as described above.

As described above, the digital data obtained by the envelope operation of the A / D converter 1 is separated into the upper side wave data and the lower side wave data by the demultiplexer 2, and the respective separated data are added. The error occurring in both the two systems of data X and Y can be detected by performing the error detection in the error detection circuit 4 based on the added data by the adder 3 and thus the envelope data is thinned out. The time required for the detection operation is half that of the conventional device shown in FIG. 5, which performs error detection based on data. As a result, efficient digital error detection operation is possible, and the product cost can be reduced by introducing the A / D converter in the shipping inspection.

In the configuration of this embodiment, the A / D
By making the adder 3 as well as the converter 1 and the demultiplexer 2 into an IC (integrated circuit) in one chip, the frequency of noise can be reduced, and thus small digital errors that cannot be measured by the conventional device can be achieved. Can also be detected. That is, the error rate evaluation of the A / D converter 1 is more susceptible to noise as the resolution becomes higher.
Therefore, in the case of the conventional digital error detection device,
Since the digital data input to the error detection circuit 54 constantly changes according to the level of the analog input signal V _IN , the threshold data β cannot be set below a certain level, and therefore a small digital error is detected. I couldn't.

On the other hand, in the case of the digital error detecting device according to the present invention, the digital data input from the adder 3 to the error detecting circuit 4 changes by continuously outputting a constant code when there is no digital error. However, since it changes only when a digital error occurs, the threshold data β can be set to a small value, and a small digital error can be detected accordingly. Moreover,
Since the frequency of noise generated when the data changes can be reduced, the noise returned to the analog input section of the A / D converter 1 is also reduced, which is particularly effective for error rate evaluation.

In the above embodiment, the case where the A / D converter is used as the digital signal generating circuit to be inspected has been described, but the present invention is not limited to the A / D converter and is synchronized with the clock pulse. The present invention can be applied to all digital signal generation circuits configured to sequentially output digital signals.

[0030]

As described above, according to the present invention,
In a digital error detection device for detecting errors in envelope data output from a digital signal generation circuit, envelope data is separated into upper side wave data and lower side wave data, and the separated upper side wave data and lower side wave data are separated. Is added, and the error detection is performed based on the added data, it is possible to detect an error that has occurred in both of the two systems of data, so that an efficient digital error detection operation is possible. And becomes effective for error rate evaluation.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a waveform diagram of each part for explaining the operation when the A / D converter is operating normally.

FIG. 3 is a waveform diagram of each part for explaining the operation when the A / D converter malfunctions.

FIG. 4 is a waveform diagram for explaining the operation of the error detection circuit.

FIG. 5 is a block diagram showing a conventional example.

FIG. 6 is a system block diagram of envelope operation evaluation.

FIG. 7 is a waveform diagram of each part during envelope operation.

FIG. 8 is a waveform diagram for explaining the principle of error detection.

FIG. 9 is a waveform diagram showing the influence of noise generated by the A / D converter.

[Explanation of symbols]

1 A / D converter 2 Demultiplexer 3, 4
3 adder 4 error detection circuit 23 to 25, 42 latch circuit 41 adder

Claims (4)

[Claims] 1. A digital error detection device for detecting an error in digital data corresponding to an envelope waveform output from a digital signal generation circuit, the data separating the digital data into upper side wave data and lower side wave data. A separation circuit, an adder that adds the upper side wave data and the lower side wave data separated by the data separation circuit, and an error detection circuit that performs error detection based on the data added by the adder. A digital error detection device characterized by being provided. 2. The A / D which outputs the digital data by an envelope operation.
The digital error detection device according to claim 1, wherein the digital error detection device is a converter. 3. The digital error detection device according to claim 1, wherein the digital signal generation circuit, the data separation circuit, and the adder are integrated. 4. The digital error detection device according to claim 2, wherein the A / D converter, the data separation circuit, and the adder are integrated circuits.