JP2646713B2 - Semiconductor device comparison test circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device comparison test circuit, and more particularly to an LSI comparison test circuit capable of detecting a delay difference or the like of a high density integrated circuit (LSI).

[Conventional technology]

Conventionally, in this type of LSI comparison tester, an appropriate pattern is input to the element and the pattern output from the element is simply compared, and most of them operate with a clock slower than the actual operation. Also, it was not possible to determine a delay difference due to a difference between LSI lots and the like.

[Problems to be solved by the invention]

In the conventional LSI comparison test circuit described above, the same type of LSI
The variation in delay due to differences in lots etc. is not taken into account, and many of them do not operate with the actual operating clock, so even if the delay difference is large, the comparison test is “OK”.
However, there is a drawback that a problem may occur after the device is mounted on an apparatus.

SUMMARY OF THE INVENTION An object of the present invention is to provide a comparison circuit of a semiconductor device in which the above-mentioned drawbacks are solved and a comparison test can be performed on the variation in delay time.

[Means for solving the problem]

The configuration of the semiconductor element comparison test circuit of the present invention includes a random code generator that generates a test pattern to be input to at least the first and second semiconductor elements, a timing generator that generates a plurality of clock signals, 1, a selection circuit for selecting a clock signal having a high frequency such that a delay difference between the operations of the second semiconductor element appears from among the clock signals, and a selecting circuit to which the test pattern is input.
1. A latch circuit for temporarily storing a signal output from the second semiconductor element by a clock signal selected by the selection circuit, and a signal stored in the latch circuit are compared with each other, and the delay difference is allowed. And a comparator for judging a failure when the value exceeds the range and outputting the result.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a comparative test circuit of a semiconductor device according to one embodiment of the present invention. In FIG. 1, the comparison test circuit of the present embodiment includes a first LSI 2 and a second
To the input terminal of LSI3. As a result, the pattern output from the output terminal is transferred to the D-type flip-flop group 4.
And input the data to the timing generator (Timing
The clock signal generated by the generator 6 is selected by a clock (CLK) selection circuit 7 and a latch similar to the maximum delay allowable in the device is latched by the clock. The result is compared with the LSI including the delay by the comparator 5.
A comparative test is performed. Here, the selection circuit 7
Only one clock signal is selected from the three clock signals, and is used as a clock signal for the D-type flip-flop group 4 and the comparator 5.

FIG. 2 is a timing chart of the circuit shown in FIG.
The output signal 8 of the first LSI 2 and the output signal 9 of the second LSI are latched by the clock (CLK) signal 10 generated by the timing generator 6 and the respective output signals 11 and 12 are compared. Are compared by the comparator 5, and GO, N
Perform OGO determination. Note that the comparator 5 has a function of holding the signal once it becomes NOGO.
Note that the delay difference ΔT between the output signals 8 and 9 depends on the difference between lots and the like.

As described above, according to the present embodiment, the test pattern generated by the random code generator 1 is input to the two LSIs 2 and 3 of the same type, and the output pattern is input to the D-type flip-flop group 4. Then, the data is latched by the timing generator 6 with a clock having the same high frequency as the maximum delay operating on the device. When the delay difference exceeds an allowable range, the next or previous data is latched. Therefore, the next-stage comparator determines NOGO, and enables a comparison test including a delay difference between LSI lots and the like.

〔The invention's effect〕

As described above, according to the present invention, since it is possible to compare LSI signal delays, it is possible to determine even a delay difference due to variations in LSI lots and the like, and it is possible to prevent a malfunction on a device due to an LSI delay difference before mounting. effective. Furthermore, according to the present invention, the presence of the selection circuit allows not only the selection of a clock signal having a delay difference but also the classification of a failure mode from data obtained by testing with a plurality of clock signals. There is also an effect that there is.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a comparative test circuit of a semiconductor device according to one embodiment of the present invention, and FIG. 2 is a timing chart of the circuit shown in FIG. 1 …… Random code generator, 2,3 …… L to be compared
SI, 4 ... D-type flip-flop group, 5 ... Comparator, 6
…… Timing generator, 7 …… CLK selection circuit, 8, 9, 10, 1
1,12,13 …… Signal.

Claims (1)

(57) [Claims] A random code generator for generating a test pattern to be input to at least first and second semiconductor elements; a timing generator for generating a plurality of clock signals;
1, a selection circuit for selecting a clock signal having a high frequency such that a delay difference between the operations of the second semiconductor element appears from among the clock signals, and the first and second inputting the test patterns A latch circuit that temporarily stores a signal output from the second semiconductor element by a clock signal selected by the selection circuit and a signal stored by the latch circuit are compared with each other, and the delay difference is within an allowable range. A comparator circuit for comparing semiconductor devices, comprising: a comparator that determines that the measured value exceeds the threshold and outputs the result.