JP2001194423A - Test circuit for semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a test circuit which is used to test a semiconductor integrated circuit at a high speed and accurately, without using an expensive testing apparatus and by suppressing the increase in the circuit scale of the semiconductor integrated circuit, and to provide a test method. SOLUTION: A switching circuit (an output buffer) 8, an exclusive-OR circuit 14, a holding circuit (a register) 11 and a control circuit (an OR gate) 18 for the holding circuit are combined into one set. The circuits in a plurality are provided. The electrical connection of the signal input part of an internal circuit 5 in the semiconductor integrated circuit to an input/output terminal 2 is cut off by the switching circuit 8. The logical sum of a signal to be input from the input/output terminal and the output signal of the internal circuit 5 is output from the exclusive-OR circuit 14. A signal which is output from the exclusive-OR circuit 14 is held, by the holding circuit 11 to which the control circuit 18 used to control a signal holding operation is connected. The logical sum of signals to be output from a plurality of holding circuits is output to a monitoring terminal 17 from an OR circuit 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit built in a semiconductor integrated circuit and a test method for the semiconductor integrated circuit.

[0002]

2. Description of the Related Art In a test apparatus for a semiconductor integrated circuit, a pin electronics which is a measurement circuit prepared for each terminal of a device under test (semiconductor integrated circuit), wiring to the device under test of the test apparatus, a device socket, and the like. Has a stray capacitance. With this test equipment, 5 semiconductor integrated circuits
When a high-speed test is performed with an output change cycle of 0 MHz or more, waveform rounding and an output signal delay occur, and the waveform rounding and the output signal delay are values that cannot be ignored during the test.

Therefore, when testing the signal output from the output terminal of the device under test, the output timing of the strobe signal of the test apparatus should be adjusted in consideration of the above problem.
The test program is set to delay by the delay amount of the output signal. This makes it possible to take measures against waveform rounding and output signal delay.

On the other hand, at the input / output terminals of the device under test,
The signal output cycle and the signal input cycle are switched at a predetermined timing. When waveform rounding or output signal delay occurs at the input / output terminal of the device under test, the output timing of the strobe signal of the test apparatus can be delayed by a test program by the delay amount of the output signal as a countermeasure. However, in a cycle in which the output cycle is switched to the input cycle, an output signal cannot be detected at a timing after the start time of the input cycle. for that reason,
The output timing of the strobe signal of the test apparatus cannot be delayed until the timing after the start time of the input cycle. Therefore, at the input / output terminals of the device under test, waveform rounding and output signal delay pose a serious problem.

Therefore, when performing a high-accuracy high-speed test,
In order to minimize the occurrence of output signal waveform distortion and output signal delay, it is necessary to use an expensive high-speed test apparatus in which the stray capacitance of pin electronics is extremely small.

As a method of performing a high-speed test without using such an expensive test apparatus, there is a method of testing a device under test including a self-test circuit using a low-speed test apparatus. As an example of a semiconductor integrated circuit with a built-in self-test circuit, as shown in FIG. 3, an expected value generation circuit for generating a signal output expected value that should be originally output from an internal circuit, and a signal actually output from the internal circuit. There is a semiconductor integrated circuit having a built-in output comparison circuit for comparing with the expected value.

The device under test 18, which is a semiconductor integrated circuit, includes an input generation circuit 20, an expected value generation circuit 21, an internal circuit under test 22, an output comparator 23, and a test result storage register 24. By inputting an input signal such as a clock signal from the semiconductor integrated circuit test apparatus 19 to the device under test 18, the
The test signal is input to the.

The output signal of the internal circuit under test 22 is input to the output comparator 23 without being output from the output terminal of the internal circuit under test 22. Further, the semiconductor integrated circuit test apparatus 19
The output signal of the expected value generation circuit 21 which operates upon input of the output signal is input to the output comparator 23. Note that the expected value generation circuit 21 generates an expected value which is a normal signal that should be output from the internal circuit.

The output comparator 23 compares the two signals,
The result is stored in the test result storage register 24. The semiconductor integrated circuit test apparatus 19 includes the test result storage register 2
4 is tested at a low speed of about 1 MHz to determine whether or not the internal circuit under test 22 operates normally.

As described above, since the test result storage register 24 is constituted by a latch circuit, it is not necessary to perform a high-speed operation test on the output of the test result storage register 24 using an expensive test apparatus.

Next, a signal output from the internal circuit that has been operated at a high speed is stored in an internal storage device such as a RAM, and a test at a high speed operation is performed. FIG. 4 shows a configuration in which a test of a read signal is performed and a test is performed so as not to be affected by output waveform rounding or output signal delay.

The device under test 25 includes an internal circuit 2 under test.
6, an output result calculation circuit 28 and an output result storage internal storage device 29 are provided. A clock signal, input data, and the like are input from the semiconductor integrated circuit test apparatus 27 to the internal circuit under test 26 of the device under test 25. In this case, a high-speed signal of 50 MHz or more is input from the semiconductor integrated circuit test device 27. When a low-speed signal of about 1 MHz is input, it is necessary to provide an input generation circuit for an internal circuit such as the input generation circuit 20 as shown in FIG.

In the device under test 25 shown in FIG. 4, the input signal is not so affected by the waveform delay and the waveform rounding as the output signal. Therefore, according to the signal input from the semiconductor integrated circuit test device 27, the signal output from the internal circuit under test 26 is input to the output result operation circuit 28 and stored in the output result storage internal storage device 29. Processed into Then, it is stored and held in the output result storage internal storage device 29. Then, by testing the output of the output result storage internal storage device 29 at a low speed, a high-speed operation test of the internal circuit under test 26 can be performed.

As described above, since the output of the output result storage internal storage device 29 is tested at a low speed, it is not affected by waveform rounding or output delay.

Japanese Patent Application Laid-Open No. Hei 5-264667 discloses that in order to perform a high-speed test, a low-speed parallel signal input is converted into high-speed serial data by an internal high-speed converter and supplied to an internal high-speed operation circuit under test. A test circuit for performing a high-speed test by converting a serial output from an internal high-speed operation circuit to be tested into low-speed parallel data and outputting the data at low speed is disclosed.

This test circuit converts a low-speed signal input into a high-speed signal inside the semiconductor integrated circuit and converts a high-speed output signal into a low-speed signal inside the semiconductor integrated circuit. Test circuit.

[0017]

In order to perform a high-speed test on a semiconductor integrated circuit, it is necessary to perform the test using a test apparatus having a very small stray capacitance of pin electronics. However, as described above, a test device having a very small stray capacitance of pin electronics is very expensive, and such a test device is mainly used for research and development. Therefore, it has not been widely deployed to mass-production factories at present.

A semiconductor integrated circuit including a self-test circuit including an input generation circuit and an expected value generation circuit, and a semiconductor integrated circuit including a self-test circuit including an internal storage device,
Incorporate very large circuits for high-speed testing. for that reason,
The circuit area increases, leading to an increase in chip cost.

In the case of the test circuit disclosed in Japanese Patent Application Laid-Open No. 5-264667, a frequency multiplier for generating a high-speed clock signal by multiplying a low-speed clock signal by a plurality of times, and a parallel for converting a low-speed parallel signal to a high-speed serial signal. / Serial converter and a serial / parallel converter for converting a high-speed serial signal into a low-speed parallel signal. Therefore, the area of the test circuit increases,
As described above, this leads to an increase in chip cost.

Further, the expected value generation circuit and the input generation circuit require complicated logic design, which may extend the design development period. In the case where the high-speed test data conversion circuit is built in, there is a problem that the circuit scale is similarly increased.

In addition, a semiconductor integrated circuit having a built-in self-test circuit and a high-speed test data conversion circuit performs a test in units of internal circuit blocks. Therefore, a sufficiently high-speed test can be performed in units of circuit blocks. There is a tendency that high-speed testing of logic circuits other than circuit blocks such as between blocks or output circuits cannot be sufficiently performed. As a result, the test quality is reduced.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to suppress an increase in the circuit scale of a semiconductor integrated circuit without using an expensive test apparatus. Another object of the present invention is to provide a test circuit and a test method incorporated in a semiconductor integrated circuit for performing a high-speed and accurate test.

[0023]

The present invention has the following arrangement as means for solving the above-mentioned problems.

(1) An opening / closing circuit for disconnecting an electrical connection between an output terminal and a signal output section of an internal circuit, and a switching circuit for disconnecting a signal input from the output terminal and a signal output from a signal output section of the internal circuit. An exclusive-OR circuit that outputs an exclusive-OR, and a holding circuit that holds a signal output from the exclusive-OR circuit are provided as a set of a plurality of circuits, and output from the plurality of holding circuits. An OR circuit that outputs the OR of the signals
A monitor terminal connected to the output terminal of the OR circuit.

In this configuration, as a test circuit of the semiconductor integrated circuit, a plurality of circuits each including a switching circuit, an exclusive OR circuit, and a holding circuit are provided, and an output terminal of the semiconductor integrated circuit and an internal circuit are provided. The electrical connection with the signal output unit is disconnected by a switching circuit, the exclusive OR of the signal input from the output terminal and the output signal of the signal output unit of the internal circuit is output from the exclusive OR circuit, and the exclusive OR is output. The signal output from the logical OR circuit is held by a holding circuit, and the OR of the signals output from the plurality of holding circuits is output from the OR circuit to the monitor terminal. Therefore, a high-speed test can be performed at low cost without using an expensive high-speed semiconductor integrated circuit test device having pin electronics with a reduced stray capacitance for the internal circuit of the semiconductor integrated circuit.

(2) An opening / closing circuit for disconnecting the electrical connection between the input / output terminal and the signal input / output unit of the internal circuit, and a signal input from the input / output terminal and a signal output from the signal input / output unit of the internal circuit. An exclusive-OR circuit that outputs an exclusive-OR with the received signal, a holding circuit that holds a signal output from the exclusive-OR circuit, and a control circuit that controls holding of a signal input to the holding circuit And a plurality of circuits as a set, comprising a logical sum circuit that outputs a logical sum of signals output from the plurality of holding circuits, and a monitor terminal connected to an output terminal of the logical sum circuit. It is characterized by having.

In this configuration, as a test circuit of the semiconductor integrated circuit, a plurality of circuits each including a set of a switching circuit, an exclusive OR circuit, a holding circuit, and a control circuit of the holding circuit are provided. The electrical connection between the input / output terminal of the circuit and the signal input / output unit of the internal circuit is cut off by a switching circuit, and the exclusive OR of the signal input from the input / output terminal and the output signal of the input / output unit of the internal circuit is calculated. A signal output from the exclusive OR circuit is held by a holding circuit connected to a control circuit that controls signal holding, and a signal output from the exclusive OR circuit is held. Is output from the OR circuit to the monitor terminal. Therefore, by configuring the test circuit of the internal circuit of the semiconductor integrated circuit with a simple circuit, it is possible to suppress an increase in circuit area and to suppress an increase in the price of the semiconductor integrated circuit.

(3) An opening / closing circuit for disconnecting the electrical connection between the output terminal and the signal output section of the internal circuit, and the switching circuit between the signal input from the output terminal and the signal output from the signal output section of the internal circuit. A plurality of circuits each including a pair of an exclusive OR circuit that outputs an exclusive OR and a first holding circuit that holds a signal output from the exclusive OR circuit; A switching circuit for disconnecting an electrical connection between a signal input / output unit of a circuit and an input / output terminal, and an exclusive logic of a signal input from the input / output terminal and a signal output from a signal input / output unit of the internal circuit An exclusive OR circuit that outputs a sum, a second holding circuit that holds a signal output from the exclusive OR circuit, a control circuit that controls holding of a signal input to the second holding circuit, Are provided as a set, and the plurality of first holding circuits and And a logical sum output circuit for outputting a logical sum of the signals output from the plurality of second holding circuits, and a monitor terminal connected to an output terminal of the logical sum circuit.

In this configuration, the test circuit connected to the output terminal of the semiconductor integrated circuit and the signal output section of the internal circuit includes a switching circuit, an exclusive OR circuit, and a first holding circuit. A plurality of circuits configured as a circuit, disconnecting an electrical connection between a signal output portion of the internal circuit of the semiconductor integrated circuit and an output terminal by a switching circuit, and outputting a signal input from the output terminal and a signal output portion of the internal circuit. The exclusive OR with the signal is output from the exclusive OR circuit, and the signal output from the exclusive OR circuit is held by the first holding circuit. The test circuit connected to the input / output terminal of the semiconductor integrated circuit and the signal input / output unit of the internal circuit includes a switching circuit, an exclusive OR circuit,
A plurality of circuits configured as a set of a second holding circuit and a control circuit of the second holding circuit are provided, and an electrical connection between a signal input / output unit and an input / output terminal of an internal circuit of the semiconductor integrated circuit is provided. The signal is cut by the open / close circuit, the exclusive OR of the signal input from the input / output terminal and the output signal of the input / output unit of the internal circuit is output from the exclusive OR circuit, and the signal output from the exclusive OR circuit Is connected to a control circuit for controlling signal holding.
Is held by the holding circuit. Then, the logical sum of the signals output from the plurality of first holding circuits and the plurality of second holding circuits is output from the OR circuit to the monitor terminal. Therefore, by incorporating a relatively simple test circuit for each output terminal and input / output terminal, it is possible to operate the internal circuit at high speed with almost all circuit blocks and output circuits at timings close to actual operation. Thus, a high-speed test of a semiconductor integrated circuit can be performed with high quality and at low cost.

(4) The switching circuit is a three-state gate circuit, and electrically connects a signal output portion of an internal circuit of the semiconductor integrated circuit and an output terminal and an input / output terminal of the semiconductor integrated circuit during a test of the semiconductor integrated circuit. Disconnecting the dynamic connection.

In this configuration, the switching circuit for disconnecting the electrical connection between the signal output section of the internal circuit of the semiconductor integrated circuit and the output terminal and the input / output terminal of the semiconductor integrated circuit during the test of the semiconductor integrated circuit is provided by a three-way switch. It is a state gate circuit. Therefore, during the test, the electrical connection is cut off without the output signal of the internal circuit of the semiconductor integrated circuit being output from the output terminal or the input / output terminal of the semiconductor integrated circuit, and the output signal of the internal circuit is surely output by the test circuit. Can be tested.

(5) The signal input from at least one of the output terminal and the input / output terminal is an expected value of a signal output from the signal output unit of the internal circuit.

In this configuration, the expected value of the output signal of the internal circuit is input from at least one of the output terminal and the input / output terminal of the semiconductor integrated circuit. Therefore, the quality of the signal output from the internal circuit can be easily determined by comparing the signal output from the signal output unit or the signal input / output unit of the internal circuit with the expected value. The expected value is
A normal output signal that should be output when a signal is input to the internal circuit.

(6) A plurality of output terminals of the semiconductor integrated circuit and a plurality of signal output portions of the internal circuit, and a plurality of input / output terminals of the semiconductor integrated circuit and one of the plurality of signal input / output portions of the internal circuit. The logical connection is cut by a plurality of switching circuits, and an exclusive OR of a signal input from one of the output terminal and the input / output terminal and an output signal of the internal circuit is output from the plurality of exclusive OR circuits. Outputting the OR of the signal output from the exclusive OR circuit from the plurality of OR circuits;
A signal output from the OR circuit is held by a plurality of holding circuits whose signal holding is controlled by a control signal, and a logical sum of the signals output from the plurality of holding circuits is output from the OR circuit, A signal output from a monitor terminal connected to an output terminal of the sum circuit is confirmed.

In this configuration, one of the plurality of signal output units and the plurality of output terminals of the internal circuit of the semiconductor integrated circuit, and one of the plurality of signal input / output units and the plurality of input / output terminals of the internal circuit are electrically connected. Is cut by an open / close circuit, and an exclusive OR of a signal input from one of a plurality of output terminals and a plurality of input / output terminals and an output signal of an internal circuit is output from the plurality of exclusive OR circuits, The signals output from the plurality of exclusive OR circuits are held by the plurality of holding circuits, and the OR of the signals output from the plurality of holding circuits is output from the OR circuit to the monitor terminal. Therefore, a high-speed test can be performed at low cost without using an expensive high-speed semiconductor integrated circuit test device in which the internal circuit of the semiconductor integrated circuit has a small floating capacitance. Further, by configuring the test circuit of the internal circuit of the semiconductor integrated circuit with a simple circuit, an increase in circuit area is suppressed, and an increase in the price of the semiconductor integrated circuit is suppressed. Furthermore, by incorporating a relatively simple test circuit for each output terminal and each input / output terminal, it is possible to operate almost all circuit blocks and output circuits at a high speed with timing close to actual operation. Thus, a high-speed test of a semiconductor integrated circuit can be performed with high quality and at low cost.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A test circuit for a semiconductor integrated circuit according to an embodiment of the present invention which can easily perform a high-speed test will be described below in detail with reference to FIGS. FIG. 1 is a block diagram of a test circuit for a semiconductor integrated circuit according to the present invention. FIG. 2 is a timing chart of the circuit of FIG.

The test circuit for a semiconductor integrated circuit according to the present invention can test output signals from output terminals and input / output terminals.

The output signal test circuit section A1 of the test circuit includes an output buffer 7, an exclusive OR gate 13, a result storage register 10, and a result storage register OR gate 16.

The signal output section of the internal circuit 4 of the semiconductor integrated circuit is connected to the output terminal 1 via an output buffer 7 which is a three-state gate circuit having a control input terminal. The signal output section of the internal circuit 4 is connected to one of two input terminals of an exclusive OR gate 13 which is an exclusive logic circuit.

The output terminal 1 of the semiconductor integrated circuit is connected to the other of the two input terminals of the exclusive OR gate 13 which is an exclusive OR circuit. The output terminal of the exclusive OR gate 13 is connected to the input terminal D of the result storage register 10, which is the first holding circuit. Further, the output terminal Q of the result storage register 10 is connected to the input terminal of the result storage register OR gate 16 which is an OR circuit.

A predetermined clock signal is input from an internal circuit to the clock input terminal CK of the result storage register 10. Further, the same signal as that input from the internal circuit to the control input terminal of the output buffer 7 is input to the reset input terminal R of the result storage register 10.

The input / output signal test circuit section A2 of the test circuit has:
It comprises an output buffer 8, an exclusive OR gate 14, a result storage register 11, an OR gate 18, and a result storage register OR gate 16.

The signal input / output section of the internal circuit 5 of the semiconductor integrated circuit is connected to the input / output terminal 2 via an output buffer 8 which is a three-state gate circuit having a control input terminal. The signal output section of the internal circuit 5 is connected to one of two input terminals of an exclusive OR gate 14 which is an exclusive logic circuit.

The input / output terminal 2 of the semiconductor integrated circuit is connected to the other of the two input terminals of the exclusive OR gate 14. The output terminal of the exclusive OR gate 14 is connected to the input terminal D of the result storage register 11, which is the second holding circuit. Further, the result storage register 11
Is connected to an input terminal different from the input terminal of the OR gate 16 for the result storage register which is an OR circuit.

The clock input terminal CK of the result storage register 11 has a logical sum gate 18 as a control circuit for controlling signal holding (latch) of the result storage register 11.
Output terminals are connected. The two input terminals of the OR gate 18 receive a predetermined clock signal from an internal circuit and IO_C which is an input / output control signal of the semiconductor integrated circuit.
And the TRL signal. The reset input terminal R of the result storage register 11 has the same HTE as that input to the control input terminal of the output buffer 8 from the internal circuit.
The ST1 signal is input.

A test circuit for a semiconductor integrated circuit according to the present invention includes a plurality of the above-mentioned output signal test circuit sections and input / output signal test circuit sections. The output terminal Q of the result storage register of each signal test circuit is connected to a plurality of input terminals of the OR gate 16 which is an OR circuit.

Next, a method for testing a signal output from the signal output section of the internal circuit 4 using the output signal test circuit section A1 will be described. In the present invention, when the output signal of the output terminal 1 is tested, the output terminal 1 is used as a signal input terminal, the test is performed by the output signal test circuit unit A1, and the pin electronics and the like of the semiconductor integrated circuit test device are tested. The test is performed by the test circuit of the semiconductor integrated circuit without intervention, and the output of the test result is confirmed.

First, the test circuit of the semiconductor integrated circuit is HT
The test mode is set by setting the EST1 signal to High.

In the output signal test circuit section A1, the HTEST1 signal is input to the control input terminal of the output buffer 7. When the HTEST1 signal is High, the output of the output buffer 7 becomes high impedance, and the electrical connection between the signal output unit of the internal circuit 4 and the output terminal 1 is disconnected. When the HTEST1 signal is low, the output buffer 7
, The signal output section of the internal circuit 4 and the output terminal 1
It is in a state of being electrically connected.

A test signal is input from the semiconductor integrated circuit test apparatus to a signal input unit (not shown) of the internal circuit 4 via an input terminal (not shown) of the semiconductor integrated circuit. Further, at this time, when the test signal is input to the internal circuit 4,
The expected value output from the signal output unit of the input signal A1_I
As input from the output terminal 1.

The exclusive OR gate 13 has an internal circuit 4
And the expected value input signal A1_I are input from the signal output unit of. Then, the exclusive OR gate 13 outputs an exclusive OR of both signals from an output terminal.

The exclusive OR gate 13 outputs a low signal if the expected value input signal A1_I matches the output signal A1_O of the internal circuit 4. The exclusive OR gate 13 outputs a High signal if the expected value input signal A1_I and the output signal A1_O of the internal circuit 4 do not match.

The output signal of the exclusive OR gate 13 is stored and held in the result storage register 10 in accordance with the test timing latch clock signal CK1 set at a predetermined timing.

On the other hand, in the input / output signal test circuit section A2, the HTEST1 signal is input to the control input terminal of the output buffer 8. When the HTEST1 signal is high, the output of the output buffer 8 becomes high impedance, and the electrical connection between the signal output section of the internal circuit 4 and the output terminal 1 is disconnected. When the HTEST1 signal is low, the signal output section of the internal circuit 4 and the output terminal 1 are electrically connected in the output buffer 7.

Further, a test signal is input from the semiconductor integrated circuit test apparatus to a signal input unit (not shown) of the internal circuit 5 via an input terminal (not shown) of the semiconductor integrated circuit. Further, at this time, when a test signal is input to the internal circuit 5,
The expected value output from the signal input / output unit of the input signal A2_
I is input from the output terminal 2.

The exclusive OR gate 14 has an internal circuit 5
A2_O output from the signal input / output unit and an expected value input signal A2_I are input. Then, the exclusive OR gate 14 outputs an exclusive OR of both signals from an output terminal.

Here, the exclusive OR gate 14 outputs a Low signal if the expected value input signal A2_I and the output signal A2_O of the internal circuit 5 match. The exclusive OR gate 14 outputs a High signal if the expected value input signal A2_I and the output signal A2_O of the internal circuit 5 do not match.

The output signal of the exclusive OR gate 14 is held and stored in the result storage register 11 in accordance with the test timing latch clock signal CK2 set at a predetermined timing.

Here, the operation of the output signal test circuit A1 is different from the operation of the test timing output from the OR gate 18 in the input mode in which the IO_CTRL signal becomes HIGH even if the clock signal changes at a predetermined timing. The latch clock signal CK2 is made inactive. In addition, the latch in the result storage register 11 is prohibited.

This prevents the output of the result storage register 11 from fluctuating in the input mode after switching from the output mode to the input mode at the time of testing the output signal of the input / output terminal, thereby preventing the occurrence of a failure judgment. Is to do so.

A signal output from each result storage register connected to the OR gate 16 such as the result storage register 10 or the result storage register 11 is input to the logic gate 16. Then, the logical sum of each input signal is output from the logical sum gate 16 to the monitor terminal 17.

The OR gate 16 outputs a High level signal if there is no problem with the input signal. However, if at least one input signal is a defective signal, Lo
A w-level signal is output.

For this reason, since the monitor terminal 17 is connected to the pin electronics of the semiconductor integrated circuit having the stray capacitance, the signal output from the monitor terminal becomes distorted and does not affect the test result even if the signal is delayed. . For this reason, there is no need to use an expensive semiconductor integrated circuit test device having a small stray capacitance inherent to the pin electronics.

As described above, according to the present invention, a signal output from the output section or the input / output section of the internal circuit is output to the output terminal 1 or the input / output terminal 2 and the semiconductor integrated circuit connected to the outside of the semiconductor integrated circuit is output. The test is performed by a test circuit built in the semiconductor integrated circuit such as the output signal test circuit section A1 or the output signal test circuit section A2 without performing the test using the pin electronics of the test apparatus. Therefore, since output signal delay and waveform rounding do not occur, the effect is remarkably exhibited not only at the input / output terminals but also at the output terminals.

Further, by using the test circuit having the above configuration, it is not necessary to add a test circuit for performing a high-speed test on circuits inside the output buffers 7 to 9.
Therefore, the internal circuit can be operated at a timing relatively close to the actual operation, and all the circuits other than the output buffer can be equally operated at a high speed, so that a very high quality test can be performed.

As another embodiment of the test circuit for a semiconductor integrated circuit according to the present invention, only a plurality of output terminal test sections are provided, and the output terminal Q of the result storage register of each terminal test section is connected to the OR gate 16. May be respectively connected to the plurality of input terminals. In this case, the operation of each unit is the same as that of the output signal test circuit unit A1 described with reference to FIGS.

Further, as still another embodiment of the test circuit for a semiconductor integrated circuit of the present invention, a plurality of input / output terminal test sections alone are provided, and the output terminal Q of the result storage register of each terminal test section is logically ORed. Each of the gates 16 may be connected to a plurality of input terminals. In this case, the operation of each unit is the same as that of the input / output signal test circuit unit A2 described with reference to FIGS.

As described above, according to the present invention, without using an expensive test apparatus and without increasing a chip cost by incorporating a self-test circuit having a large circuit scale and a data conversion circuit circuit for high-speed test. , Can perform high-speed tests. Furthermore, by incorporating a relatively simple test circuit for each output terminal and input / output terminal, it is possible to operate almost all circuit blocks and output circuits at a high speed near the actual operation. Yes,
A high-speed test of a semiconductor integrated circuit can be performed with high quality and at low cost.

[0069]

According to the present invention, the following effects can be obtained.

(1) As a test circuit for a semiconductor integrated circuit, a plurality of circuits each including a switching circuit, an exclusive OR circuit, and a holding circuit are provided. Disconnect the electrical connection with the output section with a switching circuit,
The exclusive OR of the signal input from the output terminal and the output signal of the signal output unit of the internal circuit is output from the exclusive OR circuit, and the signal output from the exclusive OR circuit is held by the holding circuit, Since the logical sum of the signals output from the plurality of holding circuits is output from the logical sum circuit to the monitor terminal, an expensive high-speed semiconductor integrated circuit test apparatus having pin electronics that reduces the stray capacitance of the internal circuit of the semiconductor integrated circuit A high-speed test can be performed at a low cost without using a computer.

(2) As a test circuit for a semiconductor integrated circuit, a plurality of circuits each including a set of a switching circuit, an exclusive OR circuit, a holding circuit, and a control circuit for the holding circuit are provided. The electrical connection between the input / output terminal and the signal input / output unit of the internal circuit is cut off by the open / close circuit, and the exclusive OR of the signal input from the input / output terminal and the output signal of the input / output unit of the internal circuit is exclusive. A signal output from the OR circuit and a signal output from the exclusive OR circuit are held by a holding circuit connected to a control circuit for controlling signal holding, and a logical sum of signals output from the plurality of holding circuits is logically Since the output is output from the sum circuit to the monitor terminal, the test circuit for the internal circuit of the semiconductor integrated circuit can be configured with a simple circuit, thereby suppressing an increase in circuit area and suppressing an increase in the price of the semiconductor integrated circuit. it can.

(3) The test circuit connected to the output terminal of the semiconductor integrated circuit and the signal output section of the internal circuit is configured as a set of a switching circuit, an exclusive OR circuit, and a first holding circuit. A plurality of circuits, the electrical connection between the signal output section of the internal circuit of the semiconductor integrated circuit and the output terminal is disconnected by a switching circuit, and the signal input from the output terminal and the output signal of the signal output section of the internal circuit are output. Is output from the exclusive OR circuit, and the signal output from the exclusive OR circuit is held by the first holding circuit. The test circuit connected to the input / output terminal of the semiconductor integrated circuit and the signal input / output unit of the internal circuit
A switching circuit, an exclusive OR circuit, a second holding circuit,
A control circuit of the second holding circuit, and a plurality of circuits configured as a set, the electrical connection between the signal input / output unit and the input / output terminal of the internal circuit of the semiconductor integrated circuit is cut by an open / close circuit,
An exclusive OR circuit outputs an exclusive OR of a signal input from the input / output terminal and an output signal of the input / output unit of the internal circuit, and controls signal holding of the signal output from the exclusive OR circuit. The data is held by the second holding circuit to which the control circuit is connected. Then, since the logical sum of the signals output from the plurality of first holding circuits and the plurality of second holding circuits is output from the OR circuit to the monitor terminal, the output terminal and the input / output terminal are relatively simple. By incorporating a test circuit, it is possible to operate almost all circuit blocks and output circuits at a high speed close to the actual operation of the internal circuit, making high-speed testing of semiconductor integrated circuits of high quality and low cost. Can be performed.

(4) A three-state gate is provided with a switching circuit for disconnecting an electrical connection between a signal output part of an internal circuit of the semiconductor integrated circuit and an output terminal and an input / output terminal of the semiconductor integrated circuit during a test of the semiconductor integrated circuit. By using a circuit,
During the test, the electrical connection is cut off without outputting the output signal of the internal circuit of the semiconductor integrated circuit from the output terminal or the input / output terminal of the semiconductor integrated circuit, and the output signal of the internal circuit is reliably tested by the test circuit. be able to.

(5) By inputting the expected value of the output signal of the internal circuit from at least one of the output terminal and the input / output terminal of the semiconductor integrated circuit, the signal output from the signal output section or the signal input / output section of the internal circuit is output. By comparing the value with the expected value, the quality of the signal output from the internal circuit can be easily determined.

(6) Opening and closing one of the plurality of signal output units and the plurality of output terminals of the internal circuit of the semiconductor integrated circuit, and one of the plurality of signal input / output units and the plurality of input / output terminals of the internal circuit. Circuit, and outputs the exclusive OR of the signal input from any one of the plurality of output terminals and the plurality of input / output terminals and the output signal of the internal circuit from the plurality of exclusive OR circuits. The signal output from the exclusive OR circuit is held by a plurality of holding circuits, and the logical sum of the signals output from the plurality of holding circuits is output from the OR circuit to a monitor terminal. It is possible to perform a high-speed test at low cost without using an expensive high-speed semiconductor integrated circuit test device with small floating capacitance. Also,
By configuring the test circuit of the internal circuit of the semiconductor integrated circuit with a simple circuit, an increase in the circuit area is suppressed, and an increase in the price of the semiconductor integrated circuit is suppressed. Furthermore, by incorporating a relatively simple test circuit for each output terminal and each input / output terminal, it is possible to operate almost all circuit blocks and output circuits at a high speed with timing close to actual operation. In addition, a high-speed test of a semiconductor integrated circuit can be executed with high quality and at low cost.

[Brief description of the drawings]

FIG. 1 is a block diagram of a test circuit of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a timing chart in the circuit shown in FIG.

FIG. 3 is a block diagram showing a configuration of a test circuit of a conventional semiconductor integrated circuit.

FIG. 4 is a block diagram showing a configuration of a test circuit of the conventional semiconductor integrated circuit different from that of FIG. 4;

[Explanation of symbols]

 2-input / output terminal 5-semiconductor integrated circuit internal circuit 5 8-switching circuit (output buffer) 11-holding circuit (register) 14-exclusive OR circuit 16-OR circuit 17-monitor terminal 18-holding circuit Control circuit (OR gate)

Claims (6)

[Claims] An open / close circuit for disconnecting an electrical connection between an output terminal and a signal output section of an internal circuit, and exclusion of a signal input from the output terminal and a signal output from a signal output section of the internal circuit. And a holding circuit that holds a signal output from the exclusive OR circuit. A test circuit for a semiconductor integrated circuit, comprising: a logical sum circuit that outputs a logical sum of a signal; and a monitor terminal connected to an output terminal of the logical sum circuit. 2. An opening / closing circuit for disconnecting an electrical connection between an input / output terminal and a signal input / output unit of an internal circuit, a signal input from the input / output terminal and a signal output from the signal input / output unit of the internal circuit. An exclusive-OR circuit that outputs an exclusive-OR with a signal, a holding circuit that holds a signal output from the exclusive-OR circuit, and a control circuit that controls holding of a signal input to the holding circuit. , A plurality of circuits, a logical sum circuit that outputs a logical sum of signals output from the plurality of holding circuits, and a monitor terminal connected to an output terminal of the logical sum circuit. A test circuit for a semiconductor integrated circuit, comprising: 3. An open / close circuit for disconnecting an electrical connection between an output terminal and a signal output section of an internal circuit, and exclusion of a signal input from the output terminal and a signal output from a signal output section of the internal circuit. An exclusive-OR circuit that outputs a logical OR, and a first holding circuit that holds a signal output from the exclusive-OR circuit. A switching circuit for disconnecting the electrical connection between the signal input / output unit and the input / output terminal, and an exclusive OR of a signal input from the input / output terminal and a signal output from the signal input / output unit of the internal circuit An exclusive-OR circuit for outputting a signal, a second holding circuit for holding a signal output from the exclusive-OR circuit, and a control circuit for controlling holding of a signal input to the second holding circuit. A plurality of first holding circuits and a plurality of first holding circuits; A semiconductor integrated circuit comprising: a logical sum output circuit for outputting a logical sum of signals output from the plurality of second holding circuits; and a monitor terminal connected to an output terminal of the logical sum circuit. Circuit test circuit. 4. The switching circuit is a three-state gate circuit, and electrically connects a signal output portion of an internal circuit of the semiconductor integrated circuit and an output terminal and an input / output terminal of the semiconductor integrated circuit when testing the semiconductor integrated circuit. 4. The test circuit for a semiconductor integrated circuit according to claim 1, wherein the connection is disconnected. 5. The signal according to claim 1, wherein the signal input from at least one of the output terminal and the input / output terminal is an expected value of a signal output from a signal output unit of an internal circuit. The test circuit of the semiconductor integrated circuit according to the above. 6. An electrical terminal for one of a plurality of output terminals of the semiconductor integrated circuit and a plurality of signal output units of the internal circuit, and a plurality of input / output terminals of the semiconductor integrated circuit and a plurality of signal input / output units of the internal circuit. The connection is cut by a plurality of switching circuits, and an exclusive OR of a signal input from one of the output terminal and the input / output terminal and an output signal of the internal circuit is output from the plurality of exclusive OR circuits. Then, the OR of the signal output from the exclusive OR circuit is output from the plurality of OR circuits, and the signal output from the OR circuit is output by the plurality of holding circuits whose signal holding is controlled by the control signal. Holding, outputting a logical sum of signals output from the plurality of holding circuits from an OR circuit, and confirming a signal output from a monitor terminal connected to an output terminal of the OR circuit. Test method for semiconductor integrated circuit .