JP3080850B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a semiconductor integrated circuit that requires a high-speed operation and includes a circuit for a non-defective test.

[0002]

2. Description of the Related Art Generally, non-defective products are selected by using a tester for a large-scale semiconductor integrated circuit (LSI). As one of the items for the non-defective product judgment, there is a case where an operation speed test is performed. Conventionally, when a semiconductor integrated circuit under test requires a high-speed operation exceeding the guaranteed standard of the LSI tester, the LSI tester performs the test only at a low test cycle within the standard. This has been done by mounting individual test panels on a semiconductor integrated circuit.

However, since a test panel is required for testing the high speed operation of the semiconductor integrated circuit, a test circuit as shown in FIG. 3 has conventionally been provided to perform a test of the high speed operation. A semiconductor integrated circuit has been proposed (Japanese Unexamined Patent Publication No. 2-45771).

In this conventional semiconductor integrated circuit, an output buffer is replaced with a bidirectional buffer in which an output buffer 301 and an input buffer 302 are connected in series, and an output buffer 3
01 to an output terminal 303 is also input to an input buffer 302, and the output signal of the input buffer 302 is supplied to a selector circuit 305 via a frequency dividing circuit 304 together with a logic signal, and is selected by the selector circuit 305. The signal selected based on the signal is output to the output buffer 30.
6 to the output terminal 307.

According to this conventional semiconductor integrated circuit, at the time of a test, the selector circuit 305 selects the output signal of the frequency dividing circuit 304 by the select signal, and the frequency of the high-speed operation is reduced by the frequency dividing circuit 304. The signal is output to the output terminal 307 via the selector circuit 305 and the output buffer 306, and a test of pass / fail is performed based on the output signal.

[0006]

However, in a conventional semiconductor integrated circuit in which an LSI tester performs a test only at a low test cycle, only a test at a speed lower than the actual operation can be performed. The solid may be determined as a good product. For this reason, it is necessary to mount the device on the test panel again and perform a high-speed operation test.

In addition, in the conventional semiconductor integrated circuit shown in FIG. 3, it is not possible to verify the output waveform after the frequency division for every cycle of the test pattern before the frequency division. However, there is a problem that even if several patterns of logic errors have occurred immediately after the change, detection may not be performed.

[0008] The present invention has been made in view of the above points,
It is an object of the present invention to provide a semiconductor integrated circuit capable of performing a high-speed operation test without using a frequency divider in a semiconductor integrated circuit that requires a high-speed operation exceeding an LSI tester standard.

Another object of the present invention is to provide a semiconductor integrated circuit capable of accurately obtaining a high-speed operation test result even if the phase of an expected value signal is different from the phase of a data signal. is there.

[0010]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a comparison circuit for determining a logic match / mismatch between an output data signal of a circuit under test and an expected value signal supplied from a first input terminal. If the output comparison result of the comparison circuit indicates a mismatch even in one of the test patterns given to the circuit to be verified, the fact that there is a mismatch is maintained until an external initialization signal is input. A first latch circuit, a first output terminal for outputting an output signal of the first latch circuit to the outside, a second output terminal for outputting an output data signal of the circuit to be verified to the outside, A third output terminal for outputting a clock signal having one pattern cycle of the pattern to the outside, a second input terminal for inputting an output data signal of the circuit to be verified from the outside, and a latch of the first latch circuit. And having a third input terminal that is inputted from the outside No..

According to the present invention, there is provided a comparison circuit for determining a match / mismatch between logic of an output data signal of a circuit to be verified and an expected value signal given from a first input terminal, and the output comparison result of the comparison circuit is If even one of the test patterns applied to the circuit under test indicates a mismatch, a first latch circuit that holds the mismatch until the initialization signal is input from the outside; The output signal of the latch circuit is determined for each predetermined number of patterns, and if a comparison result indicating a match is shown at least once, the fact that there is a match is maintained until an external initialization signal is input. A first output terminal for outputting an output data signal of the circuit under test to the outside, a second output terminal for outputting a clock signal of one cycle of the test pattern to the outside, It has a second input terminal to which an output data signal of the circuit to be verified is externally input and a third input terminal to which a latch signal of the first latch circuit is externally input.

[0012]

[0013]

In general, the output load capacity of an LSI tester is several tens of p.
F, which is one of the reasons that this load makes verification of high-speed operation impossible. Therefore, according to the present invention, in a semiconductor integrated circuit which is not provided with an output terminal for taking out an output data signal of a circuit under test to the outside, the comparison circuit compares the logic of the data signal with the expected value signal, and performs the comparison. Since the comparison result is obtained from the first latch circuit by inputting the result to the first latch circuit, the comparison result can be obtained without using a frequency dividing circuit or an LSI tester.

Further, in the present invention, the comparison result obtained by gradually changing the phase of the expected value signal from the first phase to the second phase by a predetermined phase every predetermined number of patterns is stored in the second latch circuit. And, when the comparison result shows a comparison result indicating a match even once, the stored content is kept, so that the judgment result as to whether or not a mismatch has occurred in any phase of the expected value signal is obtained. It can be taken out from the second latch circuit.

Further, according to the present invention, in a semiconductor integrated circuit provided with a second output terminal for taking out an output data signal of a circuit under test, an output data signal of the circuit under test is inputted from the outside. Since the two input terminals are directly connected on the test board, it is possible to obtain a comparison result of the logic match / mismatch between the data signal and the expected value signal without interposing an LSI tester.

[0016]

Next, an embodiment of the present invention will be described. FIG. 1 is a circuit diagram of a first embodiment of a semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit 100 of the present embodiment originally has output buffers 101 and 103 and output terminals 102 and 104.
In the semiconductor integrated circuit having
08 and 113, input buffers 106, 109 and 11
4. A test circuit including a comparison circuit 107, a latch circuit 110, an output buffer 115, and an output terminal 116 is provided. The latch circuit 110 includes a two-input OR circuit 11
1 and a flip-flop 112 to which an output signal of the OR circuit 111 is applied to an input terminal.

Next, the operation of the present embodiment will be described. In the semiconductor integrated circuit 100, an output data signal a obtained by a test pattern given to an internal circuit to be verified is output via an output buffer 101 to an output terminal. The signal is output to the outside from 102. Further, a clock signal b of one cycle of the test pattern synchronized with the data signal a is output from the output terminal 104 to the outside via the output buffer 103. At the time of low-speed operation within the standard of the LSI tester, the output signals a and b of the output terminals 102 and 104 are input to the LSI tester, and are compared with expected values to determine pass / fail.

However, at the time of a high-speed operation test exceeding the LSI tester standard, the connection with the LSI tester is cut off.
Output terminals 102 and 104 on a DUT board (test board for interface between LSI tester and LSI)
Are connected to input terminals 105 and 113, respectively. For this connection, it is also possible to set a load condition in an actual operation. Note that the output terminal 116 is connected to the LSI tester, but not for comparison with the expected value signal, but merely for identification of the comparison result, as described later.

As described above, the output load capacitance of an LSI tester is generally as large as several tens of pF, and this load is one factor that makes it impossible to verify high-speed operation. Therefore, in this embodiment, when verifying the high-speed operation, the data signal in the LSI tester cannot be accurately compared with the expected value, so that the output terminals 102 and 104 of the semiconductor integrated circuit 100 as described above.
By disconnecting the LSI and the LSI tester and connecting the output terminals 102 and 104 directly to the input terminals 105 and 113 on the DUT board, the delay due to the above load capacitance can be eliminated and high-speed operation can be verified. And

The data signal a output from the output terminal 102 is supplied to one input terminal of a comparison circuit 107 via an input terminal 105 and an input buffer 106.
On the other hand, the expected value signal c is input to the input terminal 108 and supplied to the other input terminal of the comparison circuit 107 via the input buffer 109. Thus, the comparator 107 outputs a high level when the data signal a and the expected value signal c do not match, and outputs a low level when they match.

Output signal of comparison circuit 107 (comparison result)
Is ORed with the output signal of the flip-flop 112 by the OR circuit 111 in the latch circuit 110, and then applied to the input terminal of the flip-flop 112. Also,
The clock signal b output from the output terminal 104 is applied as a latch signal to the clock terminal of the flip-flop 112 via the input terminal 113 and the input buffer 114. Thereby, the OR is synchronized with the clock signal b.
The output signal of the circuit 111 is latched by the flip-flop 112.

Therefore, the determination is made by the latch circuit 110 in the cycle of the clock signal b (one cycle of the test pattern applied to the circuit to be verified), and the output signal of the comparison circuit 107 is at a high level (ie, inconsistent) even once. ), The output signal of the flip-flop 112 is at a high level even if the output signal of the comparison circuit 107 is at a low level thereafter, so that the output signal of the OR circuit 111 is also at a high level. (The output signal of the flip-flop 112) always keeps the high level. Here, the reset signal d is a signal for initializing the output signal and the internal state of the latch circuit 110 to low level.

The output signal of the latch circuit 110 indicates the result of comparison between the data signal a and the expected value signal c.
It is input to an I tester (not shown), and the comparison result of the high-speed operation test is determined. Thus, according to the present embodiment,
The output terminals 102 and 104 are directly connected to the input terminals 105 and 113 located immediately adjacent to each other, and the comparison circuit 107 compares and compares the data signal a with the expected value signal c. Verification of time can be performed without using a frequency divider.

In the above description, the data signal a synchronized with the clock signal b has been described. However, the present invention is also applicable to an asynchronous circuit.
The latch signal of 0 may be another clock signal synchronized with the pattern period.

In a semiconductor integrated circuit that does not require external output of the high-speed data signal a and the clock signal b, the data signal a is directly output inside the semiconductor integrated circuit.
And the clock signal b may be connected to be input to the comparison circuit 107 and the latch circuit 110, respectively.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 2 shows a circuit diagram of a second embodiment of the present invention. In the figure, the same components as those in FIG.
The description is omitted. In the first embodiment shown in FIG. 1, the data signal a input from the input terminal 105 and the input terminal 1
If the phases of the expected value signals c inputted from 08 differ greatly from each other, the comparison circuit 10
7 and the latch circuit 110 may determine that they do not match.

Therefore, in the semiconductor integrated circuit 200 of the second embodiment shown in FIG. 2, a second latch circuit 201 is provided on the output side of the latch circuit 110, and the second latch circuit 201
Output signal from the output terminal 20 via the output buffer 204.
5, and the phase of the expected value signal c is gradually changed so that when no mismatch occurs in any of the phases, it is determined that there is no problem in the high-speed operation.

Here, the second latch circuit 201
Is a two-input AND circuit 202 and a flip-flop 203
The AND circuit 202 causes the latch circuit 110
And a signal that is the logical product of the output signal of the flip-flop 203 and the output signal of the flip-flop 203 is input to the data input terminal of the flip-flop 203. Note that the latch signal f is input to the clock terminal of the flip-flop 203, and the set signal g is input to the set terminal.

Next, the operation of this embodiment will be described.
First, assuming that the phase (delay amount) of the expected value signal c is P1, the comparing circuit 107 compares the expected value signal c with the data signal a, and inputs the obtained comparison result to the first latch circuit 110. Latched by clock signal b. As described above, the comparison result latched by the latch circuit 110 outputs a high level in the case of a mismatch, and outputs a low level in the case of a match.
7 becomes high level, the latch circuit 110
(The output signal of the flip-flop 112) always keeps the high level.

The output signal e of the latch circuit 110 is supplied to an AND circuit 202 in the latch circuit 201. Here, when the latch circuit 201 is initialized, since the flip-flop 203 is set by the set signal g, the AND circuit 202 is in the gate “open” state in the initial state. The signal e is input to the data input terminal of the flip-flop 203 through the AND circuit 202.

The expected value signal c of the above-mentioned phase (delay amount) P1 for a predetermined number of patterns by the above-mentioned comparing circuit 107
Is compared with the data signal a, the flip-flop 203 latches the signal e input to the data input terminal by the latch signal f. Here, the output signal e of the latch circuit 110 is at a high level when there is at least one mismatch in the comparison result between the expected value signal c of the phase (delay amount) P1 and the data signal a for the predetermined number of patterns. Is low only when all match.

The signal latched by the flip-flop 203 is output to an output terminal 205 via an output buffer 204 and is input to an AND circuit 202. Therefore, once the output signal e of the latch circuit 110 goes low, even if the output signal e of the latch circuit 110 goes high thereafter, the flip-flop 112
Is at a low level, the AND circuit 202
Is also at a low level, the latch circuit 201
(The output signal of the flip-flop 203) holds the low level.

Next, after resetting the flip-flop 112 by the reset signal d, the phase (delay amount) of the expected value signal c is switched to P2, and the data signal a is compared again with the predetermined number of patterns. The comparison circuit 1
07, and the comparison result is latched in the flip-flop 203. Hereinafter, the same operation as described above is performed with the expected value signal c.
Is repeated while changing the phase (the amount of delay) to Pn.

As described above, the latch circuit 201, the output buffer 204, and the output terminal are provided only when the output signal of the latch circuit 110 is at the high level in all the phases (delay amounts) of the expected value signal c from P1 to Pn. The comparison result output through the interface 205 becomes a high level indicating a mismatch, whereby the semiconductor integrated circuit 20 is output by the LSI tester.
0 is determined to be defective.

On the other hand, when the phase (delay amount) of the expected value signal c is P
1 to Pn, the output signal of the latch circuit 110 goes low (that is, the expected value signal c
The data signal a coincides with the expected value signal c in any one of the following phases), the latch circuit 201 and the output buffer 2
The comparison result output via the output terminal 04 and the output terminal 205 becomes a low level indicating a match, whereby the LSI tester determines that the semiconductor integrated circuit 200 is non-defective with no problem in high-speed operation.

[0036]

As described above, according to the present invention,
Even without using a frequency divider or an LSI tester, it is possible to obtain a comparison result of the logic match / mismatch between the output data signal of the circuit under test and the expected value signal. A test can be performed, and a defect caused by using the frequency divider can be eliminated. When the above comparison result is input to the LSI tester, the above-described high-speed operation test can be performed on the LSI tester.

According to the present invention, the comparison result obtained by gradually changing the phase of the expected value signal from the first phase to the second phase by a predetermined phase every predetermined number of patterns is stored in the second latch circuit. When the comparison result indicates a comparison result that indicates a match even once, the determination result as to whether or not a mismatch did not occur in any phase of the expected value signal by continuing to retain the stored content. Is extracted from the second latch circuit, so that a high-speed operation test result can be obtained accurately even if the phase of the expected value signal and the phase of the data signal are different.

Further, according to the present invention, an output terminal for extracting the output data signal of the circuit under test to the outside and an input terminal for inputting the output data signal of the circuit under test from the outside are directly connected on the test board. As a result, the comparison result of the logic match / mismatch between the data signal and the expected value signal is obtained without the intervention of the LSI tester.
A high-speed operation test exceeding the guaranteed standard of the SI tester can be performed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a conventional example.

[Explanation of symbols]

 100, 200 Semiconductor integrated circuit 101, 103, 115, 204 Output buffer 102, 104, 116, 205 Output terminal 105, 108, 113 Input terminal 106, 109, 114 Input buffer 107 Comparison circuit 110 First latch circuit 112, 203 Flip-flop 201 Second latch circuit

──────────────────────────────────────────────────続 き Continued on front page (51) Int.Cl. ⁷ Identification code FI H01L 27/04 T

Claims (2)

(57) [Claims] A comparison circuit for determining whether or not a logic of an output data signal of the circuit to be verified matches an expected value signal supplied from a first input terminal; and an output comparison result of the comparison circuit is transmitted to the circuit to be verified. If even one of the applied test patterns indicates a mismatch, a first latch circuit that holds the mismatch until an external initialization signal is input, and an output of the first latch circuit A first output terminal for outputting a signal to the outside, and a second output terminal for outputting an output data signal of the circuit under test to the outside
And a clock signal of one cycle of the test pattern
A third output terminal for outputting to the outside, and an output data signal of the circuit to be verified being inputted from outside
A second input terminal, and a latch signal of the first latch circuit, which is externally input;
And a third input terminal . 2. An output data signal of a circuit to be verified and a first input signal.
Logic match / mismatch with expected value signal given from input terminal
A comparison circuit for finding a match and an output comparison result of the comparison circuit are provided to the circuit to be verified.
If even one test pattern shows a mismatch
Indicates that there is a mismatch and an external initialization signal is input.
A first latch circuit that keeps holding until the signal is output, and an output signal of the first latch circuit is determined for each predetermined number of patterns. A second latch circuit that keeps holding until an external initialization signal is input, and a first latch circuit that outputs an output data signal of the circuit under test to the outside.
And a clock signal of one cycle of the test pattern
A second output terminal for outputting to the outside, and an output data signal of the circuit to be verified being inputted from outside
A second input terminal, and a latch signal of the first latch circuit, which is externally input;
And a third input terminal .