JP2674338B2 - Semiconductor integrated circuit test circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit for a semiconductor integrated circuit for testing a digital IC or an IC in which both digital and analog are mixed.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a conventional test circuit for a semiconductor integrated circuit.

A digital circuit 7 as a circuit under test inputs an input signal from an input terminal 8 and outputs an output signal to an output terminal 9. This digital circuit 7 includes a plurality of internal signal lines 1
The internal signal line 1 is connected to a shift register 2 which constitutes a test circuit.

The shift register 2 is constructed as follows. That is, the clock signal is supplied from the input terminal 6 to the flip-flops 10 to 12. The flip-flop 10 inputs the output of the internal signal line 1 and supplies the data output to the data selector 20. The flip-flop 11 inputs the output of the data selector 20 and supplies the data output to the data selector 19. The flip-flop 12 inputs the output of the data selector 19 and outputs the serial data output to the output terminal 18. A latch signal for latching the parallel data is supplied from the input terminal 17 to the data selectors 19 and 20. The data selectors 19 and 20 are composed of two AND gates and NOR gates.
The data selector 20 inputs the data output of the flip-flop 10 and the latch signal to one of the AND gates, and outputs the internal signal line 1 to the other AND gate.
An inverted signal of the latch signal is input, and data is selected and output according to the latch signal. The data selector 19 inputs the data output of the flip-flop 11 and the latch signal to one of the AND gates, and inputs the output of the internal signal line 1 and the inverted signal of the latch signal to the other AND gate to latch the data. Data is selected and output according to the signal.

Next, the operation of the test circuit for the above semiconductor integrated circuit will be described. First, when testing the digital circuit 7, a test pattern is input to the digital circuit 7 from the outside via the input terminal 8. And the output terminal 9
The output signal that is output to and the expected value are compared, and if both match, it is a good product, and if both do not match, it is a defective product. Next, if some of the internal signal lines 1 are not connected to the input terminal 8 or the output terminal 9, the internal signal line 1 is tested. In this case, the output of the internal signal line 1 is latched by the latch signal supplied from the input terminal 17, the clock signal is supplied from the outside through the input terminal 6, and the output of the internal signal line 1 is serialized at the output terminal 8. read out. Then, the internal signal line 1 read to the output terminal 4
Output is compared with its expected value, and if both match, it is a good product, and if both do not match, it is a defective product. In this way, the quality of the IC having the internal signal line that is not connected to the input terminal or the output terminal can be determined.

[0006]

However, in the conventional test circuit for the semiconductor integrated circuit described above, it is determined whether or not the output of the internal signal line 1 matches the expected value.
It is judged outside. Therefore, even if the expected output value of the internal signal line 1 has not changed, the internal signal line 1 is actually
Since it is necessary to read out the shift register 2 in order to confirm that the output state of 1 has not changed, there is a problem that the test time becomes long.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a test circuit for a semiconductor integrated circuit device which can shorten the test time.

[0008]

A test circuit for a semiconductor integrated circuit according to the present invention comprises as many output stages as the number of internal signal lines to be tested in the semiconductor integrated circuit, and the expected output value of the internal signal line. Latches and the expected output value does not change
A shift register that holds the latched data as it is, and a detection circuit that compares the output of the internal signal line with the parallel output of the shift register to detect a match or a mismatch between the two are featured.

[0009]

In the present invention, the shift register latches the expected output value of the internal signal line of the semiconductor integrated circuit to be tested. Therefore, the output state of the internal signal line can be known by comparing the output of the internal signal line with the parallel output of the shift register by the detection circuit and detecting a match or a mismatch. This makes it possible to determine the quality of the semiconductor integrated circuit. In this case, it is not necessary to latch new data in the shift register during the period when the expected output value of the output signal line does not change. Therefore, the test time is shortened as compared with the conventional test circuit of the semiconductor integrated circuit which reads the output of the internal signal line from the shift register for each test pattern and compares the output with the expected value outside the IC. You can

[0010]

Next, an embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a test circuit of a semiconductor integrated circuit according to a first embodiment of the present invention.

The digital circuit 7 as the circuit under test inputs the input signal from the input terminal 8 and outputs the output signal to the output terminal 9. This digital circuit 7 includes a plurality of internal signal lines 1
This internal signal line 1 is connected to a coincidence detection circuit 3 described later.

The shift register 2 is constructed as follows. That is, the clock signal is supplied from the input terminal 6 to the flip-flops 10 to 12. The flip-flop 10 serially inputs the expected output value of the internal signal line 1 from the input terminal 5 and latches it. The flip-flop 11 inputs the output of the flip-flop 10 and latches it. The flip-flop 12 inputs the output of the flip-flop 11 and latches it. The number of flip-flops in the shift register 2 is equal to the number of internal signal lines 1 in the digital circuit 7. For example, if the number of internal signal lines 1 is n (n: an integer of 1 or more), the number of flip-flops in the shift register 2 is n.

The coincidence detection circuit 3 is constructed as follows. That is, each of the EX-OR gates 13 to 15 inputs the output of the flip-flops 10 to 12 (parallel output of the shift register 2) to one input terminal thereof, and the output of the internal signal line 1 to the other input terminal thereof. Then, when both are in agreement, a Low level is output, and when both are inconsistent, a High level is output. The OR gate 16 is EX-
The outputs of the OR gates 13 to 15 are input, their logical sums are taken and output to the output terminal 4.

Next, the operation of the test circuit for the above semiconductor integrated circuit will be described. First, when the first data (the expected output value of the internal signal line 1) is input to the input terminal 5, the first data is input to the first-stage flip-flop 10 according to the clock signal supplied from the input terminal 6. Latched.
Next, when the second data is input to the input terminal 5, the first data latched in the shift register 10 is latched in the second-stage flip-flop 11 according to the clock signal at the input terminal 6, The data of 2 is latched in the flip-flop 10. By repeating such operation, the first data reaches the flip-flop 12. As a result, the Q outputs of the flip-flops 10 to 12 become parallel outputs of the shift register 2.

On the other hand, the digital circuit 7 which is the circuit under test
Depending on the test pattern input from the input terminal 8,
The output states of the output terminal 9 and the internal signal line 1 change.

If all the outputs of the internal signal line 1 match the parallel output of the shift register 2, that is, the expected output value of the internal signal line 1, the EX-OR gates 13 to 15 are provided.
Output is low level, output terminal 4
A Low level is output to. On the other hand, if any of the outputs of the internal signal line 1 does not match the expected output value of the internal signal line 1, one of the outputs of the EX-OR gates 13 to 15 becomes High level, and thus the output terminal 4 is High.
The h level is output. Therefore, if the output terminal 4 is at the Low level, it is a good product, and if it is at the High level, it is a defective product. In this way, by latching the expected output value of the internal signal line 1 in the shift register 2, the internal signal line 1
Of the digital circuit 7 can be determined, and the quality of the digital circuit 7 can be determined.

According to this embodiment, it is not necessary to latch new data in the shift register 2 during the period when the expected output value of the output signal line 1 does not change. Therefore, the test time can be shortened as compared with the conventional test circuit of the semiconductor integrated circuit which compares the output of the internal signal line and its expected value outside the IC.

FIG. 2 is a block diagram showing a test circuit of a semiconductor integrated circuit according to the second embodiment of the present invention. Since this embodiment is different from the first embodiment in the configuration of the coincidence detection circuit, the same parts in FIG. 2 as those in FIG. 1 are designated by the same reference numerals and detailed description thereof will be omitted.

The coincidence detection circuit 3a is constructed as shown below. That is, EX-NO of open drain output
Each of the R gates 24 to 26 inputs the output of the flip-flops 10 to 12 to its one input terminal and the output of the internal signal line 1 to the other input terminal, and when both of them match, their outputs are high. When the impedance state is reached and the two do not match, a Low level is output. The outputs of the EX-NOR gates 24 to 26 are output to the output terminal 4 via the inverter 23. The pull-up resistor 22 is connected to the input terminal of the inverter 23.

In the present embodiment, when all the outputs of the internal signal line 1 match the parallel output of the shift register 2, that is, the expected output value of the internal signal line 1, the outputs of the EX-NOR gates 24 to 26 will be output. Also becomes a high impedance state. In this case, the action of the pull-up resistor 22 inputs the high level to the inverter 23 and outputs the low level to the output terminal 4. On the other hand, if any of the outputs of the internal signal line 1 does not match the expected output value of the internal signal line 1, one of the EX-NOR gates 24 to 26 outputs a low level, which is input to the inverter 23 and output. High level is output to the terminal 4. Therefore, if the output terminal 4 is low level, it is a good product, and if it is high level, it is a bad product.

According to the present embodiment, as in the first embodiment, the expected output value of the internal signal line 1 is supplied as the parallel output of the shift register 2, so that the test time can be shortened. Further, since the OR gate is not used in the coincidence detection circuit 3, the number of elements can be reduced as compared with the first embodiment.

[0023]

As described above, according to the present invention, the shift register has the same number of output stages as the number of internal signal lines to be tested of the semiconductor integrated circuit and latches the expected output value of the internal signal lines. However, since the match or mismatch between the output of the internal signal line and the parallel output of the shift register is detected, the output state of the internal signal line can be known, and the quality of the semiconductor integrated circuit can be determined. In this case, since it is not necessary to latch new data in the shift register in the period in which the expected output value of the output signal line does not change, the test time is longer than that in the test circuit of the conventional semiconductor integrated circuit. Can be shortened.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a test circuit of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a test circuit of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a test circuit of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 1; Internal signal line 2; Shift register 3; Match detection circuit 4, 9; Output terminal 5, 6, 8; Input terminal 10, 11, 12; Flip-flop 13, 14, 15; EX-OR gate 16; OR gate 22; Pull-up resistor 23; Inverter 24, 25, 26; EX-NOR gate

Claims (1)

(57) [Claims] 1. A semiconductor integrated circuit having the same number of output stages as the number of internal signal lines to be tested, latching an expected output value of the internal signal lines , and during a period in which the expected output value does not change.
Includes a shift register that holds the latched data as it is, and a detection circuit that compares the output of the internal signal line with the parallel output of the shift register and detects a match or a mismatch between them. Test circuit.