JPH0560844A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To inspect an LSI easily by adding a memory which retains a data needed for testing and a coincidence/non-coincidence detection circuit which compares this memory data with an output of a sequential circuit. CONSTITUTION:In the case of a test, a needed data is input from a q-bit ROM 3 to an FF1 by using a clock CK 12 and a needed data is input also to an input signal 15. Since the FF1 retained data, an input signal 21 to a combination circuit 2 and an input signal 15 from an outside become a fixed value and a value of an output signal 16 of the circuit 2 and that of an input signal 22 to the FF1 are also fixed according to values of the signal 21 and the signal 15. Then, LSI is returned to a normal mode by a test mode switching signal MD11, n values of the signal 22 is input to the FF1, and then an expectation value of the FF1 which is retained at the ROM 3 is output to a coincidence/non- coincidence detection circuit DET 4. The DET 4 compares the output signal 21 of the FF1 with an output signal 23 of the ROM 3 and then outputs a notice signal DS 17. When the DS 17 all matches, it is regarded to be acceptable.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor integrated circuit,
In particular, it relates to a semiconductor integrated circuit having a test circuit.

[0002]

2. Description of the Related Art At present, circuits are becoming larger and more complex due to the progress of LSI technology. If all circuits are to be tested in these LSIs, the test method becomes complicated and the test time becomes long. Therefore, in order to simplify the evaluation and inspection of LSI as much as possible. When designing an LSI, a test circuit or a test function is often provided inside the LSI.

One of the test circuits of this type is called a scan path method. FIG. 3 is a diagram showing an example of a conventional semiconductor integrated circuit testing method. The semiconductor integrated circuit shown in FIG. 3 receives as inputs a flip-flop group (hereinafter referred to as FF) 1 including n flip-flops, n output signals 21 from FF1 and m input signals 15 from the outside. A combinational circuit 2 that outputs n output signals 22 to the FF 1 and p output signals 16 to the outside is provided.
11 is a test mode switching signal (MD), 12 is F
A clock (hereinafter CK) for operating F1, 13 is a serial data input terminal (hereinafter DI) at the time of test, 1
4 is an output terminal for serial data at the time of testing (hereinafter DO)
Is.

Generally, when looking inside the LSI, it can be divided into a sequential circuit such as a flip-flop and a combinational circuit such as an AND gate. When the MD 11 is switched and in the test mode, all n FF1s therein are serially connected so that they are connected as if they were n-bit shift registers. Then, input CK12 and n F
Arbitrary data required for the test is input from DI13 to F1 and arbitrary data required for the test is also input to the input signal 15. Since the n flip-flops hold the data, the input signal 21 and the input signal 15 of the combinational circuit 2 have fixed values, and the values of the output signals 16 and 22 of the combinational circuit 2 are also the input signal 21 and the input signal 15. Fixed according to the value of.

Then, the MD 11 returns the LSI from the test mode to the normal mode, one CK12 is input, and the values of the n output signals 22 are input to the n FF1. Also,
Return the LSI to the test mode by MD11, connect all FF1 serially, and input n from CK12
The individual DO 14 is output.

By repeating the above operation, the input signal 1
If the values of 3 and 15 are determined, the output signals 14 and 16 are uniquely
Since the value of is determined, the output signals 14 and 1
If the value of 6 is different from the expected value, the LSI
You can see that there is a defect inside. In addition, if this test method is used, it is possible to easily set / detect even in an internal state where it is difficult to set from the outside because the input / output is in the middle of the circuit or it is difficult to see from the outside.

[0007]

FIG. 2B is a diagram showing a test time by the conventional scan path method. In the conventional test method by the scan path method described above, FIG.
As shown in, time a at which data is input to n FF1
And one clock time b in normal mode and n FF1s
There is a time c for outputting the data, and the total time is (2 × n + 1) clocks.

In this method, the larger the value of n, the longer the test time, and the wasted time (2) of preparation and detection for operating the inside by one clock.
A problem arises that the ratio of n) increases.

[0009]

A semiconductor integrated circuit of the present invention is a semiconductor integrated circuit having a plurality of combinational circuits and a plurality of sequential circuits, in which a plurality of data necessary for testing the combinational circuits and the sequential circuits are stored. A memory for holding, mode switching means for inputting the output data of the combinational circuit to the sequential circuit during normal use and inputting the data of the memory for testing, and comparing the output data of the sequential circuit with the output data of the memory And a match / mismatch detection circuit for outputting a match / mismatch result.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1 is a block diagram showing an embodiment of a semiconductor integrated circuit of the present invention, and FIG. 2A is a diagram showing a test time in FIG.

The semiconductor integrated circuit of this embodiment is composed of FF1 and F
A combinational circuit 2 which inputs n output signals 21 from F1 and m input signals 15 from the outside and outputs n output signals 22 to FF1 and p output signals 16 to the outside And a q-bit ROM 3 of n bits or less that holds a data value set in FF1 and an expected value output from FF1, q output signals 23 of q-bit ROM 3 and values of output signal 21 of FF1. A detection circuit (hereinafter referred to as DET) 4 for detecting a match / mismatch is provided. Reference numeral 11 is a test mode switching signal (hereinafter, MD), 12 is a clock (hereinafter, CK) for operating the FF 1, and 17 is a match / mismatch result notification signal (hereinafter, DS).

Next, the operation of this embodiment will be described.
To simplify the description, the operation when n = q will be described first. The value of the input signal 22 is input to the FF1 during the LSI normal operation, and the FF1 is input by the MD11 during the LSI test.
The FF1 has a function of inputting the value of the output signal 23 of the q-bit ROM 3 to the. When testing, first FF
The data required for the test from the q-bit ROM3 to CK1
2 is used to input any data required for the test to the input signal 15. Since the FF1 holds the data, the input signal 21 to the combinational circuit 2 and the input signal 15 from the outside have fixed values, and the output signal 16 of the combinational circuit 2 and the value of the input signal 22 to the FF1 are also F.
It is fixed according to the output signal 21 of F1 and the value of 15 from the outside.

Then, the LSI is returned from the test mode to the normal mode by MD11, one CK12 is inputted, and FF is inputted.
The values of n input signals 22 to 1 are input to FF1. Then, the expected value of FF1 held in the q-bit ROM 3 is output from the q-bit ROM 3 to the DET 4. DET4
Compares the value of the output signal 21 of FF1 with the output signal 23 of the q-bit ROM 3 and outputs DS17.

When the value of n exceeds "16", for example, q
If the number of beats of the bit ROM 3 is set to n as it is, the number of bits of the q bit ROM 3 increases, which is not a good idea for an LSI. Therefore, it is advisable to set the value of q to "16" at the maximum and perform the data input from the q-bit ROM 3 to the FF1 and the match / mismatch detection in the test mode separately for n / q (= r: rounding up after the decimal point) times. ..

In the LSI test, if it can be confirmed that the designed circuit operates as expected, it is regarded as passed. Therefore, if the DS17 produces all the matching results during the LSI test according to the embodiment, the points that can be confirmed using this test method.
Items can be considered pass.

In this embodiment, when n = q, FIG.
As shown in, time a to input data to FF1 and FF1
2 is much shorter than the conventional example shown in FIG. 2B, and the total time is (2 × n
-2) This means that the time for the clock is shortened. Even when the data input to the FF1 is divided into r times when the value of n is large, it means that the time for (2 × n−2 × r) clocks is shortened.

[0017]

As described above, the present invention has the effect that the test time can be shortened by adding a small amount of hardware to the conventional semiconductor integrated circuit using the test method of the scan path method. Have. Further, in the conventional test method, since the output data from the LSI is compared with the expected value outside the LSI to be tested, a circuit / program for comparison is required outside the LSI, but the present invention is used. For example, the effect of facilitating the inspection of the LSI can be obtained only by adding the function of detecting the match / mismatch detection result to the outside of the LSI.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a semiconductor integrated circuit of the present invention.

FIG. 2 is a diagram showing a test time when the present invention is used and when a conventional scan path method is used.

FIG. 3 is a diagram showing an example of a conventional semiconductor integrated circuit testing method.

[Explanation of symbols]

 1 flip-flop group (FF) 2 combinational circuit 3 q-bit ROM 4 n-bit match / mismatch detection circuit (DET) 11 test mode switching signal (MD) 12 clock (CK) 13 input terminal for serial data during test ( DI) 14 Serial data output terminal (DO) 15 test signal 16 output signal 17 match / mismatch result notification signal (DS) 21 FF1 output signal 22 FF1 input signal 23 q-bit ROM3 output signal

Claims (1)

[Claims] 1. A semiconductor integrated circuit having a plurality of combinational circuits and a plurality of sequential circuits, comprising: a memory that holds a plurality of data necessary for testing the combinational circuits and the sequential circuits; A mode switching means for inputting the output data of the combinational circuit and for inputting the data of the memory at the time of testing, and an output of the sequential circuit and the output data of the memory are compared, and a match / mismatch is output. A semiconductor integrated circuit comprising: a detection circuit.