JPH02134842A - Macrocell of integrated circuit - Google Patents

Abstract

PURPOSE:To facilitate reduction of the number of external input terminals compared to that of conventional circuitry by a method wherein an N-bit shift register which receives N-bit serial input test data and converts them into N-bit parallel test data to supply them to selectors is added. CONSTITUTION:The macrocell 1 of an integrated circuit has test terminals through which test data for a functional test are inputted and a plurality of selectors 3i which select input data D and test data SP and supply them to an internal circuit 4, and adds an N-bit shift register 2 which receives N-bit serial input test data STS and converts them into N-bit parallel test data SP to supply them to the selectors 3i. For instance, (n) output terminals Ni of the N-bit shift register 2 having the input terminals TC and TSD are connected to the input terminals of the selectors 3i respectively and the serial N-bit test data STS inputted from the external input terminal TSD are read bit by bit by the falls of clock pulses CK inputted from the external input terminal TC.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to macrocells of integrated circuits.

[Conventional technology]

FIG. 3 is a block diagram of an example of a macrocell of a conventional integrated circuit.

In the macrocell under test 1b, N-bit test data Spl is input from n external input terminals TI to one input terminal of each of n selectors 3I.

Further, N-bit normal input data DI from other macrocells are input to other input terminals of the n selectors 3I, respectively.

The selector 3I is located inside the macrocell under test 1b,
Depending on the control signal S input from the external input terminal T, either the test data Spl or the normal input data D1 is selected and supplied to the internal circuit 4.

[Problem to be solved by the invention]

The macrocell of the conventional integrated circuit described above has a configuration in which N-bit test data is input in parallel to the macrocell under test. , 2N external input terminals are required to input test data,
There is a drawback that as the number of bits of test data increases, the number of external input terminals increases accordingly.

[Means to solve the problem]

A macro cell of an integrated circuit according to the present invention has a test terminal for inputting test data for functional testing, and a plurality of selectors that select the input data and the test data and supply the selected data to an internal circuit. , N bits of serial test data are input, and N
It is constructed by adding an N-bit shift register that converts the test data into bit parallel test data and supplies the data to the selector.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of the present invention.

The macrocell under test 1 has an input terminal T. The macrocell under test 1 is the same as the conventional macrocell 1 except that the n output terminals of the N-bit shift register 2 having TSD and TSD are respectively connected to the input terminals of the selector 31 shown in FIG.

When the clock pulse CK input from the external input terminal Tc falls (or rises), the external input terminal T
The serial N-bit test data SA input from 'so' is read one bit at a time.

N-bit test data Sp subjected to serial-to-parallel conversion by the N-bit shift register 2;

from node NI to selector 3. is input to one input end of the .

N-bit normal input data DI from macrocells other than the macrocell under test 1 is input to the other end of each selector 31 .

The selector 31 is located inside the macrocell under test 1, and selects either the test data S2 or the normal data D1 according to the control signal Sc input from the external input terminal T, and controls the internal circuit 4 to respond to the selected data. is supplied to the input terminal 11.

FIG. 2 is a block diagram of a second embodiment of the invention.

Macrocell under test 1. are N-bit shift register 2 and selector 3. in FIG. A corresponding latch circuit between 5.
and a timing generation circuit 4 that supplies timing to it.
The macrocell under test 1 is the same as the macrocell under test 1 of the first embodiment except for the addition of the following.

N-bit test data SpI subjected to serial-to-parallel conversion by the N-bit shift register 2 is input to each corresponding latch circuit 5I.

Each latch circuit 5I has an external input terminal T.

The test data 3 is controlled by a timing generation circuit 6 that generates timing using a clock pulse CK input from the external input terminal TSD.
When all N bits of data have been input to shift register 2, N-bit parallel test data Sp+ is latched at the same time until the next N bits of serial data are completely input to shift register 2. The previously input test data Spl is held.

The N-bit test data SLI output from the latch circuit 5I is input to the selector 31, respectively.

N from any macrocell other than the macrocell under test 1a
The normal data inputs DI of the bits are respectively selector 3
1 and performs the same operation as in the first embodiment.

〔Effect of the invention〕

As explained above, the present invention reduces the number of external input terminals compared to conventional circuit configurations by arranging shift 1 to registers in the test data input portion of the macrocell under test and inputting the test data as serial data. There is an effect that can be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a block diagram of a second embodiment of the present invention, and FIG. 3 is a block diagram of an example of a macro cell of a conventional integrated circuit. 1.1. Macro cell under test, 2 N-bit shift register, 3I i-th selector, 4 internal circuit, 5 timing generation circuit, D1 to Dfi.
. . . 1st to nth input data, Spl . . . i-th test data. Agent: Susumu Uchihara, Patent Attorney Figure 2, Figure 3

Claims (1)

[Claims] In a macro cell of an integrated circuit having a test terminal for inputting test data for performing a functional test, and a plurality of selectors that select the input data and the test data and supply the selected data to an internal circuit, the N-bit serial test data is 1. A macro cell of an integrated circuit, characterized in that an N-bit shift register is added for inputting N-bit parallel test data, converting the data into N-bit parallel test data, and supplying the converted data to the selector.