JP3147039B2 - Integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an integrated circuit including a sequential circuit, and more particularly to an AC characteristic defect inspection circuit having a closed path inside the integrated circuit from the sequential circuit to the sequential circuit.

[0002]

2. Description of the Related Art The highest operating frequency of a semiconductor integrated circuit is determined by a path having the longest transmission time in an integrated circuit among signal transmission paths from an output of a sequential circuit to an input of the sequential circuit via a combinational circuit. Is done. This path is called a critical path.

Whether the operating frequency of the manufactured integrated circuit satisfies the design value can be checked by checking whether the propagation delay time of the critical path satisfies the design value. However, it is difficult to measure the signal waveform of the critical path existing inside the integrated circuit covered with the insulating protection film or the like without destroying the manufactured integrated circuit to determine the quality of the transmission delay time.

In order to solve this problem, a scan method is adopted as an inspection method of an integrated circuit, and a state change of a starting sequential circuit of a critical path is set to propagate to an end sequential circuit. Japanese Patent Laid-Open No. 4-128661 ("Line Delay Test Apparatus") discloses a method in which the value of an end point sequential circuit is determined by a scan method by stepping at an operating frequency to determine the quality of the circuit. In consideration of the increase in transmission delay due to change or aging, this method has a drawback in that a test at a frequency much higher than the actually used frequency is required, and a high-performance and expensive test device is required.

In addition, a circuit having a reference transmission delay time is formed in an integrated circuit, and the same input signal as that of the circuit to be measured is provided, so that the transmission delay time of the circuit to be measured satisfies the reference time. Japanese Unexamined Patent Publication (Kokai) No. 3-10 / 1990 discloses a method of judging pass / fail by confirming using a latch built in the system.
1245 (“Semiconductor integrated circuit device and its manufacturing method”). However, since a circuit having a reference propagation delay time is also manufactured in the same process at the same time as the circuit to be measured, it is tentatively manufactured. When the propagation delay time increases due to a failure, the propagation delay time of the circuit having the reference propagation delay time together with the circuit to be measured also increases, and this method has a disadvantage that defective products cannot be found.

[0006]

The first problem is that, in the prior art, a test circuit other than the scan method is not provided on the integrated circuit, and the transmission delay time of the critical path is determined only by the function of the integrated circuit test apparatus. In order to inspect whether or not satisfies the design value, a high-performance and expensive inspection device is required.

The reason is that the transmission delay may increase during actual use due to temperature change or aging, and it is necessary to check whether the transmission delay time of the critical path satisfies the design value even during actual use. This is because an inspection at a frequency much higher than the actually used frequency is required. High-performance inspection equipment that supports high frequencies increases the manufacturing cost of integrated circuits.

A second problem is that, in the prior art, in order to check whether a transmission delay time of a circuit under test constituting a critical path in an integrated circuit satisfies a design value, a reference is required in the integrated circuit. If a circuit having a propagation delay time and a circuit that determines that the circuit under test operates faster than the reference circuit are built in the integrated circuit, it is not possible to correctly determine a defect in AC characteristics due to a manufacturing defect of the integrated circuit. The point is that there are times.

The reason is that a circuit having a reference transmission delay time is also manufactured in the same process at the same time as the circuit to be measured. Therefore, if the transmission delay time increases due to manufacturing failure of the integrated circuit, the circuit to be measured is At the same time, the transmission delay time of the circuit having the reference transmission delay time increases, and a defective product cannot be found.

According to the present invention, in an integrated circuit including a sequential circuit and a combinational circuit, a path to be inspected from an output of the sequential circuit for determining the highest operating frequency of the integrated circuit to an input of the sequential circuit via the combinational circuit is determined. It is therefore an object of the present invention to reliably determine a non-defective product having AC characteristics, which has a sufficient margin for an increase in transmission delay due to a temperature change or an aging change in actual use.

Further, the present invention makes it possible to perform a function test at an actually used frequency and an AC characteristic test without using a high-performance and expensive integrated circuit inspection apparatus, thereby reducing the manufacturing cost of the integrated circuit. Also aim.

[0012]

SUMMARY OF THE INVENTION An integrated circuit according to the present invention includes a signal transmission path from an output of a sequential circuit for determining the highest operating frequency to an input of the sequential circuit via a combinational circuit.
It verifies that there is enough delay margin to prevent malfunction due to increase in transmission delay time due to temperature change and aging during actual use. More specifically, a signal delay means (4 in FIG. 1) which outputs the same logical value after a certain period of time with the output of the combinational circuit as an input, and an end point sequential circuit for the path under test for determining the highest operating frequency. The output of the delay signal holding means (5 in FIG. 1) which takes in and holds the output of the delay means as an input, the output of the end point sequential circuit of the path under test, and the output of the delay signal holding means are compared to determine whether they match. And a determination means (6 in FIG. 1) for determining the quality of the integrated circuit.

[0013] The starting point sequential circuit of the path under test that determines the highest operating frequency of the integrated circuit changes the output signal according to the input of the clock signal. The combinational circuit of the path under test performs a logical operation according to the change of the signal, and changes the output signal after a processing time peculiar to the manufactured combinational circuit. The end point sequential circuit of the path under test captures the output of the combinational circuit in response to the input of the clock signal, and holds this value. On the other hand, the signal delay means receives the output of the combinational circuit as an input and outputs the same logical value as the input after a time corresponding to the delay margin required for the path under test. The delay signal holding unit captures the output of the signal delay unit by using the same clock signal as the end point sequential circuit of the path under test, and holds the value.

If there is a sufficient delay margin required for the path under test, the end point sequential circuit of the path under test and the delay signal holding means can simultaneously capture the same value by the clock signal. On the other hand, when the delay margin required for the path under test does not sufficiently exist, the end point sequential circuit of the path under test correctly holds the value output by the combinational circuit, but the delay signal holding unit stores the new state value. Retain incorrect values because they cannot be captured. For this reason, the determination means can compare the output of the end point sequential circuit of the path under test with the output of the delay signal holding means, and determine whether the AC characteristics of the integrated circuit are good or not based on whether or not they match.

[0015]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, an embodiment of the present invention includes a sequential circuit 1, a combinational circuit 2, and a sequential circuit 3 constituting a path to be inspected. After inputting 12 and performing a logical operation, the signal is output as a signal 13. The sequential circuit 3 outputs the clock signal 15
The signal 13 is input in synchronism with, and this value is held. The AC characteristic inspection section of the path to be inspected includes a signal delay unit 4, a delay signal holding unit 5, and a determination unit 6.
Outputs a signal 13 which is the output of the combinational circuit 2 and outputs the same waveform as the signal 16 after a predetermined time. The delay signal holding means 5 receives the signal 16 in synchronization with the clock signal 15 and holds this value. The determination means 6
The output signal 14 of the sequential circuit 3 and the output signal 17 of the delay signal holding unit 5 are input to determine whether or not the AC characteristics of the path to be inspected are good.

Next, the operation of the embodiment of the present invention will be described.
This will be described in detail with reference to the time chart of FIG.

The sequential circuit 1 constituting the path to be inspected holds the value A0 in the initial state (time T0) and outputs this to the signal 12, and the combinational circuit 2 outputs the value B0 to the signal 13 as a result of the logical operation. It is assumed that it is output. The value of the signal 10, which is the input of the sequential circuit 1, changes from A0 to A1 at time T0, but the value held by the sequential circuit 1 does not change to A0.

At time T1, the sequential circuit 1 outputs the clock signal 1
The value A1 is fetched from the input signal 10 in synchronization with 1, and this value is held and output to the signal 12. Combination circuit 2
Inputs the new logical value A1 of the signal 12 and outputs the result B1 to the signal 13 after the logical operation.

If the result of the operation is different from the previous value, the logical value of signal 13 changes. At time T1, the sequential circuit 3 holds the logical value B0. At time T2, the sequential circuit 3 captures and holds the logical value B1 from the signal 13 in synchronization with the clock signal 15, and outputs this value as the signal 14.

When the value of the signal 13 changes from the logical value B0 to the logical value B1, the signal delay means 4 outputs the output value to the signal 16 after a specific time corresponding to the delay margin required for the path under test.
Change from 0 to B1.

The signal holding means 5 receives the signal 16 in synchronization with the clock signal 15, holds the value, and outputs the value to the signal 17. At time T1, the signal holding means 5 outputs the logical value B.
Holds 0. If the manufactured integrated circuit has a good AC characteristic, the logic value B1 can be taken from the signal 16 at the time T2 in synchronization with the clock signal 15 and held, and this value can be output to the signal 17.

FIG. 3 is a time chart when the AC characteristics of the manufactured integrated circuit are defective.

When the transmission delay time of the entire integrated circuit is later than the design value due to a manufacturing defect, the combinational circuit 2 processes the logical value A1 which is taken in by the sequential circuit 1 and output as the signal 12 in synchronization with the clock signal 11. The time at which the logical value B1 is output to the signal 13 is later than that of the non-defective product. Also in this case, the signal delay means 4 changes the value of the signal 13 from the logical value B0 to the logical value B1.
, The output value to the signal 16 is changed from B0 to B1 after a specific time corresponding to the delay margin required for the path under test.

In FIG. 3, at time T1, the signal holding means 5
Holds the logical value B0 and outputs this value to the signal 17. At time T2, the signal holding unit 5 inputs a value from the signal 16 in synchronization with the clock signal 15, but the value of the signal 16 does not change to the correct value because the transmission delay time is slower than the design value, and The logic value B0 is fetched and held again, and this value is output to the signal 17.

The judging means 6 inputs the values of the signal 14 and the signal 17, and if the two logical values match, the manufactured integrated circuit judges that the integrated circuit is good in AC characteristics. judge.

Next, embodiments of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 4, the embodiment of the present invention includes a sequential circuit 210, a combinational circuit 220, and a sequential circuit 230 forming a path to be inspected. The combinational circuit 220 receives the output signal 120 of the sequential circuit 210, performs a logical operation, and outputs a signal 130. The sequential circuit 230 inputs the signal 130 in synchronization with the clock signal 110 and holds this value.

In order to inspect the AC characteristics of the inspected path,
The circuit includes a signal delay circuit 240, a delay signal holding circuit 250, and a pass / fail determination circuit 260. The signal delay circuit 240 receives the signal 130 output from the combinational circuit 220 as an input, and outputs the same logical value as the input to the signal 160 after a specific time corresponding to the delay margin required for the path under test. The delay signal holding circuit 250 receives the signal 160 in synchronization with the clock signal 110 and holds this value. Pass / fail judgment circuit 26
0 inputs the output signal 140 of the sequential circuit 3 and the output signal 170 of the delay signal holding circuit 250 to determine whether or not the AC characteristic of the path to be inspected is good.

The present invention is applicable to any arithmetic circuit for the combination circuit of the path to be inspected. In this embodiment, it is assumed that the combination circuit 220 is a 3-bit parity generation circuit. Output signals 121 and 122 of the sequential circuits 211 and 212 are connected to inputs of the combinational circuit 220 other than the path to be inspected. As shown in FIG. 5, the 3-bit parity generation circuit is configured by a combination of exclusive OR circuits.

As shown in FIG. 4, the clock signal 110 and the input signal 1 of the sequential circuits 210, 211 and 212
00, 101 and 102 are supplied from the input terminals of the integrated circuit, and the output signal 180 of the pass / fail judgment circuit is connected to the output terminal of the integrated circuit. Sequential circuits 210, 211, 212,
230 and the delay signal holding circuit 250
Use type flip-flops.

As a path to be inspected, a path that limits the maximum operating frequency of the integrated circuit is selected by delay estimation based on delay parameters of circuit elements. Signal delay circuit 240
Is configured to delay transmission of a logic signal by a time corresponding to a delay margin required for a path under test.

Next, an embodiment of the present invention will be described in detail with reference to FIGS.

In the initial state (time T0), the input signals 100, 101, and 102 of the integrated circuit are all logic 0, and the logic 0 is held in the sequential circuits 210, 211, and 212. The sequential circuits 210, 211, 212 are D
As shown in the truth table of FIG. 6, a new value is fetched and held in synchronization with the rise of the clock signal.

When the clock signal rises at the beginning of time T1, the sequential circuits 210, 211, and 212 take logic 0 from the signals 100, 101, and 102. At time T1, the signal 100 changes from logic 0 to logic 1. Signals 101 and 102 are assumed to maintain logic 0 throughout the following description.

When the clock signal rises at the beginning of the time T2, the sequential circuit 210 takes in and holds the logic 1 from the signal 100 and outputs it to the signal 120. The sequential circuits 211 and 212 output the logic 0 to the signals 121 and 12
Output to 2. Since the combinational circuit 220 is a 3-bit parity generation circuit, the output to the result signal 130 of the arithmetic processing is changed from logic 0 to logic 1. The time from when the clock signal 110 rises to when the signal 130 becomes logic 1 is defined as Tpd0.

The sequential circuit 230 is composed of a D type flip-flop and operates as shown in the truth table of FIG. When the clock signal rises at the beginning of time T3, the sequential circuit 230 captures and holds the logic 1 from the signal 130, and changes the output to the signal 140 from logic 0 to logic 1.

At time T2, signal 130 changes from logic 0 to logic 1
, The signal delay circuit 240 changes the output to the signal 160 from logic 0 to logic 1 after the designed natural time Tpd1.

The delay signal holding circuit 250 is constituted by a D type flip-flop and operates as shown in the truth table of FIG. 6. When the clock signal 110 rises at the beginning of time T3, the delay signal holding circuit 250 Fetch a new value from 160 and hold. If the sum of transmission delay times Tpd0 and Tpd1 of the manufactured integrated circuit is smaller than one cycle time Tf of clock signal 110, delay signal holding circuit 250 takes and holds logic 1 from signal 160, and holds this value. Is output to the signal 170.

The pass / fail judgment circuit 260 inputs and compares the signal 140 and the signal 170. If the logical values match, the transmission delay time of the path to be inspected is changed with respect to temperature change and aging change in actual use. It has sufficient margin and determines that the AC characteristics are non-defective, and outputs a logic 0 indicating non-defective.

Next, the operation when the AC characteristics are defective will be described with reference to FIG.

The operation of each part from time T0 to T2 is the same as that in the case of the non-defective AC characteristic shown in FIG. When the clock signal 110 rises at the beginning of the time T3, the delay signal holding circuit 250 takes in a new value from the signal 160 and holds it. The sum of the transmission delay times Tpd0 and Tpd1 of the manufactured integrated circuit is one cycle time Td of the clock signal 110.
If f is greater than f, signal 160 is still at logic 0 at the first rising edge of clock signal 110 at time T3.
Does not change to logic 1 and the delay signal holding circuit 250
Fetches and holds the logic 0 again from the signal 160, and continuously outputs this value to the signal 170.

The pass / fail judgment circuit 260 receives and compares the signal 140 and the signal 170, and when the logical values do not match,
The transmission delay time of the path to be inspected does not have a sufficient margin for a temperature change or an aging change in actual use, and it is determined that the AC characteristic is defective, and a logic 1 representing the defective is output.

[0044]

The first effect is that there is a sufficient delay time margin with respect to an increase in transmission delay time of a path to be inspected which is a critical path in an integrated circuit due to a temperature change or an aging change in actual use. It is an object of the present invention to determine whether or not the test can be performed by using a functional test at room temperature for a short period of time at a practical use frequency without using an expensive test apparatus, thereby reducing manufacturing costs.

The reason for this is that simply adding a simple AC characteristic inspection circuit for examining the delay margin of the path under test to an integrated circuit for manufacturing the circuit causes the propagation delay time of the critical path due to a temperature change or an aging change in actual use. In order to check that there is sufficient delay time for the increase, it is not necessary to use a high-performance and expensive test device capable of performing a test at a frequency much higher than the actually used frequency. is there.

The second effect is that it is possible to reliably determine a defective AC characteristic due to a defective semiconductor manufacturing.

The reason is that, even if the delay of the AC characteristic inspection circuit together with the path to be inspected increases due to the AC characteristic defect due to semiconductor manufacturing defect, the delay time due to the temperature change and the aging change in actual use is required. This is because the transmission delay time of the signal delay circuit which gives a given delay margin is extended, so that a defective AC characteristic is not erroneously determined as a non-defective product.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an integrated circuit of the present invention.

FIG. 2 is a time chart showing the operation of the embodiment of the integrated circuit of the present invention.

FIG. 3 is a time chart showing the operation of the embodiment of the integrated circuit of the present invention.

FIG. 4 is a circuit diagram showing an embodiment of the integrated circuit of the present invention.

FIG. 5 is a circuit diagram showing a detailed configuration of a 3-bit parity generation circuit.

FIG. 6 is a truth table showing an operation of a general D-type flip-flop.

FIG. 7 is a time chart showing the operation of the embodiment of the integrated circuit of the present invention.

FIG. 8 is a time chart showing the operation of the embodiment of the integrated circuit of the present invention.

FIG. 9 is a diagram showing a conventional integrated circuit inspection technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Sequential circuit 2 Combination circuit 3 Sequential circuit 4 Signal delay means 5 Delay signal holding means 6 Pass / fail judgment means 10 Input signal 11 Clock signal 12-14 Signal 15 Clock signal 16-17 Signal 100-102 signal 110 Clock signal 120-180 Signal 210 to 212 Sequential circuit 220 Combination circuit 230 Sequential circuit 240 Signal delay circuit 250 Delayed signal holding circuit 260 Pass / fail judgment circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/04 G01R 31/28 G01R 31/319 H01L 21/822

Claims (1)

(57) [Claims] 1. An integrated circuit including a sequential circuit and a combinational circuit, wherein an output of a first sequential circuit that determines a maximum operating frequency of the integrated circuit ranges from an output of the first sequential circuit to an input of a second sequential circuit via the combinational circuit. A path under test, a signal delay unit that receives an output signal of the combinational circuit and outputs the output signal after a predetermined time, and an end point sequential circuit of the path under test captures the output signal of the combinational circuit, A delay signal holding unit that receives and holds the output signal of the signal delay unit as an input, and compares an output signal of the end point sequential circuit of the path under test with an output signal of the delay signal holding unit to determine whether they match. Determining means for determining whether the AC characteristics of the integrated circuit are good or not based on whether the integrated circuit is good or not.