KR950008421Y1 - Test window constrol circuit of in circuit tester using a gray code - Google Patents

Abstract

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Description

Test window control circuit of in-circuit tester using gray code

1 is a function generation block diagram using a conventional gray code.

2 is a block diagram showing an embodiment of a conventional start and control circuit.

3 is a function generation block diagram using the present invention gray code.

4 is a block diagram showing an embodiment of the present invention start and control circuit.

5 is a timing chart according to FIG.

6 is an explanatory diagram of a comparison between the conventional test window and the present invention.

7 is an explanatory diagram of a 74HC373 IC for explaining a conventional problem.

* Explanation of symbols for main parts of the drawings

1: CPU 2: Clock generation circuit

3: gray code generating circuit 4: function generating circuit

5: Start and end control circuit 6: Measurement object

12: Start Reach 13: End Reach

14: first window stretch 15: second window stretch

16: Start Comparator & Litch 17: End Comparator & Litch

18: first window comparator and latch 19: second window comparator and latch

20,21: Di-Flip flop 22,23: T-Flip flop

The present invention relates to a digital in-circuit tester (1CT) that automatically checks the defect status of a digital IC on a mounted PCB. In particular, the test window is modified in various forms to create various stimulus functions. The present invention relates to an in-circuit test window control circuit using a gray code which has been expanded.

In general, many kinds of devices are mounted on a PCB, and it is impossible to quantitatively and individually inspect the defect status of each of these devices with a general measuring instrument.

Therefore, an in-circuit tester is used to measure the devices automatically at one time. This is done by connecting the applied signal from the measuring circuit of the equipment to one side of the device and connecting the electrical output signal to the measuring circuit.

The function generation using the conventional gray code is based on the clock generation circuit 2 which generates the clock under the control of the CPU 1 and the clock of the clock generation circuit 2 as a reference clock as shown in FIG. A gray code generating circuit (3) for generating a gray code, a function generating circuit (4) for making a function based on the gray code and sending it to the measurement object (6), and a test window of the function generating circuit (4) And a start and end control circuit 5 for determining.

Referring to the operation, when the clock is generated by the clock generation circuit 2 under the control of the CPU 1, it becomes the reference clock of all circuits and is input to the gray code generation circuit 3.

In addition, the gray code generating circuit 3 generates a gray code and sends it to the function generating circuit 4, and the function generating circuit 4 generates a signal having a constant period from F ₁ to F _16, where the start and end control circuits are generated. The test window created in (5) determines the start and end of the test.

In addition, when the input to the measurement object (6) by the combination of these functions, the output generates a number of unique signals.

2 is a block diagram showing an embodiment of the start and end control circuits 5, each of which has four bits of data and a strobe signal to latch into a register, and an end latch 7 and the start latch. (6) and synchronizing the outputs of the first and second comparators and latches (8) (9) and the outputs of the comparators and latches (8) (9) comparing the outputs of the end latches (7) and respective gray codes. And latches 10 and 11 that latch to the clock to generate start and end signals.

Referring to the operation of FIG. 2, each 4-bit data and strobe signal are latched at the start latch 6 and the end latch 7, and according to the clocks of the first and second comparators and the latches 8 and 9, respectively. The output is only output when it is equal to the changing gray code, and latched back to the clock to synchronize to create a window waveform at the beginning and at the end.

However, in the prior art as described above, since the test window has a constant shape indicating only the beginning and the end, if the IC to be tested has a pin for performing both input and output, the general waveform input (F ₁ to F ₁₆ : IC is tested) The various waveforms that are input at the time of input) cannot maintain the consistency of the test output. Therefore, it is necessary to distinguish between areas that should be tested (parts to be sensed) and areas that should not (parts not to be sensed).

For example, if an error such as high impedance is encountered during an IC test to be measured, an abnormality may occur in the result value, and a good IC may output a wrong CRC (cyclic re-dundancy check) value, which may cause a fatal error in the repeatability of the test equipment. There was a flaw that could be.

In other words, when testing a typical IC, digital ICT exchanges inputs and outputs simultaneously. However, in the case of the IC (74HC373) having an OE terminal as shown in FIG. 7, the OE becomes high while signaling the CP terminal, and the output (Q ₁ to Q ₇ ) has a high impedance state (high degree). Is not low).

If you continue to test the IC in the above case, there is a problem in the test because it does not know what value will come in when the device senses the output waveform for the output (Q ₁ ~ Q ₇ ).

In this situation, when the OE is high when performing I / O at the same time, it is impossible to read the value. Therefore, sensing should be prevented while the OE is high and the output according to the input should be read only when the OE is low.

Therefore, when the test results such as high impedance during the test, an abnormality occurs in the result value. Therefore, a faulty IC can cause a fatal error in the repeatability of the test equipment by outputting an incorrect CRC value.

The present invention has been devised in view of the above-mentioned shortcomings. Even in a test window composed only of a start and an end, the test window area is created again to distinguish the part to be tested and the part not to be able to output an accurate CRC value. There is a purpose.

Hereinafter, an embodiment of the present invention for achieving the above object will be described in detail with reference to the accompanying drawings.

First, Fig. 3 shows the block diagram of the in-circuit tester using the gray code of the present invention. The basic configuration is as shown in Fig. 1, but the signal line is transferred from the CPU 1 to the start and end control circuit 5. A clock signal line is added from the clock generator circuit 2 to the function generator circuit 4, and a clear, To ^* , Listen signal line is added between the function generator circuit 4 and the start and end control circuits 5; Is different.

4 is a block diagram showing an embodiment of the start and end control circuit 5 of the present invention, and includes a start latch 12, an end latch 13, which receive data of respective control signals from the CPU 1, and latch data. Start comparator and latch 16, end comparator and latch for comparing the first window latch 14 and the second window latch 15 with the data stored in the respective latches 12-15 and the gray code at the start of the test. (17), a first window comparator and latch 18, a second window comparator and latch 19, and a first delay for a predetermined time delay of the outputs of the start comparator and latch 16 and the end comparator and latch 17; And the first and second tee flip-flops 22 and 23 which toggle and output the outputs of the second tee-flop flops 20 and 21 and the first and second window comparators and the latches 18 and 19. ), A NAND gate 24 for logically negating the output of the AND comparator and latch 17 and the second de-flip flop 21, and the first and second de-flops. Flop and the first and second D-flip-flop is configured hayeoseo including the AND gate 25 is a logical product of the output of the (20-23).

Referring to the present invention configured as described above with reference to the timing chart shown in FIG.

The CPU 1 uses the control signals S, E, W ₁ , and W ₂ before starting the test, the start latch 12, the end latch 13, the first window latch 14, and the second window latch. Each bit of data is latched into (15).

This 4-bit data is latched because the gray code comes out as 4 bits, and the types of functions are 16 signals from F ₁ to F ₁₆ .

For example, if the start is to be performed at F ₁ , 0001 data is latched to the start latch 12, and if the data is to be completed at F ₅ , the 0202 data is latched to the end latch 13.

Here, the first window latch 14 is for resetting the desired window in the middle of the start and end, and the second window latch 15 is for generating the window 2.

In addition, the data stored in each latch 12-15 is compared and latched in the gray code, comparator and latch 16-19, which occur at the beginning of the test, and if the start occurs from the beginning of F ₁ , as shown in FIG. Keep high from F ₁ . When the end signal is to be finished at the beginning of F, the AND signal is compared with the gray code value to generate an output (And ^* ) when the same, so that it remains low.

Here, the output signal TO ^* of the NAND gate 24 NANDs the output T of the AND comparator and the latch 17 and the output (AND) of the de-flip flop 21 to the function generating circuit 4. Output it. In addition, the first window comparator and the latch 18 and the second window comparator and the latch 19 are made in the first window latch 14 and the second window latch 15 to make the first and second windows, respectively. Compare the existing value with the gray code.

On the other hand, when the output signals of the de-flip flops 20 and 21 and the tee-flop flops 22 and 23 are ANDed through the AND gate 25, they are output as shown in the waveform of FIG. 5 during the test. It distinguishes between the area to be tested and the area not to be tested.

That is, the conventional test window has a constant shape indicating only the start and end of the test window as shown in FIG. 6A, and thus, when the IC to be tested has a pin OE that performs both input and output, the test output While the consistency of the test equipment could cause a fatal error in the repeatability of the test equipment, the present invention uses the additional components 14, 15, 18, 19, 22, 23, 24, and 25 in FIG. Even within a test window consisting only of start and end, you can create a test window area to distinguish between what you want to test and what you don't want to test.

At this time, the part to be tested and the part not to be tested are generated by the logical product (AND) of the first and second windows in FIG. 6, b, c, and d in the first window Win and the second window Win ₂ . Create a real test window (a window that identifies which parts of the test to test).

As described above, the present invention has modified the existing function in various ways to diversify the test pattern, and configures the control circuit in the test window circuit to prevent the CRC generation input circuit from entering the high impedance state of the measurement object. By doing so, it is possible to output only a constant value.

Claims (1)

The clock generation circuit 2 which generates a clock under the control of the CPU 1, the gray code generation circuit 3 which generates gray codes using the clock of the clock generation circuit as a reference clock, and the gray code And a start and end control circuit (5) for determining a test window of the function generating circuit and a function generating circuit (4) for making a function and sending it to a measurement object. A start latch 12, an end latch 13, a first window latch 14, a second window latch 15, and data and tests stored in the respective latches, which receive the respective control signals from the CPU and latch the data. Start comparator and latch 16, end comparator and latch 17, first and second window comparators and latches 18 and 19 for comparing the gray codes coming out at the beginning and the start comparator and latch and end comparator and latch Exodus De-flip flop (20) (21) for a predetermined time delay, and tee-flip flop (22) (23) for toggling the outputs of the first and second window comparators and latches (18) (19), And a NAND gate 24 for logically negating the output of the latch and the de-flop flop 21, and an AND gate 25 for logically multiplying the output of the flip-flop 20-23. Test window control circuit of an in-circuit tester using gray code.