JPH03242572A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To inspect functions of an LSI with minimum patterns by observing contents of a memory means from an external terminal of the LSI via an output means and comparing it with an expected value. CONSTITUTION:A mode switching terminal 106 is set inactive by an LSI tester, and a pattern for checking normal functions is applied to an LSI 101. When an output terminal 112 changes from LOW to HIGH at this time, this is detected by an inverter 103 and an AND gate 104 and input to a counter 105. Then the mode switching terminal 106 is set active. A lead signal 108 is made active by a mode control circuit 107, and contents of the counter 105 are read out to an internal bus 110. In addition a control signal 109 is also made active by the mode control circuit 107, and the contents of the counter 105 are output to therminals 113. An LSI tester samples the counter values output from the terminals 113 and compares them with an expected value.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to semiconductor integrated circuits.

[Conventional technology]

A conventional LSI testing method will be explained with reference to FIGS. 4 and 5. The functional operation testing method using an LSI tester is generally performed by sampling the output signal of the LSI at certain time intervals and comparing the sample data with a test pattern of expected values. FIG. 4 shows a case where the defect cannot be inspected even when a defect occurs in the LSI and an abnormality occurs in the output terminal. Fourth
In the figure, changes over time in the LSI output terminal are shown for two cases: normal operation and abnormal operation.

Assuming that this output terminal changes at a time interval TS during normal operation, the period of observation sample time set during testing by an LSI tester is also normally set to TS. However, at this time, if the signal waveform output from the LSI is an abnormal operation waveform as shown in Figure 4, each observation time (T
Since the observed values at I, T2, and T3 are in agreement with the expected values, the LSI tester concludes that this LSI is functionally normal.

Conventionally, this problem has been avoided by further shortening the observation sample time period of the LSI tester. FIG. 5 shows an example of a conventional countermeasure method. In FIG. 5, the observation sample period of the LSI tester is set to TS/2, which is half of the period in FIG. As a result, observation time T2. At T4, a discrepancy with each expected value can be detected.

[Problem to be solved by the invention]

However, if the observation sample period of the tester is shortened, many patterns for expected values are required.

For example, in the case of FIG. 5, the number of patterns of expected values is doubled because the sampling period is half that of the case of FIG.

In addition, when setting a smaller observation period to improve inspection accuracy, the number of patterns with expected values will increase accordingly, but in this case, depending on the LSI tester used for inspection, the number of patterns may exceed the allowable storage capacity of patterns. The disadvantage is that it may cause problems. Furthermore, even if the observation sample period can be made smaller, if the output of the LSI changes in a pulse-like manner with a width smaller than the set sample period, there is an essential drawback that failure phenomena may be overlooked and sufficient inspection cannot be performed. be.

[Means to solve the problem]

In the semiconductor integrated circuit of the present invention, a detection means for detecting a change in the output of the LSI, a storage means for storing information detected by the detection means, and a content of the storage means is stored in the LSI chip. and an output means for outputting to an external terminal of the LSI, and the LSI is inspected by observing the contents of the storage means from the external terminal of the LSI through the output means and comparing it with an expected value. .

〔Example〕

Next, the present invention will be explained with reference to the drawings.

In FIG. 1 showing the first embodiment of the present invention, 101 is an LSI, 102 is an output buffer, and 103 is an inverter (
INV), 104 is an AND gate (AND). 1
05 is an active signal (
This is a counter that counts up when the signal goes high.

A mode control circuit 107 generates a read signal 108 for outputting the contents of the counter 105 to the internal bus 110 when the mode switching terminal 106 is active, and a signal 109 for controlling the connection of the terminal.

112 is an output terminal to be inspected, and 114 is an output signal generation circuit. A terminal control circuit 111 outputs the value of the internal bus 110 to the terminal group 113 when the control signal 109 is active, and controls the terminal group 11B to perform the original operation of the LSI 101 when the control signal 109 is inactive.

Next, LSI10 when functionally inspected with an LSI tester.
I will explain the operation of I. First, the mode switching terminal 106 is made inactive by the LSI tester, and a pattern for normal function check is applied to the LSI I0I. At this time, when the output terminal 112 changes from LOW to HIGH, the rising change is detected by the inverter 103 and the AND gate 104, and LOW-HIGH→L
One shot of pulse that changes to O'iV is counted as counter 1.
, 05. Counter 105 receives pulse input and counts up. This counting operation is performed every time the output terminal 112 changes from LOW to HIGH. Therefore, when the pattern for confirming the normal function operation has finished flowing to the end, the counter 105 will have stored the number of times the output terminal 112 changed from LOW to HIGH during that time. Naturally, during this time, the expected value of the output terminal 112 is verified by the LSI tester at certain time intervals.

Next, the mode switching terminal 106 is activated.

Then, the mode control circuit 107 outputs the read signal 108.
becomes active, and the contents of counter 105 are read out to internal bus 110.

At the same time, the control signal 109 is also activated by the mode control circuit 107, and the internal bus 110 and terminal group 113
As a result, the contents of the counter 105 are directly output to the terminal group 113. Therefore, L.S.
The I tester samples the counter value output from the terminal group 113 and compares it with the expected value.
It is possible to finally decide whether or not I can function.

FIG. 2 shows the counter 10 depending on the signal change at the output terminal 112.
The operation of No. 5 is specifically shown using a timing chart. Here, the final expected value of the counter 105 during normal operation is N+1, while the counter value is N+3 during abnormal operation. Therefore,
Abnormal operation can be detected by comparing the counter values using the mode switching terminal 106.

Next, referring to FIG. 3 showing the second embodiment of the present invention, 306 is an AND gate (AND) operated by three people;
01 is in the driving state when the signal 302 is HIGH, and is L
This is an output buffer that becomes high impedance when it is OW. A mode control circuit 303 outputs a clock signal 304 and an output permission signal 305 to the parallel-serial converter 307, and outputs a signal 302 to the output buffer 301 and the AND gate 306. In addition, 307 is a parallel serial converter (hereinafter abbreviated as PS converter),
When a clock is supplied to the signal 304, the contents of the counter 105 are taken in and converted into serial data, and the serially converted data is output to the output terminal 112 when the output permission signal 305 is active.

Next, LSI30 when functionally inspected with an LSI tester.
The operation of No. 8 will be explained. First, the LSI tester makes the mode switching terminal 106 inactive and applies a normal function check pattern to the LSI 308.

When the switching terminal 106 is inactive, the mode control circuit 303 makes the signal 302 HIGH and the signal 304
．． 305 inactive. At this time, the output buffer 301 functions as a normal output buffer, and since the signal 305 is inactive, the PS converter 3
07 value is not output. Therefore, the normal value for the LSI 308 is output to the output terminal 112. Now, when the output terminal 112 changes from LOW to HIGH, the signal 302 is HIGH, so a change in the rising edge is detected by the inverter 103 and the AND gate 306, and the signal 1 changes from LOW-+HIGH to LOW.
The pulse of the shot is input to the counter 105. Counter 105 receives pulse input and counts up. This counting operation is performed when the output terminal 112 changes from LOW to HI.
It is done to change to GH. Therefore, when the pattern that affirms the normal function operation finishes flowing to the end, the counter 105 indicates that the output terminal 112 is LO.
The number of times the signal changes from W to HIGH is stored. Of course, during that time, the output terminal 11 is checked by the LSI tester.
2 expected value comparisons are performed at certain time intervals.

Next, when the mode switching terminal 106 is activated, the mode control circuit 303 first sets the signal 302 to LOW, so the output of the output buffer 301 becomes high impedance, the output of the AND gate 306 is always fixed to LOW, and the counter ], the operation of 05 stops thereafter. The mode control circuit 303 supplies a clock signal to the signal line 304 and causes the PS converter 307 to start a parallel-to-serial conversion operation. At this time, since the signal line 305 becomes active at the same time, the data of the counter 105 serially converted by the PS converter 307 is output from the output terminal 112. Therefore, the LSI tester can finally determine whether or not the LSI 308 is functional by sampling the value output from the terminal 112 and comparing it with the expected value.

〔Effect of the invention〕

As described above, according to the present invention, changes in the output are detected and stored inside the LSI chip, and the stored contents are transferred to the LSI through the terminal.
By having a reading means outside the SI chip, it is possible to conduct a functional test using an LSI tester without changing the observation sample time period of the LSI tester. The disadvantage of increasing the number of patterns is eliminated, and the essential disadvantage of overlooking defects such as pulse-like changes in the LSI output with a width smaller than the sample period is also eliminated.
It is possible to perform highly accurate functional testing of I.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing the first embodiment of the present invention, FIG. 2 is a timing chart explaining the operation of the first embodiment of the present invention, and FIG. 3 is a diagram showing the second embodiment of the present invention. The configuration diagrams shown in FIGS. 4 and 5 are timing charts for explaining the conventional example. 101...LSI, 102...Output buffer, 10
3...Inverter, 104...And gate, 10
5...Counter, 106...Mode switching terminal,
107...Mode control circuit, It)8...Read signal, 109...Control signal, 110...Internal lotus, 1
11...Terminal connection control circuit, 112...Output terminal,
113...Terminal group, 301...Output buffer, 30
2... Control signal, 30B... Mode control circuit, 30
4... Clock signal, 305... Output permission signal, 3
06...AND gate, 307...Parallel serial converter.

Claims (1)

[Claims] Inside the LSI chip, there is a detection means for detecting a change in the output of the LSI, a storage means for storing information detected by the detection means, and a storage means for storing the contents of the storage means into the LSI.
and an output means for outputting to an external terminal of the LSI, the content of the storage means is observed from the external terminal of the LSI through the output means, and compared with an expected value.
A semiconductor integrated circuit, characterized in that it performs an inspection of I.