JPS6429951A - Storage system - Google Patents

Storage system

Info

Publication number
JPS6429951A
JPS6429951A JP18525387A JP18525387A JPS6429951A JP S6429951 A JPS6429951 A JP S6429951A JP 18525387 A JP18525387 A JP 18525387A JP 18525387 A JP18525387 A JP 18525387A JP S6429951 A JPS6429951 A JP S6429951A
Authority
JP
Japan
Prior art keywords
signal
scu
memory device
same clock
attach
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18525387A
Other languages
Japanese (ja)
Inventor
Takashi Kumagai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP18525387A priority Critical patent/JPS6429951A/en
Publication of JPS6429951A publication Critical patent/JPS6429951A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enable fast access and to attach flexibility on the connection of memory devices whose operational specifications are different, by generating the control signal of the memory device in an MS and the set signal of data, etc., by using the same clock as that of an SCU, and sending them with a various kinds of phases and the number of cycles. CONSTITUTION:The same clock 5 is used commonly in a storage control unit (SCU) 3 and a main storage (MS) 4, and a signal which controls the memory device of the MS 4 or the signal to set the data, etc., are generated by using the clock 5, and also, a means 51 which varies each signal by information representing a machine cycle or the operation specification of the memory device is provided in the MS 4. The SCU 3 and the MS 4 use the same clock source 5, and since all of the signals 60-66 are generated by using the clock source 5, no circuit for synchronization between the SCU 3 and the MS 4 is required, and also, it is possible to output the signal by the cycle and the phase with an arbitrary number. In such a way, it is possible to make access to the MS at high speed, and also, the attach the flexibility on the connection of the memory devices with different operational specifications.
JP18525387A 1987-07-24 1987-07-24 Storage system Pending JPS6429951A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18525387A JPS6429951A (en) 1987-07-24 1987-07-24 Storage system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18525387A JPS6429951A (en) 1987-07-24 1987-07-24 Storage system

Publications (1)

Publication Number Publication Date
JPS6429951A true JPS6429951A (en) 1989-01-31

Family

ID=16167578

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18525387A Pending JPS6429951A (en) 1987-07-24 1987-07-24 Storage system

Country Status (1)

Country Link
JP (1) JPS6429951A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6182184B1 (en) 1990-04-18 2001-01-30 Rambus Inc. Method of operating a memory device having a variable data input length
US7138372B2 (en) 1997-03-14 2006-11-21 Daiichi Pharmaceutical Co., Ltd. Agent for preventing and/or treating cachexia

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6182184B1 (en) 1990-04-18 2001-01-30 Rambus Inc. Method of operating a memory device having a variable data input length
US6260097B1 (en) 1990-04-18 2001-07-10 Rambus Method and apparatus for controlling a synchronous memory device
US6266285B1 (en) 1990-04-18 2001-07-24 Rambus Inc. Method of operating a memory device having write latency
US6304937B1 (en) 1990-04-18 2001-10-16 Rambus Inc. Method of operation of a memory controller
US6314051B1 (en) 1990-04-18 2001-11-06 Rambus Inc. Memory device having write latency
US6584037B2 (en) 1990-04-18 2003-06-24 Rambus Inc Memory device which samples data after an amount of time transpires
US6697295B2 (en) 1990-04-18 2004-02-24 Rambus Inc. Memory device having a programmable register
US7138372B2 (en) 1997-03-14 2006-11-21 Daiichi Pharmaceutical Co., Ltd. Agent for preventing and/or treating cachexia

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