JPS6391578A - Test circuit - Google Patents

Abstract

PURPOSE:To enable the execution of a test at the maximum speed in such a manner that it is suited to an operation speed of IC, by a construction wherein a frequency multiplier circuit multiplying the frequency of a clock signal for the test is provided as a test circuit which is incorporated in IC. CONSTITUTION:In response to the input of a clock signal 101, the clock frequency of the clock signal 101 is multiplied to be double in a frequency multiplier circuit 1, and the signal is outputted therefrom and inputted to an inverter 3. When a gate switching signal 102 is at an H level, the clock signal 101 is selected as a clock output signal 104, and when the signal 102 is at an L level, a multiplied-frequency output signal 103 is supplied to an internal circuit of IC. The gate switching signal 102 is set at the H level in a non-test state, while it is set at the L level in a test state. Thereby it is possible to double a speed at the time of the test.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to test circuits, and more particularly to improvements in test circuits built into integrated circuits.

[Technique of promoting rice]

Conventionally, integrated circuits (integrated circuits)
The built-in test circuit (hereinafter referred to as IG) is used to test the clock signal supplied from an external source such as an IC tester, or the clock signal 11CIC output from the built-in clock oscillator. The maximum frequency value of the clock frequency is determined by the clock frequency of the 1c tester or the clock oscillator.

[Problem that the invention seeks to solve]

In the conventional test circuit described above, the test speed for the IC is uniquely determined by the frequency of the clock signal supplied from the industrial C tester or the frequency of the clock signal output from the clock excavator built into the IC. It is added. Therefore, even if the operating speed of the circuit function under test of the IC itself can quickly respond to the speed that corresponds to the frequency of the clock signal of the IC tester or built-in clock excavator, nil
The test speed for the IC reaches a peak due to the number of cycles of the clock (g), and the time required to test the IC is suppressed to a test speed that is less than the operation speed development capability of the IC, increasing several times to several tens of times. How long does it take?In short, you will notice the shortcomings.

[Friendly means of solving problems]

The test circuit of the present invention is a test circuit built into the IC, and is capable of controlling the frequency of a test clock signal supplied from the outside or the frequency of a test clock signal output from a clock oscillator built into the TC. It is configured with a frequency multiplier circuit that multiplies the frequency.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

1 and 2 are block diagrams of first and second embodiments of the present invention, respectively. As shown in FIG. 1, the first embodiment includes a frequency multiplier circuit 1, a NAND circuit 2, an inverter 3, and a second circuit 4. The embodiment includes a frequency multiplier circuit 6, a circuit 7, a D circuit 82 to NA, and a NOO circuit 10.
The construction 11, the inverters 12 and 13, the circuit 14, and the ANI) l! 2 circuits 15.

In response to the large power of the clock signal 101, the clock frequency of the clock signal 101 is doubled in the frequency multiplier circuit 1 and output, and is input to the inverter 3 as a frequency multiplied output signal 103. Ru. In the inverter 3, the frequency multiplied output signal 103 is inverted and output, and is input to the JR circuit 4.
A gate switching signal 102 is also input to the circuit 4,
A clock signal 101 and a gate switching signal 102 are input to the (JR ratio output NAND circuit 5 of both ministries. On the other hand, a clock signal 101 and a gate switching signal 102 are input to the NANI) circuit 2, and the NAND output thereof is input to the NANI) circuit 5. In the NAND circuit 5, the NAND output input from the NAND circuit 2,
Ol(.

A predetermined clock output signal 104 is output in response to the input (Jl(, output) from the circuit 4, and is supplied to the internal (low) path of the IC.

In this case, the level k (/llf NANL) of the gate switching signal 102 is the tarok output signal 10 output from the circuit 5.
4 is output after being switched to either the clock signal 101 itself or a tarok signal having a frequency twice the number of cycles tIiL of the clock signal 101. When the gate switching signal 102 is at the ")■# level, the clock signal 101 is selected and output as the clock output signal 104, and when the gate switching signal 102 is at the 1L" level, the clock signal 101 is determined by the output of the frequency multiplier circuit 1. The frequency multiplied output signal 103 is output as a test clock signal having twice the clock frequency.

FIGS. 2(al), (b), (C) and (d+) show examples of signal shaping of the above-mentioned clock signal 101, gate switching signal 102, frequency multiplied output signal 103 and clock output signal 104, respectively. be.

As described above, the gate switching signal 102 is set to the aH" level in the non-test state, and the gate switching signal 102i is set to the "L" level in the test state. The clock output signal 104 during the test is set to the clock The signal 1010 is supplied to the internal circuit of the IC as a test clock signal with a clock frequency twice as high as 1, making it possible to double the speed f: during testing.

Next, a second embodiment of the present invention will be described.

In the second embodiment shown in FIG. 3, frequency multiplier circuits 6L and 7, NANI) circuit 8,
(1 circuit 10 and 11, inverter 12 and 13
, an 0L circuit 14 , and an AND circuit 15 .

In FIG. 3, the frequency of the clock signal 105 is doubled in the frequency multiplier 6, outputted as a frequency multiplied output signal 108, and inputted to the frequency multiplier (9) path 7 and the inverter 13.

In the frequency multiplier circuit 7, the frequency multiplier output signal 10
8 is further doubled and output, and the frequency multiplied output signal 1
09 to (input to JR circuit 10.N(JR(
b) Road 10 work 11. Inverter 13 construction AND1
The gl path 15 forms a switching circuit that is controlled by the level of the gate switching signal 107 (7), and when the gate switching signal 107 is at the 1H'' level, the frequency multiplication circuit 108 outputs the output from the frequency multiplication circuit 6. When the clock signal corresponding to the frequency multiplication signal 109 outputted from the frequency multiplier circuit 7 is past and the n1 gate switching signal 107 is at the 1L'' level, the clock signal corresponding to the frequency Vμ multiplication signal 109 output from the frequency multiplier circuit 7 is selected and output from the circuit 11.

The clock signal output from the NO ordinary circuit 11 is input to the inverter 12, and the NAND AND circuit 9, the inverter 12, and the (Jkt circuit 14) receive the gate switching signal as in the first embodiment. A switching circuit is formed which is controlled by the level of the clock signal 106, and when the gate switching signal 106 is @H'' level, the clock signal 10
5 is selected and output from the NAND circuit 9, and when the gate switching signal 106 is at the "L" level, the doubled or quadrupled clock signal output from the NAND circuit 11 is selected. It is output from 9 NAND circuits.

Therefore, in the non-test state, the gate switching signal 10
The clock signal 105 is output to the AND circuit 9 through the gate 6 and sent to the internal circuit of the IC.In the test state, the clock signal 105 is outputted through the gate switching signal 106 to the AND circuit 9 and sent to the internal circuit of the IC. The output of the ANL circuit 9 is supplied to the internal circuit of the IC as a test clock signal. Until you say%h
The role of the gate switching signal 107 is to enable a double or quadruple test clock signal to be appropriately selected depending on the operating speed of the IC.

〔Effect of the invention〕

As explained above, since the present invention can be used for all tests of a clock signal obtained by multiplying the frequency of a predetermined reference clock signal, the operation of an IC can be tested at a frequency higher than the frequency of the reference clock signal. This makes it possible to perform tests at maximum speed in a manner that is compatible with the operating speed of the IC, and has the effect of significantly shortening the time required for IC testing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the first embodiment of the present invention, and the second embodiment (
a) , (C) , (C1$-engineering (d) is a signal cross diagram in 2 of the first embodiment, FIG. 3 is a prong diagram of the second embodiment of the present invention, Figure 4 fal, fbl
, (C), (di, (e) mustache) are
FIG. 6 is a signal waveform diagram in the second embodiment. In the figure, 1, 6.7... frequency multiplier circuit,
2゜5.8.9・・・Prospective circuit, 3,12.1
3. River... Inverter circuit, 4.14... (J
R circuit, 15...AND circuit. Agent Patent Attorney Uchihara 8 Focus) /II $ 2 Bacteria

Claims (1)

[Claims] A frequency multiplier circuit, which is a test circuit built into an integrated circuit, that multiplies the frequency of a test clock signal supplied from the outside or the frequency of a test clock signal output from a clock oscillator built into the integrated circuit. A test circuit comprising: