JPS61216047A - Scan logic circuit - Google Patents

Abstract

PURPOSE:To generate a pulse and to make the pulse to execute scan-in by suppressing a system clock inverted output with the aid of a scan clock. CONSTITUTION:The scan-in is executed in the normal procedure with respect to the preceding edge trigger-type FF 29, and data is set. An FF 37 is selected with an FF selecting signal 38 as a logic '1' with respect to the subsequent edge trigger-type ff 37, and a scan data 33 is selected by a scan data selecting circuit 39 with a scan enable signal 31 as the logic '1'. While the system clock 34 is set to a logic '0', namely the FF 37 is fixed to the logic '1', a scan clock 36 is given, whereby a system clock suppressing circuit 40 generates a pulse. Thus, the pulse is transmitted to the FF 37 through a clock driver 45, thereby setting the scan data 33.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a scan access method for logic circuits, and in particular, a diagnostic method for checking the direct current logic function of an LSA (Large Scale Integrated Circuit) from an LSQ terminal. The present invention relates to a scan logic circuit used in the method.

[Background of the Invention] Conventional scan logic is applicable only to a logic configuration in which data is transferred using system clocks 1 and 2, which have different phases and do not overlap, as shown in Figure 2. In a circuit with a logic configuration, when performing scan-in to the 7 flip-flop 3, the flip-flop selection signal 4 is set to logic "1" to select the flip-flop 3, and the scan enable signal 5 is set to logic "1" to select the scan data selection circuit 6. Scan data 7
After selecting and setting system clock 1 to logic 10',
When the scan clock 8 is given, the clock driver 13
A clock is transmitted to the flip-flop 3 through it, and data can be set there. The flip-flop 9 can also be scanned in using the same procedure.

However, by using edge-triggered flip-flops 14 and 15 shown in FIG.
In the logic that configures a master-slave format using the rising and falling edges of 6, if the system clock 16 is fixed at logic 0'i in the conventional scan-in procedure, the subsequent flip 70 block 15 , the scanner clock 17 is not transmitted and scan-in is not possible. Furthermore, in order to eliminate the influence on the rear stage 7c1 block 15 of the system clock 16, when the system clock 16 is changed from logic "0" to logic "1", the front stage flip-flop 14
will change. In this way, conventional scan logic uses edge-triggered flip-flops and uses the falling edges and falling edges of the same system clock to form a master-slave format.
Scan-in to the rear clip 70 tube could not be performed without affecting the 0 tube.

Regarding scan logic, see
-25287 publication is mentioned.

(Objective of the Invention) An object of the present invention is to solve the above-mentioned problems and to implement a master-slave format by using an edge-triggered 7-ring 7)a lag and using the same system clock rising and falling edges. The object of the present invention is to enable scan-in to the 7 lips and 70 blocks in the subsequent stage without affecting the 7 lips and 70 blocks in the preceding stage for the logic circuits that constitute the logic circuit.

(Summary of the Invention) According to the present invention, since the inverted output of the system clock is given to the clock terminal of an edge-triggered flip-flop, the clock input terminal of the flip-flop becomes a logic "1" state, making scan-in impossible. By suppressing the system clock inverted output with a scan clock for a group of flip-flops, a pulse is generated, and the pulse enables scan-in, thereby achieving the object. Embodiment] Hereinafter, an embodiment of the present invention will be described with reference to FIG. 1. In FIG. 1, conventional procedure I trowel scan-in is performed for the edge trigger type flip-flop 29 at the front stage. That is, The flip-flop selection signal 50 is set to logic ``1''.
The edge trigger type flip 70 tube 29 is selected as ', the scan enable signal 31 is set to logic '1', the scan data selection circuit 52 selects the scan data 35, and the system clock 34 is fixed to logic '0'. When the clock 66 is applied, the clock is transmitted to the edge trigger type 7 rig 70 tube 29 through the clock driver 35, and data can be set. On the other hand, for the subsequent edge trigger type flip-flop 37, the edge trigger type flip-flop 57 is selected by setting the free lag flop selection signal 68 to logic 1', and the scan data selection circuit 39 sets the scan enable signal 31 to logic 11'. , by selecting the scan data 36 and applying the scan clock 36 while keeping the system clock 34 at logic ``0'', that is, by fixing the scan clock 36 to the edge-triggered flip 70 tube 37 and fixing it to logic ``1''. The scan data 63 can be set by causing the system clock inhibit circuit 40 to generate a pulse and transmitting the pulse to the edge trigger type 7 rig 70 tube 37 through the clock driver 45.

According to this embodiment, the front edge trigger type flip 70
Edge trigger type 7 lip 7 in the latter stage without affecting the knob.
This has the effect of making it possible to scan in for 0 points.

〔Effect of the invention〕

According to the present invention, for a logic circuit that configures a master-slave format by using the rising edge and falling edge of one system clock using edge-triggered flip-flops that could not be scanned in in the conventional method, By suppressing the system clock with the scan clock and generating pulses, there is an effect that scan-in can be carried out for the subsequent slip 70 without affecting the preceding slip 70.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a logic block diagram that can be scanned in using conventional scan logic, and Fig. 3 is a block diagram of a logic that can be scanned in using conventional scan logic. FIG. 2 is a block diagram when applied to logic constituting a master-slave format using the rising edge and falling edge of a clock as trigger inputs; FIG. DESCRIPTION OF SYMBOLS 1... System clock, 2... System clock, 3... 7 lips, 8... Scan clock signal, 9... Flip-flop, 10... Combinational logic circuit, 11... Scan data selection circuit,
16... System clock signal, 17... Scan clock signal, 18... Scan enable signal, 1
9... Scan-in data, 20... Scan data selection circuit, 21... Combinational logic circuit, 22...
Scan data selection circuit, 25... Inverter, 27
...Clock driver, 2 days...Clock driver, 29...Edge trigger type 7 lip 70 knobs, 42...
・Inverter, 45...NAND gate, 4
4...AND gate, 45...Clock driver. Figure 1

Claims (1)

[Claims] 1. An edge-triggered flip-flop is used for the internal logic, and the rising edge and falling edge of one system clock are used as trigger inputs. In the logic circuit that configures the master-slave format, the terminals used during scanning and the normal a selection circuit for switching between data and scan data;
A scan logic circuit comprising a driver circuit for applying a clock to an edge-triggered flip-flop, and a suppression circuit for suppressing the influence of a system clock on the subsequent edge-triggered flip-flop during scanning.