JP3085322B2 - Sampling clock supply device for digital / analog mixed LSI test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sampling clock supply apparatus for a digital / analog mixed LSI test apparatus, and more particularly, to operate a plurality of arbitrary waveform generators and a plurality of waveform digitizers with asynchronous sampling clocks. Start of sampling clock supply device for digital / analog mixed LSI test equipment
The present invention relates to a sampling clock supply device that controls timing or trigger timing with good reproducibility.

[0002]

2. Description of the Related Art A conventional example of a sampling clock supply apparatus for a digital / analog mixed LSI test apparatus will be described with reference to FIG. In FIG. 1, T is a digital / analog mixed LSI test apparatus, which includes a plurality of arbitrary waveform generators 7, 8 and a plurality of waveform digitizers 9, 10. C is a sampling clock supply device, which includes an original pulse oscillator 1 and its dividers 3 and 4, and an original pulse oscillator 2 and its dividers 5 and 6. The arbitrary waveform generator 7 is connected to the original pulse oscillator 1 via the frequency divider 3, the arbitrary waveform generator 2 is connected to the original pulse oscillator 1 via the frequency divider 4, and the waveform digitizer 9 is divided. The waveform digitizer 10 is connected to the original pulse oscillator 2 via a frequency divider 6 and a frequency digitizer 6. A plurality of arbitrary waveform generators 7, 8
As described above, the divided sampling clocks are supplied to the plurality of waveform digitizers 9 and 10, respectively.

Here, referring to FIG. 2A, the problem is that when the waveform digitizer 1 receives a trigger pulse, the waveform digitizer 9 outputs a sampling clock * 1.
It is not clear whether to start with the sampling clock * 2 or start with the sampling clock * 2. As a result, the start timing is indefinite for one clock. Figure 2 with large sampling clock frequency
In the case of (a), the time difference for one clock is small and the problem is small, but in the case of FIG. 2B where the sampling clock frequency is smaller, the time difference for one clock becomes large and is ignored. I can't. In other words, the reproducibility of the measured data is degraded due to the fact that the waveform digitizer supplied with the sampling clock having a small clock frequency has a large error in the start timing.

[0004]

SUMMARY OF THE INVENTION An object of the present invention is to provide a sampling clock supply apparatus for a digital / analog mixed LSI test apparatus which solves the above-mentioned problems.

[0005]

In a sampling clock supply apparatus for a digital / analog mixed LSI test apparatus, a clock in which an original oscillation pulse is supplied from an original pulse oscillator to each of a plurality of arbitrary waveform generators and a plurality of waveform digitizers. A clock unit comprising: a start controller for gating an original oscillation pulse supplied from an original pulse oscillator by a trigger signal; and a frequency divider for dividing an output of the start controller to a required sampling clock. And

[0006]

An embodiment of the present invention will be described with reference to FIG. FIG. 3A is a diagram showing an outline of a sampling clock supply device of a digital / analog mixed LSI test device according to the present invention, wherein a plurality of arbitrary waveform generators W and a plurality of waveform digitizers D are respectively provided with an original pulse oscillator G.
And a clock section C to which the original oscillation pulse P is supplied.

FIG. 3B is a diagram showing the configuration of each clock section C. The start controller 11 gates the original oscillation pulse P supplied from the original pulse oscillator G by a trigger signal and the output of the start controller 11. And a frequency divider 12 which divides the frequency into a necessary sampling clock. The step-down rate of these frequency dividers 12 is set to a predetermined value corresponding to each arbitrary waveform generator W and waveform digitizer D.

FIG. 3 (c) is a timing chart when the arbitrary waveform generator W and the waveform digitizer D are started, and FIG. 3 (d) is a partially enlarged view. That is, the original oscillation pulse P supplied to the start controller 11 is gated by the trigger signal here, and is output to the frequency divider 12. The above is a description of the case where the clock section C is provided in each of the arbitrary waveform generators W and the waveform digitizers D. As shown in FIG. 4, each clock section C is used as a clock source unit in one place. You can also concentrate on

[0009]

The start of the output to the frequency divider 12 means the start of each of the arbitrary waveform generators W and the digitizer D. This start also starts with the sampling clock * 1 as in the prior art. There is a trigger error of starting with the sampling clock * 2. However, this trigger error is equivalent to one period of the always constant original oscillation pulse P irrespective of the sampling clock for each of the arbitrary waveform generator W and the waveform digitizer D. It is a short time. The effect on the reproducibility of the measurement data due to the trigger error in a very short time is hardly considered.

[Brief description of the drawings]

FIG. 1 is a diagram showing a conventional example of a sampling clock supply device of a digital / analog mixed LSI test device.

FIG. 2 is a timing chart when starting an arbitrary waveform generator and a waveform digitizer, where (a) is a diagram showing a case where a sampling clock frequency is large;
(B) is a diagram showing a case where the sampling clock frequency is small.

FIG. 3 shows a digital / analog mixed LS according to the present invention.
FIGS. 2A and 2B are diagrams illustrating a sampling clock supply device of an I test apparatus, in which FIG. 1A is a diagram illustrating the outline thereof, FIG. 2B is a diagram illustrating the configuration of each clock unit, and FIG. Timing when starting
The chart, (d) is a partially enlarged view thereof.

FIG. 4 is a diagram showing another embodiment of the present invention.

[Explanation of symbols]

 W Arbitrary waveform generator D Waveform digitizer G Original pulse oscillator C Clock section P Original oscillation pulse 11 Start controller 12 Divider

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Claims (1)

(57) [Claims] 1. A plurality of arbitrary waveform generators and a plurality of waveform digitizers each having a clock section to which an original oscillation pulse is supplied from an original pulse oscillator, wherein the clock section outputs the original oscillation pulse supplied from the original pulse oscillator. A sampling clock supply for a digital / analog mixed LSI test apparatus, comprising: a start controller that gates by a trigger signal; and a frequency divider that divides the output of the start controller to a required sampling clock. apparatus.