JPH0410097B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Technical Field of the Invention The present invention provides a manual clock control system, particularly when it is necessary to use 60 ns, 90 ns, 120 ns, and 360 ns clocks in a system. In a data processing device capable of generating each of the above types of clocks using a 30ns original clock oscillator corresponding to The present invention relates to a manual clock control system that allows operation in a manual clock operating mode.

(B) Technical background and problems In data processing systems, for example, 60 ns and
Since 90ns, 120ns, and 360ns clocks may be required, a 30ns original clock oscillator is used. For example, the central processing unit operates in one machine cycle synchronized with a 120 ns clock obtained by dividing the 30 ns original clock. However, within the central processing unit, there are components that operate by distinguishing between the first half and the second half of one machine cycle, and when testing a device in manual clock operation mode, the first half It is necessary to generate a manual clock to distinguish between the first and second half sections. That is, when diagnosing the operation of the central processing unit, instead of using a normal clock, one clock is manually applied, the state inside the central processing unit is collected, and then one clock is applied again. By applying a starting clock and collecting the state within the central processing unit at that time, changes in the state are investigated. In the manual clock operation mode where operations are performed using this manual clock, the state can normally be collected for each machine cycle, but within the central processing unit, the state in the first half of one machine cycle is collected. There are components that need to be collected separately from the state in the latter half. In such a case, when giving a manual clock, keep in mind when giving a manual clock corresponding to the first half section and when giving a manual clock corresponding to the second half section.・It is necessary to give a clock.

(C) Object and Structure of the Invention The purpose of the present invention is to solve the above-mentioned problems, and the manual clock control method of the present invention has the following features:
The manual clock is configured to have at least a basic clock and a clock with twice the frequency of the basic clock in one machine cycle, and is provided with an oscillator that emits one-fourth of the cycle of one machine cycle as the original clock oscillator. - In a data processing device that is configured to selectively output one of the two types of clocks in the clock operation mode, the one machine cycle is divided into two phase intervals, and each phase is divided into two phases. An interval indication signal generation unit that generates an interval indication signal indicating an interval, and a previous clock phase that maintains at least in which of the two phase intervals the most recently issued clock was issued under the manual clock operation mode. a holding section and a manual clock operation start circuit section, and when an instruction is given by the manual clock operation start circuit section, one of the section instruction signals is set based on the contents of the previous clock phase holding section. The present invention is characterized in that one of the two types of clocks having different phases is generated by a signal obtained by dividing the frequency of the output of the original clock oscillator. Examples will be described below with reference to the drawings.

(D) Embodiment of the Invention FIG. 1 shows the main structure of an embodiment of the invention, and FIG. 2 shows its time chart. Note that the illustrated case corresponds to p=2 in the present application.

In FIG. 1, 1 is an original clock oscillator, 2 is an interval instruction signal generation section, 3 is a previous clock phase holding section, 4 is a manual clock operation start circuit section, 5 is a manual clock generation section, 6 to 1
0 is JK flip flop, 11 or 1 respectively
6 represents an AND circuit, and 17 represents an OR circuit.

The original clock oscillator 1 has the form shown in Fig. 2.
Generates an original clock with a period of 30ns. In the section instruction signal generation section 2, the flip-flop 6
The frequency of the original clock is divided by 1/2 to obtain the signal T ₀ , and the frequency of the signal T ₀ is further divided by 1/2 to obtain the signal T ₁
I am getting . The signal T ₁ and signal ₁ are 120ns
This signal has a period of , and indicates the first half section and the second half section of one machine cycle.

Figure 2 Illustrated signals HFCLO, HFCLM, TOS,
The TIS solid line indicates that the most recently issued clock is one machine clock under manual clock operation mode.
The operation is shown in a warm state in the latter half of the cycle. That is, in this case, the signal SiNGLE CLOCK which gives the manual clock operation start
Before START is issued, the flip
Flop 8 forces signal HFGLO to logic "0".

In this state, the signal SiNGLE CLOCK START
When is set to logic “1” for 120ns each time,
Since the manual clock operation start circuit section 4 receives a 30 ns clock from the AND circuit 11 shown in FIG. 1, it outputs, so to speak, four original clocks. At this time, since the signal is logic "1" and the AND circuit 13 is operating in response to the signal ₁ , the flip-flop 10 issues the signal TOS with a period of 60 ns as shown by the solid line in the figure. As a result, the flip-flop 9 also operates and generates the signal TIS as shown by the solid line in the figure. Then, the AND circuit 15 is turned on in response to the signal _T0 , and the flip-flop 8 is set. That is, the signal HFCLO is set to logic "1". By the above operation, one signal SiNGLE CLOCK
Corresponding to START, one signal TOS is output corresponding to the first half of one machine cycle, that is, the first manual clock signal is
If it was applied during the latter half of the machine cycle, the signal TOS is used as a clock for one machine under the current manual clock mode.
It will be given corresponding to the first half of the cycle.

Under the condition that the signal HFCLO is logic "1", the signal is turned off again for manual clock operation.
Assume that one SiNGLE CLOCK START is output. That is, if the previously issued manual clock was applied in the first half of one machine cycle, the signal SINGLE CLOCK
Assume that one START is output. In this case, in the manual clock generator 5, the AND circuit 12 operates in response to the signal _T1 , and the signal TOS is generated at the timing indicated by the dotted line in FIG. This inverts the signal TIS and then forces the signal HFCLO to a logic "0". That is, in response to one signal SiNGLE CLOCK, START,
Corresponding to the latter half of one machine cycle, the signal
One TOS is output.

Note that in order to obtain a signal with an arbitrary pulse width from the signal TOS, it is sufficient to insert a monostable circuit as necessary.

(E) Effects of the Invention As explained above, according to the present invention, under the manual clock operation mode, for example, the original
Along with the 120 ns clock, it is possible to generate clocks corresponding to the first and second half sections of one machine cycle.

[Brief explanation of drawings]

FIG. 1 shows the main structure of an embodiment of the present invention, and FIG. 2 shows its time chart. In the figure, 1 is an original clock oscillator, 2 is a section instruction signal generating section, 3 is a previous clock phase holding section, 4 is a manual clock operation start circuit section, and 5 is a manual clock generating section.

Claims (1)

[Claims] 1. An oscillator configured to have at least a basic clock and a clock with twice the frequency of the basic clock in one machine cycle, and which emits a cycle of 1/4 of the above-mentioned one machine cycle as the original clock oscillator, In a data processing device configured to selectively output one of the two types of clocks under the manual clock operation mode, the one machine cycle is divided into two phase intervals and each an interval indication signal generation unit that generates an interval indication signal indicating a phase interval; and a pre-clock that maintains at least in which of the two phase intervals the most recently issued clock was issued under the manual clock operation mode. A phase holding section and a manual clock operation start circuit section are provided, and when an instruction is given by the manual clock operation start circuit section, the period instruction signal is controlled based on the contents of the previous clock phase holding section. 1. A manual clock control system, characterized in that one of the two types of clocks having different phases is generated by one clock oscillator and a signal obtained by frequency-dividing the output of the original clock oscillator.