JP2008286660A - Semiconductor testing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor testing device capable of dispensing with use of an expensive transmission cable for a high-frequency characteristic and prevention of a mixed noise, when distributing a clock from a clock board. <P>SOLUTION: The clock board 21 is provided with a system clock generating part 10 for generating a system clock used in the whole system, using an oscillation output from a clock origin oscillator 5 as a reference, dedicated boards 12, 13 are provided respectively with PLL frequency synthesizers 63, 64 for generating a clock signal having a frequency higher than that of the system clock output from the system clock generating part 10, and input sampling clocks based on the clock signal into dedicated circuits 8, 9. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor test apparatus, and more particularly to sampling clock supply in a mixed digital / analog semiconductor test apparatus.

  In the conventional digital / analog mixed semiconductor test apparatus, an independent clock board generates a clock by a PLL frequency synthesizer based on the clock source oscillator, and the clock is generated by an arbitrary number of AWG (arbitrary waveform generation function) boards, DTZ. (Waveform digitizer function) The data is transmitted to the board and divided as necessary to generate a sampling clock for the arbitrary waveform generator and the waveform digitizer.

FIG. 3 is a block diagram showing the configuration of a sampling clock supply means of a conventional digital / analog mixed semiconductor test apparatus in which the output of one PLL frequency synthesizer is shared by both AWG and DTZ boards. In the clock board 1, the oscillation signal output from the clock source oscillator 5 is input to the PLL frequency synthesizer 6, and a clock signal based on the oscillation signal is output from the PLL frequency synthesizer 6. The clock signal output from the PLL frequency synthesizer 6 is sent to the AWG board 2 and the DTZ board 3 via the clock transmission path 4. The clock signal sent to the AWG board 2 is frequency-divided by the frequency divider 71 and becomes the sampling clock of the arbitrary waveform generator 8. The clock signal sent to the DTZ board 3 is frequency-divided by the frequency divider 72 and becomes a sampling clock of the waveform digitizer unit 9.

FIG. 4 is a block diagram showing the configuration of a sampling clock supply means of a conventional digital / analog mixed semiconductor test apparatus having an independent PLL frequency synthesizer on the clock board for each AWG board and DTZ board. In the clock board 11, the oscillation signal output from the clock source oscillator 5 is input to the PLL frequency synthesizers 61 and 62, and a clock signal based on the oscillation signal is output from each of them. These clock signals are sent to the AWG board 2 and the DTZ board 3 through the clock transmission paths 41 and 42, respectively. The subsequent steps are the same as in FIG.

3 and 4, the frequency divider is arranged on the AWG board side and the DTZ board side, but may be arranged on the clock board side.

  Prior art documents related to sampling clock supply for semiconductor test equipment include the following.

Japanese Patent Laid-Open No. 5-142302

  In the prior art, since the PLL frequency synthesizer is shared by a plurality of AWG boards and DTZ boards, there is an advantage that the number of PLL frequency synthesizers can be minimized, but there are the following problems.

That is, each AWG and DTZ board has a configuration having only a frequency divider for supplying a sampling clock, and therefore, it is necessary to generate the highest frequency that can be used in the clock board. It becomes necessary to transmit a high-frequency clock to the AWG and DTZ boards. For this reason, it is necessary to sufficiently increase the frequency characteristics of the transmission path, and when the transmission distance from the clock board to the AWG / DTZ board is long, accurate transmission may be difficult. In addition, it is necessary to use an expensive transmission cable excellent in high-frequency characteristics, and there is a problem that costs increase.

In addition, noise may be mixed in the process in which the clock generated by the clock board is transmitted to the AWG and DTZ boards. Therefore, it is necessary to use an expensive transmission cable with good shielding characteristics in order to prevent noise mixing.

  The present invention is intended to solve such problems, and provides a semiconductor test apparatus that does not require the use of an expensive transmission cable in order to prevent high-frequency characteristics and noise mixing in clock distribution from a clock board. Objective.

In order to achieve such a problem, the invention according to claim 1 of the present invention is:
In a semiconductor test apparatus that provides a sampling clock based on a clock signal generated by a PLL frequency synthesizer to a dedicated circuit on a dedicated board based on an oscillation output from a clock source oscillator on the clock board,
The clock board includes a system clock generator that generates a system clock based on an oscillation output from the clock source oscillator,
The dedicated board includes the PLL frequency synthesizer that generates a clock signal having a frequency higher than the system clock, and supplies a sampling clock based on the clock signal to the dedicated circuit.

The invention according to claim 2
The semiconductor test apparatus according to claim 1,
As the dedicated circuit, an arbitrary waveform generating unit and a digitizer unit are provided on the corresponding dedicated boards, respectively.

The invention described in claim 3
The semiconductor test apparatus according to claim 1,
As the dedicated circuit, an arbitrary waveform generating unit and a digitizer unit are provided on the same dedicated board.

The invention according to claim 4
The semiconductor test apparatus according to any one of claims 1 to 3,
The dedicated board includes a frequency divider that divides a clock signal output from a PLL frequency synthesizer in the previous period and outputs a sampling clock to the dedicated circuit.

  As is apparent from the above description, according to the present invention, the sampling clock based on the clock signal generated by the PLL frequency synthesizer based on the oscillation output from the clock source oscillator on the clock board is dedicated on the dedicated board. In the semiconductor test apparatus applied to the circuit, the clock board includes a system clock generation unit that generates a system clock based on an oscillation output from the clock source oscillator, and the dedicated board has a clock having a frequency higher than the system clock. The PLL frequency synthesizer for generating a signal is provided, and by supplying a sampling clock based on the clock signal to the dedicated circuit, an expensive transmission cable can be used to prevent high frequency characteristics and noise mixing in clock distribution from the clock board. use It is possible to provide a semiconductor testing device is not needed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a configuration block diagram showing an example of sampling clock supply means of the semiconductor test apparatus according to the embodiment of the present invention.

In the clock board 21, the clock source oscillator 5 outputs an oscillation signal as a reference, and the system clock generator 10 generates a system clock used in the entire system based on this. The system clock output from the system clock generator 10 is sent from the clock board 21 to the plurality of AWG boards 12 and the DTZ board 13 via the clock transmission path 43.

The PLL frequency synthesizer 63 receives the system clock sent to the AWG board 12 and outputs a clock signal based on the system clock. The frequency divider 71 divides the clock signal output from the PLL frequency synthesizer 63 and outputs a sampling clock to the arbitrary waveform generator 8.

The PLL frequency synthesizer 64 receives the system clock sent to the DTZ board 13 and outputs a clock signal based on the system clock. The frequency divider 72 divides the clock signal output from the PLL frequency synthesizer 64 and outputs a sampling clock to the waveform digitizer unit 9.

In the above description, the AWG board 12 and the DTZ board 13 each constitute a dedicated board, and the arbitrary waveform generator 8 and the digitizer section 9 each constitute a dedicated circuit on the dedicated board.

The operation of the apparatus of FIG. 1 will be described below. In the clock board 21, an oscillation signal is output from the clock source oscillator 5, and a system clock used in the entire system is output from the system clock generation unit 10 based on the oscillation signal. This system clock is sent to a plurality of AWG boards 12 and DTZ boards 13 via a clock transmission path 43.

The AWG board 12 outputs a clock signal having a frequency higher than the system clock from the PLL frequency synthesizer 63 with the system clock as a reference. This clock signal is frequency-divided, and a sampling clock is output from the frequency divider 71 to the arbitrary waveform generator 8.

In the DTZ board 13, a clock signal having a frequency higher than the system clock is output from the PLL frequency synthesizer 64 with the system clock as a reference. This clock signal is frequency-divided, and a sampling clock is output from the frequency divider 72 to the waveform digitizer unit 9.

According to the semiconductor test apparatus configured as described above, by mounting the PLL frequency synthesizer on the AWG board or DTZ board, the clock frequency can be converted to a high frequency inside the AWG and DTZ boards. The frequency of the clock transmitted from the clock board can be set to a frequency lower than the frequency of the sampling clock to be used. As a result, it is not necessary to use a high-performance cable for the transmission path.

Further, when the transmission line is long, the amount of attenuation of the clock signal due to the restriction of the frequency characteristic of the transmission line can be reduced.

Furthermore, the noise removal function by the PLL circuit of the PLL frequency synthesizer unit can remove or reduce noise mixed in the transmission line without using an expensive transmission cable or the like that is particularly excellent in shielding characteristics.

In addition, since the PLL frequency synthesizer is individually provided, the characteristics of the clock signal can be optimized according to the characteristics of the arbitrary waveform generator 8 and the digitizer 9.

FIG. 2 is a block diagram showing a second example of the sampling clock supply means of the semiconductor test apparatus according to the embodiment of the present invention, in which the functions of the arbitrary waveform generation and the digitizer are combined into one board. is there. The same parts as those in FIG. 1 are denoted by the same symbols, and redundant description is omitted.

The system clock output from the system clock generator 10 of the clock board 21 is sent to the plurality of AWGDTZ boards 14 via the clock transmission path 44.

The PLL frequency synthesizers 63 and 64 receive the system clock sent to the AWGDTZ board 14 and output clock signals based on the system clock. The frequency dividers 71 and 72 divide the clock signals output from the PLL frequency synthesizers 63 and 64, respectively, and output the sampling clocks of the arbitrary waveform generator 8 and the waveform digitizer 9, respectively.

In the above description, the AWGDTZ board 14 constitutes a dedicated board, and the arbitrary waveform generator 8 and the digitizer section 9 constitute a dedicated circuit on the dedicated board.

According to the semiconductor test apparatus configured as described above, the same effects as those of the apparatus of FIG. 1 are produced.

  In each of the above embodiments, the frequency divider is used to generate the sampling clock. However, the output of the PLL frequency synthesizer is directly used as the sampling clock of the arbitrary waveform generator 8 and the digitizer 9 without using the frequency divider. It is good.

1 is a configuration block diagram showing an example of a semiconductor test apparatus according to an embodiment of the present invention. It is a block diagram which shows the 2nd Example of the semiconductor test apparatus which concerns on embodiment of this invention. It is a block diagram showing a conventional example of a semiconductor test apparatus. It is a block diagram which shows the 2nd prior art example of a semiconductor test apparatus.

Explanation of symbols

5 Clock original oscillators 8 and 9 Dedicated circuit 10 System clock generators 12, 13, and 14 Dedicated board 21 Clock boards 63 and 64 PLL frequency synthesizer

Claims (4)

In a semiconductor test apparatus that provides a sampling clock based on a clock signal generated by a PLL frequency synthesizer to a dedicated circuit on a dedicated board based on an oscillation output from a clock source oscillator on the clock board,
The clock board includes a system clock generator that generates a system clock based on an oscillation output from the clock source oscillator,
The dedicated board includes the PLL frequency synthesizer that generates a clock signal having a frequency higher than the system clock, and supplies a sampling clock based on the clock signal to the dedicated circuit. 2. The semiconductor test apparatus according to claim 1, wherein an arbitrary waveform generation unit and a digitizer unit are provided on the corresponding dedicated boards as the dedicated circuit. 2. The semiconductor test apparatus according to claim 1, wherein an arbitrary waveform generator and a digitizer are provided on the same dedicated board as the dedicated circuit. 4. The dedicated board includes a frequency divider that divides a clock signal output from a previous PLL frequency synthesizer and outputs a sampling clock to the dedicated circuit. The semiconductor test apparatus described in 1.

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