JP5806200B2 - Pseudo random bit string generator - Google Patents

Description

  The present invention relates to a pseudo-random bit string generator capable of operating at high speed, which is used for a test signal source for a digital integrated circuit or analog integrated circuit operating at high speed.

  Pseudo random bit sequence generators (Pseudo Random Bit Sequence Generators, hereinafter abbreviated as PRBS generators) are widely used as test signal sources for various digital circuits and analog circuits. The PRBS generator is composed of a feedback loop including a shift register. The length and pattern of the bit string are determined by the number of shift registers, the number of taps, and the tap extraction position. In many cases, the number of taps is two, and an exclusive OR (hereinafter referred to as XOR) of a plurality of signals extracted from the taps is taken, and the output of the XOR is returned to the top entry of the shift register. Thus, a feedback loop is configured.

Figure 26 is conventional bit Retsucho 2 ⁹ -1 PRBS generator (hereinafter, 2 ⁹ -1 PRBS generator and substantially) is a block diagram showing the configuration of a. The conventional 2 ⁹ -1 PRBS generator is a shift register consisting of nine delay flip-flops (hereinafter referred to as DFF) 100-1 to 100-9 and one XOR circuit 101. It consists of two feedback loops. In FIG. 26, reference numeral 102 denotes a clock buffer that supplies a clock signal CK to the DFFs 100-1 to 100-9, and reference numeral 103 denotes an output buffer that takes out the output of the DFF 100-1 as the output of the 2 ⁹ -1 PRBS generator.

  Each bit sequentially moves between nine DFFs 100-1 to 100-9 driven by a clock signal CK having a frequency of F1 and a period of T1 (T1 = 1 / F1). A total delay time of 9 × T1 is given for the DFFs 100-1 to 100-9. A bit existing in the DFF 100-5 is given to the XOR circuit 101 as one input of the XOR circuit 101. The bit existing in the DFF 100-9 is given to the XOR circuit 101 as another input of the XOR circuit 101. Here, the bits existing in the DFF 100-9 are the same as the bits existing in the DFF 100-5 at a time point four cycles before, that is, by a time of 4 × T1.

FIG. 27 shows a timing chart of the outputs of all nine DFFs 100-1 to 100-9, and FIG. 28 shows a signal data string output from the nine DFFs 100-1 to 100-9. In FIG. 27, bit A _X is equal to the result of exclusive OR of bit A _X-9 and bit A _X-5 (X is an arbitrary value). The vertical axis in FIG. 28 is voltage. FIG. 28 shows that a bit string having a bit string length of 2 ⁹ −1 = 511 bits is repeatedly output.

Non-Patent Document 1 describes a circuit configuration almost identical to that of the conventional 2 ⁹ -1 PRBS generator shown in FIG.
Conventional PRBS generator bit Retsucho 2 ^N -1 29 (hereinafter, 2 ^N -1 PRBS generator and substantially) shows the configuration of a. Here, N is an integer of 3 or more. In the 2 ^N −1 PRBS generator, ^N DFFs 100-1, 100-2,..., 100-N and one XOR circuit 101 constitute a feedback loop. The XOR circuit 101 takes out the output of the DFF 100-N and the outputs of one to three other DFFs as inputs, and returns the output to the input of the DFF 100-1. Table 1 summarizes the DFF numbers that the XOR circuit 101 takes out as tap1 to tap4.

  Table 1 is based on what is described in Non-Patent Document 2.

F. Schumann and J. Bock, “Silicon Bipolar IC for PRBS testing generates adjustable bit rates up to 25 Gbit / s”, IEE Electronics Letters, vol.33, no.24, pp.2022-2023, 1997 Peter Alfke, “Efficient Shift Registers, LFSR Counters, and Long Pseudo-Random Sequence Generators”, XILINX Application Note, XAPP 052, July 7, 1996, Version 1.1

The following problems occur when the conventional PRBS generator is operated at a higher speed.
(A) Difficulty in realizing high-speed clock signal distribution.
In the conventional configuration shown in FIG. 26, all circuit blocks from DFF 100-1 to DFF 100-9 operate in synchronization with a clock signal CK supplied from the outside. Therefore, a clock signal CK (full rate clock) having a frequency equal to the data signal rate is required, and the same amplitude characteristic as the simultaneity is required for the arrival time of the clock signal CK to each circuit block. In the conventional circuit configuration, the clock buffer 102 has a function of amplifying and distributing the clock signal CK. A voltage amplifier is generally used for the clock buffer 102, but the gain decreases as the frequency increases because the gain band characteristic is limited. Further, as the number of distributions increases, it becomes difficult to ensure the coincidence of jitter characteristics and arrival times. Furthermore, there is a problem that power consumption increases as the operating frequency increases.

(B) Data signal transmission loop delay time.
The data signal and the clock signal CK must be synchronized. However, signal lines and buffer circuits inserted between the respective DFFs cause some delay times due to the data signal paths. If the delay time causes a deviation in the timing between the data signal and the clock signal and exceeds the input phase margin range of the DFF, the input data signal is erroneously identified. That is, the PRBS generator malfunctions. In general, as the bit rate increases, the influence of this delay time increases. In this PRBS generator, the phase margin at the maximum operating bit rate of the DFF determines the upper limit of the delay time design in the data signal path.

(C) Power consumption.
As described above, in the conventional configuration, the power consumption increases as the operation speed increases.

  An object of the present invention is to provide a PRBS generator that alleviates the above-described problems and can operate at high speed.

The pseudo random bit string generator according to the present invention includes a number of first delay flip-flops corresponding to an integer part of K / (2V) and a number corresponding to an integer part of (N−K) / (2V) (N is 3 The above-described natural number, K is a natural number of 2 or more smaller than N, NK is an even number, and V is a natural number up to the number given by (NK) / 2) and a second delay flip-flop. 2V feedback loops included in each, and 2V first clock signals whose phases are shifted by 360 degrees / (2V), respectively, are supplied to the first and second delay flip-flops of the corresponding feedback loops. A distribution circuit, a multiplexer that multiplexes the outputs of the 2V feedback loops, and a second clock signal having a frequency 2V times that of the first clock signal. A third delay flip-flop for identifying and reproducing the signal and inputting an output signal obtained by the identification reproduction to the first delay flip-flop at the first stage of each feedback loop, and each feedback loop in its own loop The number of cascaded first delay flip-flops corresponding to the integer part of K / (2V) for identifying and reproducing the input signal at a predetermined timing of the corresponding first clock signal, and the first of the own loop The number of cascades corresponding to the integer part of (N−K) / (2V) is input and output at the predetermined timing of the first clock signal corresponding to the own loop. The connected second delay flip-flop, the signal passing through the first delay flip-flop in its own loop, and the second delay flip-flop in its own loop Performs an exclusive OR operation of a signal obtained through the result of this exclusive or operation is composed of an exclusive OR circuit which outputs to the multiplexer, the third delay bit from flip-flop Retsucho 2 ^N -1 bit string is output.

Further, the pseudo random bit string generator of the present invention includes the number of first delay flip-flops obtained by subtracting H from the number corresponding to the integer part of K / (2V) and the integer part of (NK) / (2V). The number of second delay flip-flops corresponding to and H (N is a natural number of 3 or more, K is a natural number of 2 or more smaller than N, NK is an even number, and V is given by (NK) / 2. 2V feedback loops each including a third delay flip-flop having a natural number with an upper limit of a given number, H being a natural number in the range of 0 to K / (2V), and a phase of 360 degrees / (2V) A clock distribution circuit for supplying 2V first clock signals shifted by 1 to the first, second, and third delay flip-flops of the corresponding feedback loop, and outputs of the 2V feedback loops are multiplexed. Maru The multiplexer output signal is discriminated and reproduced by a plexer and a second clock signal having a frequency 2V times that of the first clock signal, and the output signal obtained by the discriminating reproduction is used as the first stage of each feedback loop. And a fourth delay flip-flop that inputs to the delay flip-flop, and each feedback loop identifies and reproduces the input signal at a predetermined timing of the first clock signal corresponding to the own loop. The number of the first delay flip-flops connected in cascade obtained by subtracting H from the number corresponding to the integer part and the output of the first delay flip-flop of the own loop as inputs, and the first clock corresponding to the own loop The number of cascaded connections corresponding to the integer part of (N−K) / (2V) for identifying and reproducing the input signal at a predetermined timing of the signal An exclusive OR circuit that performs an exclusive OR operation on a signal that has passed through the first delay flip-flop of the own loop and a signal that has passed through the second delay flip-flop of the own loop; The output of the exclusive OR circuit of the own loop is input, the input signal is identified and reproduced at a predetermined timing of the first clock signal corresponding to the own loop, and is output to the multiplexer. The third delay flip-flop outputs a bit string having a bit string length of 2 ^N -1 from the fourth delay flip-flop.

  The configuration example of the pseudo random bit string generator according to the present invention further includes a frequency multiplier that generates the second clock signal by multiplying the frequency of the first clock signal by 2V. Is.

In addition, the pseudo random bit string generator of the present invention includes a number of first delay flip-flops, one second delay flip-flop corresponding to an integer part of (K-1) / 2, and (NK) / 2 feedbacks including the number of third delay flip-flops corresponding to the integer part of 2 (N is a natural number of 3 or more, K is a natural number of 2 or more smaller than N, and NK is an odd number) for each loop. A loop, a clock distribution circuit for supplying two first clock signals whose phases are shifted by 180 degrees to the corresponding first, second and third delay flip-flops of the corresponding feedback loop, and the two feedbacks A multiplexer that multiplexes the output of the loop and a second clock signal having a frequency twice that of the first clock signal are used to discriminate and reproduce the output signal of the multiplexer. And a fourth delay flip-flop for inputting the output signal obtained to the first delay flip-flop at the first stage of each feedback loop, each feedback loop having a predetermined first clock signal corresponding to the own loop. The number of cascaded first delay flip-flops corresponding to the integer part of (K-1) / 2 and the output of the first delay flip-flop in its own loop are identified and reproduced at the timing of One second delay flip-flop as an input for identifying and reproducing the input signal at a predetermined timing of the first clock signal corresponding to the own loop and another loop, and the second delay flip-flop of the own loop The input signal is identified and reproduced at a predetermined timing of the first clock signal corresponding to the own loop. The number of cascade-connected third delay flip-flops corresponding to a part, the signal passing through the third delay flip-flop of its own loop, and the master latch circuit in the second delay flip-flop of another loop And an exclusive OR circuit that outputs the result of the exclusive OR operation to the multiplexer. The second delay flip-flop in one loop The output of the first delay flip-flop of the loop is input, and the master latch circuit that operates with the first clock signal corresponding to another loop and the output of the master latch circuit of the own loop are input, and the output corresponds to the own loop. A slave latch circuit that operates with a first clock signal, and the second delay flip-flop in the other loop The output of one delay flip-flop is used as an input, the master latch circuit that operates with the first clock signal corresponding to its own loop, and the output of the master latch circuit of its own loop as the input, and the first corresponding to another loop And a slave latch circuit operating with a clock signal, and outputting a bit string having a bit string length of 2 ^N -1 from the fourth delay flip-flop.

The pseudo random bit string generator of the present invention includes a number of first delay flip-flops obtained by subtracting H from a number corresponding to an integer part of (K-1) / 2, and one second delay flip-flop. (N−K) / 2 third delay flip-flops corresponding to the integer part and H (N is a natural number of 3 or more, K is a natural number of 2 or more smaller than N, NK is an odd number, H Is a natural number in the range of 0 to K / 2), a feedback loop corresponding to each of two feedback loops each including a fourth delay flip-flop and two first clock signals whose phases are shifted by 180 degrees. A clock distribution circuit for supplying the first, second, third and fourth delay flip-flops of the loop; a multiplexer for multiplexing the outputs of the two feedback loops; and twice the first clock signal. A fifth delay flip-flop that discriminates and reproduces the output signal of the multiplexer by the second clock signal having the frequency and inputs the output signal obtained by the discrimination reproduction to the first delay flip-flop at the first stage of each feedback loop. Each feedback loop identifies and reproduces the input signal at a predetermined timing of the first clock signal corresponding to the own loop, and subtracts H from the number corresponding to the integer part of (K-1) / 2. The number of the first delay flip-flops connected in cascade and the output of the first delay flip-flop of the own loop are input, and the first clock signal corresponding to the own loop and another loop is input at a predetermined timing. Inputs the output of one second delay flip-flop for identifying and reproducing the signal and the second delay flip-flop of its own loop The number of cascaded third delay flip-flops corresponding to the integer part of (N−K) / 2, for identifying and reproducing the input signal at a predetermined timing of the first clock signal corresponding to the own loop An exclusive OR circuit that performs an exclusive OR operation on a signal that has passed through the third delay flip-flop of its own loop and a signal that has passed through the master latch circuit in the second delay flip-flop of another loop, The output of the exclusive OR circuit of the own loop is input, the input signal is identified and reproduced at a predetermined timing of the first clock signal corresponding to the own loop, and output to the multiplexer. And the fourth delay flip-flop, and the second delay flip-flop of one loop receives the output of the first delay flip-flop of its own loop as another input. A master latch circuit that operates with a first clock signal corresponding to the loop, and a slave latch circuit that receives the output of the master latch circuit of the own loop and operates with the first clock signal corresponding to the own loop; The second delay flip-flop of the other loop receives the output of the first delay flip-flop of the own loop and operates with a first clock signal corresponding to the own loop, and a master of the own loop. A slave latch circuit that operates with a first clock signal corresponding to another loop and that receives the output of the latch circuit, and outputs a bit string having a bit string length of 2 ^N -1 from the fifth delay flip-flop; It is characterized by.

  The configuration example of the pseudo random bit string generator according to the present invention further includes a frequency multiplier that generates the second clock signal by doubling the frequency of the first clock signal. Is.

  According to the present invention, 2V feedback loops operating at a rate 1 / (2V) of the operating rate of the third delay flip-flop are provided, and the necessary number of first and second delay flip-flops are provided in each feedback loop. And the exclusive OR circuit, the word length of the pseudo random bit string, that is, N can be set to a programmable configuration. In the present invention, the operating speed of the first and second delay flip-flops and the exclusive OR circuit that occupies the majority of the delay flip-flops in the pseudo random bit string generator is 1 / of the operating speed of the third delay flip-flop. Since (2V) is sufficient, power consumption can be reduced and a high-speed pseudo random bit string generator circuit can be easily realized. In the present invention, since the operating speed of the first and second delay flip-flops and the exclusive OR circuit may be 1 / (2V) of the operating speed of the third delay flip-flop, The operational phase margin of the delay flip-flop is not narrowed, and the possibility that the delay time due to the wiring and buffer in the feedback loop affects the operation can be reduced, so the malfunction due to the delay time due to the wiring and buffer Can be reduced.

  In the present invention, the number of first delay flip-flops obtained by subtracting H from the number corresponding to the integer part of K / (2V) and the number of first delay flip-flops corresponding to the integer part of (NK) / (2V). The operating speed of the two delay flip-flops, the H third delay flip-flops, and the exclusive OR circuit may be 1 / (2V) of the operating speed of the fourth delay flip-flop, thereby reducing power consumption. Therefore, a high-speed pseudo random bit string generator circuit can be easily realized, and malfunctions due to delay times caused by wiring and buffers can be reduced.

  In the present invention, the number of first delay flip-flops corresponding to the integer part of (K-1) / 2, one second delay flip-flop, and the integer part of (NK) / 2 are equivalent. Since the operation speed of the number of third delay flip-flops and the exclusive OR circuit can be ½ of the operation speed of the fourth delay flip-flop, power consumption can be reduced and high-speed pseudo-random A bit string generator circuit can be easily realized, and malfunctions due to delay times due to wiring and buffers can be reduced.

  In the present invention, the number of first delay flip-flops obtained by subtracting H from the number corresponding to the integer part of (K-1) / 2, one second delay flip-flop, and (NK) / The number of third delay flip-flops corresponding to the integer part of 2, the number of H fourth delay flip-flops, and the exclusive OR circuit may be 1/2 of the operation speed of the fifth delay flip-flop. Therefore, power consumption can be reduced, a high-speed pseudo random bit string generator circuit can be easily realized, and malfunctions due to delay times due to wiring and buffers can be reduced.

It is a block diagram which shows the structure of the pseudo random bit stream generator which concerns on the 1st Embodiment of this invention. It is a block diagram which shows the specific example of the pseudo random bit stream generator which concerns on the 1st Embodiment of this invention. FIG. 3 is a timing chart of the output of each delay flip-flop in the pseudo random bit string generator of FIG. 2. It is a figure which shows the signal data sequence output from each delay flip-flop in the pseudo random bit sequence generator of FIG. It is a block diagram which shows another specific example of the pseudo random bit stream generator which concerns on the 1st Embodiment of this invention. 6 is a timing chart of the output of each delay flip-flop in the pseudo random bit string generator of FIG. 5. It is a figure which shows the signal data sequence output from each delay flip-flop in the pseudo random bit sequence generator of FIG. It is a block diagram which shows another specific example of the pseudo random bit stream generator which concerns on the 1st Embodiment of this invention. It is a block diagram which shows another specific example of the pseudo random bit stream generator which concerns on the 1st Embodiment of this invention. It is a block diagram which shows another specific example of the pseudo random bit stream generator which concerns on the 1st Embodiment of this invention. It is a block diagram which shows another specific example of the pseudo random bit stream generator which concerns on the 1st Embodiment of this invention. It is a block diagram which shows the structure of the pseudo random bit stream generator which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the specific example of the pseudo random bit stream generator which concerns on the 2nd Embodiment of this invention. It is a timing chart of the output of each delay flip-flop in the pseudo random bit string generator of FIG. It is a figure which shows the signal data sequence output from each delay flip-flop in the pseudo random bit sequence generator of FIG. It is a block diagram which shows another specific example of the pseudo random bit stream generator which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows another specific example of the pseudo random bit stream generator which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows another specific example of the pseudo random bit stream generator which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows another specific example of the pseudo random bit stream generator which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the pseudo random bit stream generator which concerns on the 3rd Embodiment of this invention. It is a block diagram which shows the specific example of the pseudo random bit stream generator which concerns on the 3rd Embodiment of this invention. It is a timing chart of the output of each delay flip-flop in the pseudo random bit string generator of FIG. It is a figure which shows the signal data sequence output from each delay flip-flop in the pseudo random bit sequence generator of FIG. It is a block diagram which shows another specific example of the pseudo random bit stream generator which concerns on the 3rd Embodiment of this invention. It is a block diagram which shows the structure of the pseudo random bit stream generator which concerns on the 4th Embodiment of this invention. It is a block diagram which shows the structure of the conventional pseudorandom bit string generator of bit string length 2 ⁹ -1. It is a timing chart of the output of each delay flip-flop in the pseudo random bit string generator of FIG. It is a figure which shows the signal data sequence output from each delay flip-flop in the pseudo random bit stream generator of FIG. It is a block diagram which shows the structure of the conventional pseudorandom bit stream generator of bit stream length ^2N- 1.

[First Embodiment]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a PRBS generator according to the first embodiment of the present invention. This embodiment can be applied to a 2 ^N −1 PRBS generator using two taps (N, K) (N is a natural number of 3 or more, K is a natural number of 2 or more smaller than ^{N, and} NK is an even number). It is. Here, N is the number of the DFF that extracts the first tap tap1 described in Table 1, K is the number of the DFF that extracts the second tap tap2 described in Table 1, and V is (NK). It is a natural number whose upper limit is the number given by / 2. For example, when N = 9 and K = 5, (NK) / 2 = 2, and V can take either 1 or 2.

  The PRBS generator of the present embodiment distributes a clock buffer (hereinafter referred to as CBUF) 1 that operates at a signal rate of 1 / (2V) and a 1 / (2V) clock signal that is output from CBUF1, and generates a clock signal. A clock distribution circuit 2 having a phase adjustment function, a frequency multiplier 3 that multiplies a 1 / (2V) clock signal by 2V, a multiplexer (hereinafter referred to as MUX) 4 that performs 2V: 1 bit multiplexing, and a full rate clock operation. DFF5-1, output buffer (hereinafter referred to as OBUF) 6, Int [K / (2V)] DFF5-a, Int [(NK) / (2V)] DFF5-b and one The XOR circuit 7 includes 2V feedback loops 8 each constituting a loop. Int [] means the integer part of the numerical value in []. The XOR circuit 7 in each feedback loop has two input terminals. The output signals of Int [K / (2V)] DFF5-a and Int [(NK) / (2V)] The output signal of DFF5-b is used as an input.

  In the present embodiment, the frequency multiplier 3, the MUX4, the DFF5-1, and the OBUF6 operate with a clock signal having a frequency of F1 and a period of T1 (T1 = 1 / F1) (hereinafter abbreviated as a full-rate clock signal). The CBUF1, the clock distribution circuit 2, the DFF5-a, the DFF5-b, and the XOR circuit 7 are clock signals having a frequency of (1 / (2V)) F1 and a cycle of 2V × T1 (hereinafter abbreviated as a divided clock signal). Operate.

  Here, the phase adjustment function to be provided in the clock distribution circuit 2 will be described. In the DFF arranged in the first stage of each feedback loop, in order to ensure a phase margin for the demultiplexer operation, the phase of the divided clock signal having a signal rate of 1 / (2V) is optimal for each feedback loop. Must be set to a value. That is, if this phase adjustment amount is θ, this value depends on 2V, which is the sum of the number of feedback loops. Specifically, it can be set to an optimum value by setting θ = 360 degrees / (2V). It becomes possible. For example, when N = 9, K = 5, and V = 1, the optimum phase adjustment amount θ is 180 degrees. When N = 9, K = 5, and V = 2, the optimum phase adjustment amount θ is 90 degrees. That is, the clock distribution circuit 2 outputs 2V frequency-divided clock signals whose phases are shifted by θ. By providing the clock distribution circuit 2 with such a phase adjustment function of the divided clock signal, the phase margin in each feedback loop can be optimized.

Next, the circuit operation of the 2 ^N −1 PRBS generator of FIG. 1 will be described. A frequency-divided clock signal is input to CBUF1, and the frequency-divided clock signal is supplied from CBUF1 to clock distribution circuit 2, frequency multiplier 3, and MUX4. The frequency multiplier 3 supplies a full-rate clock signal having a frequency 2V times that of the divided clock signal to the DFF 5-1.
The DFF 5-1 retimates and reproduces the output bit of the MUX 4 at the rising edge of the full rate clock signal supplied from the frequency multiplier 3, and holds the bit for the period of the full rate clock signal.

  After the output signal of DFF 5-1 is separated into 2V paths, the first DFF of each feedback loop operates with a divided clock signal with a signal rate of 1 / (2 V), so that the demultiplexer operation is once performed. As a result, the operation rate becomes 1 / (2V). Thereafter, the XOR circuit 7 exclusively uses a signal that has passed through Int [K / (2V)] DFF5-a and a signal that has passed through Int [(NK) / (2V)] DFF5-b. Performs a logical OR operation. That is, the delay difference between the two signals is (NK) × T1.

  Then, the MUX 4 sequentially takes in the output of the XOR circuit 7 of the feedback loop corresponding to the divided clock signal at the rising edge of the divided clock signal for each divided clock (for each feedback loop). In this way, the MUX 4 multiplexes the outputs of the XOR circuits 7 of the respective feedback loops by repeatedly taking in and outputting the outputs of the XOR circuits 7 of the respective feedback loops in turn at the rising edges of the divided clock signals. Therefore, the output signal of MUX4 is converted to the full rate.

  The output bit string of the DFF 5-1 is output to the outside as the output bit string Out of the PRBS generator via the OBUF 6. When N is an odd number, it is necessary to arrange DFF5-1 in the subsequent stage of MUX4. However, when N is an even number, it is not necessary to arrange DFF5-1.

In the circuit configuration of the conventional 2 ^N −1 PRBS generator, the output of the Nth DFF 100 -N and the output of the Kth DFF 100 -K are input to the XOR circuit 101 as shown in FIG. Here, signals from DFF 100-K to DFF 100-N are delayed by (N−K) DFFs.

  On the other hand, according to the present embodiment, it is possible to reduce the operation bit rate of these DFFs in order to obtain the same delay. That is, when the number of DFFs is ½, the DFF operates at a half rate, and when the number of DFFs is ¼, the DFF operates at a data rate of ¼. Become. Since the clock rate of the DFF that causes these delays can be reduced, power consumption can be reduced.

FIG. 2 is a block diagram showing a specific example of the PRBS generator of the present embodiment, and is a block diagram showing a circuit configuration of a 2 ⁹ -1 PRBS generator using a 1/2 rate divided clock signal. In this example, N = 9, K = 5, and V = 1. In this example, 2V = 2 feedback loops are provided. The first feedback loop includes Int [K / (2V)] = 2 DFF5-2, 5-4 corresponding to DFF5-a in FIG. 1 and Int [(N -K) / (2V)] = 2, which is composed of two DFFs 5-6 and 5-8 and an XOR circuit 7-1. The XOR circuit 7-1 performs an exclusive OR operation between the output of the DFF 5-4 and the output of the DFF 5-8. On the other hand, the second feedback loop includes Int [K / (2V)] = 2 DFF5-3, 5-5 corresponding to DFF5-a in FIG. 1 and Int [K] corresponding to DFF5-b in FIG. (N−K) / (2V)] = 2 DFFs 5-7 and 5-9, and an XOR circuit 7-2. The XOR circuit 7-2 performs an exclusive OR operation on the output of the DFF 5-5 and the output of the DFF 5-9.

  The DFF 5-1 and the OBUF 6 arranged at the subsequent stage of the MUX 4 in FIG. 2 operate at a full rate, but other circuit blocks, that is, the CBUF 1, the clock distribution circuit 2, the DFFs 5-2 to 5-9, the XOR circuit 7-1, 7-2 operates with a divided clock signal (hereinafter referred to as a half-rate clock signal) whose frequency is ½ with respect to the full-rate clock signal. The frequency multiplier 3 supplies a full-rate clock signal having a frequency 2V = 2 times that of the half-rate clock signal to the DFF 5-1.

  The clock distribution circuit 2 supplies the half-rate clock signal from the CBUF 1 to the DFFs 5-2, 5-4, 5-6, and 5-8 of the first feedback loop, and the half-rate clock signal is 180 degrees out of phase with the half-rate clock signal. Different half rate clock signals are supplied to DFFs 5-3, 5-5, 5-7, 5-9 of the second feedback loop.

  In the conventional circuit configuration shown in FIG. 26, the output of the DFF 100-9 and the output of the DFF 100-5 are input to the XOR circuit 101. On the other hand, in the example of FIG. 2, two feedback loops are configured using the DFFs 5-2 to 5-9 that operate at a half rate. The circuit configuration of FIG. 2 is characterized in that power consumption can be greatly reduced because most of the circuit configuration operates with a half-rate clock signal. Further, since all the DFFs 5-2 to 5-9 except the DFF 5-1 operate with the half-rate clock signal, the layout design and timing design of the clock distribution circuit 2 are facilitated, and at the same time, the DFFs 5-2 to 5-9. Since the timing margin at 1 is wide, the timing design is easy.

FIG. 3 shows a timing chart of outputs of all nine DFFs 5-1 to 5-9 in FIG. 2, and FIG. 4 shows signal data strings output from the nine DFFs 5-1 to 5-9. In FIG. 3, bit A _X is equal to the result of exclusive OR of bit A _X-9 and bit A _X-5 (X is an arbitrary value). The vertical axis in FIG. 4 is voltage.

  In the example of FIG. 2, the output of DFF5-1 is input to DFF5-2 and 5-3. The first feedback loop including the even-numbered DFFs 5-2, 5-4, 5-6, 5-8 and the XOR circuit 7-1 connected in cascade, and the odd-numbered DFFs 5-3 connected in cascade. , 5-5, 5-7, 5-9 and the XOR circuit 7-2 operate so as to be shifted by 180 degrees in the phase of the half rate clock.

  For example, the even-numbered DFFs 5-2, 5-4, 5-6, and 5-8 retime the output bit of the preceding DFF at the rising edge of the first half-rate clock signal output from the clock distribution circuit 2. The identification is reproduced, and the bit is held for the period of 2 × T1 of the first half rate clock signal. The odd-numbered DFFs 5-3, 5-5, 5-7, and 5-9 receive the output bits of the preceding DFF at the rising edge of the second half-rate clock signal that is 180 degrees out of phase with the first half-rate clock signal. Recognizing and reproducing by retiming, the bit is held for the period of 2 × T1 of the second half rate clock signal.

  As a result, each feedback loop identifies and reproduces either the even-numbered or odd-numbered bit string. For example, when the first feedback loop including even-numbered DFFs 5-2, 5-4, 5-6 and 5-8 discriminates and reproduces only even-numbered bit strings, odd-numbered DFFs 5-3, 5-5 and 5 The second feedback loop including -7 and 5-9 is for identifying and reproducing only the odd-numbered bit string.

  The MUX 4 captures and outputs the output of the XOR circuit 7-1 of the first feedback loop at the rising edge of the first half-rate clock signal, and outputs the second feedback loop at the rising edge of the second half-rate clock signal. The output of the XOR circuit 7-2 is taken in and output. Thus, the MUX 4 multiplexes the outputs of the XOR circuits 7-1 and 7-2 by alternately taking and outputting the outputs of the XOR circuits 7-1 and 7-2. Therefore, the output signal of MUX4 is converted to the full rate.

As a result, the circuit shown in FIG. 2 operates at the timing shown in FIG. According to FIG. 4, in DFF5-1, it can be seen that conventional 2 ⁹ -1 PRBS generator similar to the bit Retsucho 2 ⁹ -1 = 511 bits of the bit string is obtained.

FIG. 5 is a block diagram showing a specific example of the PRBS generator according to the present embodiment, and is a block diagram showing a circuit configuration of a 2 ⁹ -1 PRBS generator using a 1/4 rate divided clock signal. In this example, N = 9, K = 5, and V = 2. In this example, 2V = 4 feedback loops are provided.

  The first feedback loop includes Int [K / (2V)] = 1 DFF5-2 corresponding to DFF5-a in FIG. 1 and Int [(NK) / corresponding to DFF5-b in FIG. (2V)] = 1 DFF 5-6 and XOR circuit 7-1. The XOR circuit 7-1 performs an exclusive OR operation on the output of the DFF 5-2 and the output of the DFF 5-6. The second feedback loop includes Int [K / (2V)] = 1 DFF5-3 corresponding to DFF5-a in FIG. 1 and Int [(NK) / corresponding to DFF5-b in FIG. (2V)] = 1 DFF 5-7 and XOR circuit 7-2. The XOR circuit 7-2 performs an exclusive OR operation between the output of the DFF 5-3 and the output of the DFF 5-7.

  The third feedback loop includes Int [K / (2V)] = 1 DFF5-4 corresponding to DFF5-a in FIG. 1 and Int [(NK) / corresponding to DFF5-b in FIG. (2V)] = 1 DFF 5-8 and XOR circuit 7-3. The XOR circuit 7-3 performs an exclusive OR operation on the output of the DFF 5-4 and the output of the DFF 5-8. The fourth feedback loop includes Int [K / (2V)] = 1 DFF5-5 corresponding to DFF5-a in FIG. 1 and Int [(NK) / corresponding to DFF5-b in FIG. (2V)] = 1 DFF 5-9 and XOR circuit 7-4. The XOR circuit 7-4 performs an exclusive OR operation on the output of the DFF 5-5 and the output of the DFF 5-9.

  The DFF 5-1 and the OBUF 6 arranged at the subsequent stage of the MUX 4 in FIG. 5 operate at a full rate, but other circuit blocks, that is, the CBUF 1, the clock distribution circuits 2-1 to 2-4, and the DFFs 5-2 to 5-9, The XOR circuits 7-1 to 7-4 operate with a clock signal whose frequency is 1/4 rate with respect to the full rate clock signal. The frequency multiplier 3 supplies a full-rate clock signal having a frequency 2V = 4 times that of the quarter-rate clock signal to the DFF 5-1.

  The clock distribution circuit 2-1 supplies the quarter rate clock signal (θ = 0 degree) from the CBUF 1 to the DFFs 5-2 and 5-6 of the first feedback loop. The clock distribution circuit 2-2 sends a 1/4 rate clock signal (θ = 90 degrees) whose phase is delayed by 90 degrees with respect to the clock signal supplied to the first feedback loop to the DFF 5-3 of the second feedback loop. , 5-7. The clock distribution circuit 2-3 uses the 1/4 rate clock signal (θ = 180 degrees) whose phase is delayed by 180 degrees with respect to the clock signal supplied to the first feedback loop as the DFF 5-4 of the third feedback loop. , 5-8. The clock distribution circuit 2-4 outputs a ¼ rate clock signal (θ = 270 degrees) whose phase is delayed by 270 degrees relative to the clock signal supplied to the first feedback loop to the DFF 5-5 of the fourth feedback loop. , 5-9.

FIG. 6 shows a timing chart of outputs of all nine DFFs 5-1 to 5-9 in FIG. 2, and FIG. 7 shows signal data strings output from the nine DFFs 5-1 to 5-9. In FIG. 6, bit A _X is equal to the result of exclusive OR of bit A _X-9 and bit A _X-5 (X is an arbitrary value). The vertical axis in FIG. 7 is voltage.

  In the example of FIG. 5, the output of DFF5-1 is input to DFF5-2, 5-3, 5-4, and 5-5. A first feedback loop composed of cascaded DFFs 5-2, 5-6 and an XOR circuit 7-1 and a first feedback loop composed of cascaded DFFs 5-3, 5-7 and an XOR circuit 7-2. 2 feedback loops, a third feedback loop composed of cascaded DFFs 5-4 and 5-8 and an XOR circuit 7-3, and cascaded DFFs 5-5 and 5-9 and an XOR circuit 7-4 Is operated so as to be shifted by 90 degrees in order of the phase of the 1/4 rate clock.

  For example, the DFFs 5-2 and 5-6 of the first feedback loop are identified by retiming the output bit of the preceding DFF at the rising edge of the first ¼ rate clock signal output from the clock distribution circuit 2-1. Reproduce and hold bits for a period of 4 × T1 of the first quarter rate clock signal. The DFFs 5-3 and 5-7 in the second feedback loop output the DFF in the preceding stage at the rising edge of the second quarter rate clock signal whose phase is delayed by 90 degrees with respect to the first quarter rate clock signal. Recognizing and reproducing the bit by retiming the bit, the bit is held for the period of 4 × T1 of the second quarter rate clock signal.

  The DFFs 5-4 and 5-8 in the third feedback loop output the DFF in the preceding stage at the rising edge of the third quarter-rate clock signal whose phase is delayed by 180 degrees with respect to the first quarter-rate clock signal. Recognizing and reproducing the bit by retiming the bit, the bit is held for a period of 4 × T1 of the third quarter-rate clock signal. The DFFs 5-5 and 5-9 in the fourth feedback loop output the DFF in the preceding stage at the rising edge of the fourth quarter-rate clock signal whose phase is delayed by 270 degrees with respect to the first quarter-rate clock signal. Recognizing and reproducing the bit by retiming the bit, the bit is held for a period of 4 × T1 of the fourth quarter rate clock signal.

  The MUX 4 captures and outputs the output of the XOR circuit 7-1 of the first feedback loop at the rising edge of the first 1/4 rate clock signal, and the second at the rising edge of the second 1/4 rate clock signal. The output of the XOR circuit 7-2 of the third feedback loop is captured and output at the rising edge of the third quarter-rate clock signal, and the output of the XOR circuit 7-3 of the third feedback loop is captured and output. The output of the XOR circuit 7-4 of the fourth feedback loop is taken in and output at the rising edge of the 1/4 rate clock signal. In this manner, the MUX 4 repeatedly takes in and outputs the outputs of the XOR circuits 7-1, 7-2, 7-3, and 7-4, and thereby outputs the XOR circuits 7-1, 7-2, and 7-2. , 7-4 are multiplexed. Therefore, the output signal of MUX4 is converted to the full rate.

As a result, the circuit shown in FIG. 5 operates at the timing shown in FIG. According to FIG. 7, in DFF5-1, it can be seen that conventional 2 ⁹ -1 PRBS generator similar to the bit Retsucho 2 ⁹ -1 = 511 bits of the bit string is obtained.

So far, a circuit configuration using two feedback loops operating with a half rate clock signal as a 2 ⁹ -1 PRBS generator and a circuit configuration using four feedback loops operating with a quarter rate clock signal have been described. This type of configuration is directly applicable when N is an odd number among 2 ^N -1 PRBS generators using two taps in the conventional configuration as shown in FIG. That is, this corresponds to the case where two taps (N, K) shown in Table 1 are used and NK is an even number.

  Like the examples described so far, examples of circuit configurations relating to several N are shown in FIGS. 8 is for N = 5, K = 3, and V = 1, FIG. 9 is for N = 11, K = 9, and V = 1, and FIG. 10 is for N = 21, K = 19, and V = 1. FIG. 11 shows an example when N = 29, K = 27, and V = 1. Each of the PRBS generators of FIGS. 8 to 11 has a configuration using two feedback loops that operate with a half-rate clock signal, and the operation is the same as the circuit configuration of FIG. Omitted.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. FIG. 12 is a block diagram showing a configuration of a PRBS generator according to the second embodiment of the present invention. This embodiment shows another configuration example of the 2 ^N −1 PRBS generator described in the first embodiment.
In the present embodiment, Int [K / (2V)]-H DFF5-c, Int [(NK) / (2V)] DFF5-d, one XOR circuit 7, and H The DFF5-e includes 2V feedback loops 8 each of which constitutes a loop. As in the first embodiment, N is a natural number of 3 or more, K is a natural number of 2 or more smaller than N, and NK is an even number.

The operations of CBUF1, clock distribution circuit 2, frequency multiplier 3, MUX4, DFF5-1, and OBUF6 are as described in the first embodiment.
The difference between the present embodiment and the first embodiment is the configuration of each feedback loop, and the arrangement of the XOR circuit 7 is different in this embodiment. In the first embodiment, the XOR circuit 7 is arranged at the output part of each feedback loop. However, since the XOR circuit 7 is not controlled by the clock signal, the output waveform quality is inferior to the output of the DFF. . Since the DFF operates in synchronization with the clock signal, the jitter characteristic and the fluctuation amount of the signal in the time axis direction are usually small. Since the output signal of each feedback loop is multiplexed by the MUX 4 at the next stage, good waveform quality is required.

  Therefore, in the present embodiment, this problem is solved by arranging H DFFs 5-e in the subsequent stage of the XOR circuit 7. The total sum of DFFs to be arranged in the feedback loop is determined by the previous circuit configuration described in the first embodiment. Here, the value of H must be an integer in the range of 0 to K / (2V). Also, the number of DFFs in the first stage of each feedback loop needs to be determined in consideration of the phase margin when the demultiplexer operates. From the above, it is desirable that H is an integer value of about K / (4V).

FIG. 13 is a block diagram showing a specific example of the PRBS generator of the present embodiment, and is a block diagram showing a circuit configuration of a 2 ⁹ -1 PRBS generator using a half-rate clock signal. In this example, N = 9, K = 5, V = 1, and H = 1. In this example, 2V = 2 feedback loops are provided.

  The first feedback loop includes Int [K / (2V)] − H = 1 corresponding to DFF5-c in FIG. 12 and Int [(N−K) corresponding to DFF5-d in FIG. ) / (2V)] = 2 DFFs 5-4 and 5-6, an XOR circuit 7-1, and H = 1 DFF 5-8 corresponding to DFF5-e in FIG. The XOR circuit 7-1 performs an exclusive OR operation on the output of the DFF 5-2 and the output of the DFF 5-6.

  On the other hand, the second feedback loop includes Int [K / (2V)] − H = 1 corresponding to DFF5-c in FIG. 12 and Int [(N corresponding to DFF5-d in FIG. -K) / (2V)] = 2 DFF5-5, 5-7, XOR circuit 7-2, and H = 1 DFF5-9 corresponding to DFF5-e in FIG. Yes. The XOR circuit 7-2 performs an exclusive OR operation between the output of the DFF 5-3 and the output of the DFF 5-7.

FIG. 14 shows a timing chart of the outputs of all nine DFFs 5-1 to 5-9 in FIG. 13, and FIG. 15 shows a signal data string output from the nine DFFs 5-1 to 5-9. In FIG. 14, bit A _X is equal to the result of exclusive OR of bit A _X-9 and bit A _X-5 (X is an arbitrary value). The vertical axis in FIG. 15 is voltage.

  In the example of FIG. 13, the output of DFF5-1 is input to DFF5-2 and 5-3. The first feedback loop including the even-numbered DFFs 5-2, 5-4, 5-6, 5-8 and the XOR circuit 7-1 connected in cascade, and the odd-numbered DFFs 5-3 connected in cascade. , 5-5, 5-7, 5-9 and the XOR circuit 7-2 operate so as to be shifted by 180 degrees in the phase of the half rate clock.

  The DFFs 5-2, 5-4, and 5-6 in the first feedback loop perform identification reproduction by retiming the output bit of the preceding DFF at the rising edge of the first half-rate clock signal output from the clock distribution circuit 2. Then, the bit is held for the period 2 × T1 of the first half-rate clock signal. The DFF 5-8 re-identifies and reproduces the output bit of the XOR circuit 7-1 at the rising edge of the first half-rate clock signal, and holds the bit for the period of 2 × T1 of the first half-rate clock signal. .

  The DFFs 5-3, 5-5, and 5-7 of the second feedback loop reset the output bit of the preceding DFF at the rising edge of the second half-rate clock signal that is 180 degrees out of phase with the first half-rate clock signal. Recognizing and reproducing at the timing, the bit is held for the period of 2 × T1 of the second half rate clock signal. The DFF 5-9 retimates and reproduces the output bit of the XOR circuit 7-2 at the rising edge of the second half-rate clock signal, and holds the bit for the period of 2 × T1 of the second half-rate clock signal. .

  The MUX 4 takes in and outputs the output of the DFF 5-8 of the first feedback loop at the rising edge of the first half-rate clock signal, and outputs the DFF 5- of the second feedback loop at the rising edge of the second half-rate clock signal. 9 output is captured and output. Thus, the MUX 4 multiplexes the outputs of the DFFs 5-8 and 5-9 by alternately taking and outputting the outputs of the DFFs 5-8 and 5-9. Therefore, the output signal of MUX4 is converted to the full rate.

As a result, the circuit shown in FIG. 13 operates at the timing shown in FIG. According to FIG. 15, in DFF5-1, it can be seen that conventional 2 ⁹ -1 PRBS generator similar to the bit Retsucho 2 ⁹ -1 = 511 bits of the bit string is obtained.

So far, a circuit configuration using two feedback loops operating with a half-rate clock signal as a 2 ⁹ -1 PRBS generator has been described. This type of configuration is directly applicable when N is an odd number among 2 ^N -1 PRBS generators using two taps in the conventional configuration as shown in FIG. That is, this corresponds to the case where two taps (N, K) shown in Table 1 are used and NK is an even number.

  Like the examples described so far, examples of circuit configurations relating to several N are shown in FIGS. 16 is N = 5, K = 3, V = 1, and H = 1. FIG. 17 is N = 11, K = 9, V = 1, and H = 1. = 19, V = 1, H = 1, FIG. 19 shows an example of N = 29, K = 27, V = 1, and H = 1. Each of the PRBS generators of FIGS. 16 to 19 has a configuration using two feedback loops that operate with a half-rate clock signal, and the operation is the same as the circuit configuration of FIG. Omitted.

[Third Embodiment]
Next, a third embodiment of the present invention will be described. FIG. 20 is a block diagram showing the configuration of the PRBS generator according to the present embodiment. This embodiment can be applied to a 2 ^N −1 PRBS generator using two taps (N, K) (N is a natural number of 3 or more, K is a natural number of 2 or more smaller than ^{N, and} NK is an odd number). It is. Here, N is the number of the DFF that extracts the first tap tap1 described in Table 1, and K is the number of the DFF that extracts the second tap tap2 described in Table 1. In the case of this embodiment, V = 1, that is, only a configuration using two feedback loops operating with a half-rate clock signal is applicable.

  The PRBS generator according to the present embodiment includes a CBUF 1 that operates at a signal rate of 1/2, a clock distribution circuit 2 that distributes a half-rate clock signal output from the CBUF 1 and has a phase adjustment function of the clock signal, and a half A frequency multiplier 3 that doubles the rate clock signal, a MUX 4 that performs 2: 1 bit multiplexing, a DFF 5-1 that performs a full rate clock operation, an OBUF 6, an Int [N / 2] DFF, and one The XOR circuit 7 includes two feedback loops 8 each constituting a loop.

  The first feedback loop consists of Int [(K−1) / 2] DFF5-f, 1 DFF5-K, Int [(N−K) / 2] DFF5-g, and 1 XOR. Circuit 7-1. The DFF5-K includes a master latch circuit 9-K-1 and a slave latch circuit 9-K-2. The second feedback loop consists of Int [(K−1) / 2] DFF5-h, 1 DFF5-K + 1, Int [(N−K) / 2] DFF5-i, and 1 XOR. Circuit 7-2. DFF5-K + 1 includes a master latch circuit 9-K + 1-1 and a slave latch circuit 9-K + 1-2.

  The XOR circuit 7-1 in the first feedback loop includes the output of the final stage DFF5-g in the first feedback loop and Int [(K-1) / 2] DFF5 in the second feedback loop. Performs an exclusive OR operation with the output of the master latch circuit 9-K + 1-1 of DFF5-K + 1 arranged at the next stage of -h. On the other hand, the XOR circuit 7-2 in the second feedback loop includes the output of the final stage DFF5-i in the second feedback loop and Int [(K-1) / 2] pieces in the first feedback loop. XFF with the output of the master latch circuit 9-K-1 of DFF5-K arranged at the next stage of DFF5-f.

Next, the circuit operation of the 2 ^N −1 PRBS generator of FIG. 20 will be described. In this embodiment, the frequency multiplier 3, the MUX 4, the DFF 5-1, and the OBUF 6 operate at a full rate, and the CBUF 1, the clock distribution circuit 2, and the DFFs 5-f, 5-g, 5-h, 5-i, 5- K, 5-K + 1 and XOR circuits 7-1, 7-2 operate with a half-rate clock signal. The frequency multiplier 3 supplies a full-rate clock signal having a frequency twice that of the half-rate clock signal to the DFF 5-1.

  The DFF 5-1 retimates and reproduces the output bit of the MUX 4 at the rising edge of the full rate clock signal supplied from the frequency multiplier 3, and holds the bit for the period of the full rate clock signal.

  The clock distribution circuit 2 includes a slave latch circuit 9-K-2 in the DFF5-f, 5-g and DFF5-K of the first feedback loop and a master latch circuit 9- in the DFF5-K + 1 of the second feedback loop. A half-rate clock signal from CBUF1 is supplied to K + 1-1, and a half-rate clock signal that is 180 degrees out of phase with this half-rate clock signal is supplied to DFF5-h, 5-i and DFF5-K + 1 in the second feedback loop. To the slave latch circuit 9-K + 1-2 and the master latch circuit 9-K-1 in the DFF5-K of the first feedback loop.

After the output signal of DFF 5-1 is separated into two paths, the first DFF of each feedback loop operates with a half-rate clock signal, so that the demultiplexer operation is performed once and the operation rate becomes 1/2. Become.
The DFFs 5-f and 5-g of the first feedback loop perform identification and reproduction by retiming the output bit of the preceding DFF at the rising edge of the first half-rate clock signal output from the clock distribution circuit 2. Bits are held for a period of 2 × T1 of the half rate clock signal. The master latch circuit 9-K-1 in the DFF5-K of the first feedback loop receives a second half-rate clock signal that is 180 degrees out of phase with the first half-rate clock signal output from the clock distribution circuit 2. When it is at “H” level, the output of the preceding DFF5-f is output as it is to the subsequent stage, and when the second half-rate clock signal is at “L” level, the data output at the previous “H” level is held. The slave latch circuit 9-K-2 in the DFF5-K of the first feedback loop uses the output of the master latch circuit 9-K-1 at the previous stage as it is when the first half-rate clock signal is at the “H” level. When the first half rate clock signal is at “L” level, the data output at the immediately preceding “H” level is held.

  The DFFs 5-h and 5-i in the second feedback loop re-identify and reproduce the output bit of the preceding DFF at the rising edge of the second half-rate clock signal, and the period 2 of the second half-rate clock signal. X Hold the bit for T1. The master latch circuit 9-K + 1-1 in the DFF5-K + 1 of the second feedback loop outputs the output of the previous stage DFF5-h to the subsequent stage as it is when the first half-rate clock signal is at "H" level, When the first half-rate clock signal is at “L” level, the data output at the previous “H” level is held. The slave latch circuit 9-K + 1-2 in the DFF5-K + 1 of the second feedback loop uses the output of the master latch circuit 9-K + 1-1 in the previous stage as it is when the second half-rate clock signal is at “H” level. When the second half-rate clock signal is “L” level, the data output at the previous “H” level is held.

  Thereafter, the XOR circuits 7-1 and 7-2 in each feedback loop receive the signal passing through Int [N / 2] DFFs in the own loop and Int [(K-1) in the opposite loop. / 2] Performs an exclusive OR operation with a signal that has passed through the master latch circuit of the DFF arranged in the next stage of the number of DFFs. That is, the delay difference between the two signals is (NK) × T1 (T1 is the period of the full-rate clock signal).

The MUX 4 sequentially takes in the outputs of the XOR circuits 7-1 and 7-2 of the feedback loop corresponding to the half-rate clock signal at the rising edge of the half-rate clock signal in order of the half-rate clock signal (each feedback loop). Do. In this way, the MUX 4 repeatedly takes in and outputs the outputs of the XOR circuits 7-1 and 7-2 of each feedback loop in turn at the rising edge of each half-rate clock signal, so that the XOR circuit 7-1 of each feedback loop. 7-2 are multiplexed. Therefore, the output signal of MUX4 is converted to the full rate.
The output bit string of the DFF 5-1 is output to the outside as the output bit string Out of the PRBS generator via the OBUF 6.

In the circuit configuration of the conventional 2 ^N −1 PRBS generator, the output of the Nth DFF 100 -N and the output of the Kth DFF 100 -K are input to the XOR circuit 101 as shown in FIG. Here, signals from DFF 100-K to DFF 100-N are delayed by (N−K) DFFs.

  On the other hand, according to the present embodiment, it is possible to reduce the operation bit rate of these DFFs in order to obtain the same delay. That is, when the number of DFFs is ½, the DFFs operate at a half rate. Since the clock rate of the DFF that causes these delays can be reduced, power consumption can be reduced.

FIG. 21 is a block diagram showing a specific example of the PRBS generator of the present embodiment, and is a block diagram showing a circuit configuration of a 2 ¹⁷ −1 PRBS generator using a half-rate clock signal. In this example, N = 17 and K = 14. The first feedback loop is Int [(K-1) / 2] = 6 DFFs 5-2, 5-4, 5-6, 5-8, 5-10, which corresponds to DFF5-f in FIG. 5-12 and one DFF5-14 corresponding to DFF5-K in FIG. 20 and Int [(N−K) / 2] = 1 DFF5-16 corresponding to DFF5-g in FIG. And an XOR circuit 7-1. The DFF 5-14 includes a master latch circuit 9-14-1 and a slave latch circuit 9-14-2.

  The second feedback loop includes Int [(K-1) / 2] = 6 DFFs 5-3, 5-5, 5-7, 5-9, 5-11, which corresponds to DFF5-h in FIG. 5-13 and one DFF5-15 corresponding to DFF5-K + 1 in FIG. 20 and Int [(NK) / 2] = 1 DFF5-17 corresponding to DFF5-i in FIG. XOR circuit 7-2. The DFF 5-15 includes a master latch circuit 9-15-1 and a slave latch circuit 9-15-2.

  The XOR circuit 7-1 in the first feedback loop includes the output of the final stage DFF 5-16 in the first feedback loop and Int [(K-1) / 2] = 6 in the second feedback loop. Exclusive logic with the output of the master latch circuit 9-15-1 of the DFF 5-15 arranged at the next stage of the DFFs 5-3, 5-5, 5-7, 5-9, 5-11, 5-13 Perform a sum operation. On the other hand, the XOR circuit 7-2 in the second feedback loop outputs the output of the final stage DFF 5-17 in the second feedback loop and Int [(K-1) / 2] = in the first feedback loop. Exclusive with the output of the master latch circuit 9-14-1 of the DFF 5-14 arranged in the next stage of the six DFFs 5-2, 5-4, 5-6, 5-8, 5-10, 5-12 Perform logical OR operation.

  The DFF 5-1 and the OBUF 6 arranged at the subsequent stage of the MUX 4 in FIG. 21 operate at a full rate, but other circuit blocks, that is, the CBUF 1, the clock distribution circuit 2, the DFFs 5-2 to 5-17, the XOR circuit 7-1, 7-2 operates with a half-rate clock signal.

  The clock distribution circuit 2 is a slave latch circuit 9-in the DFF 5-2, 5-4, 5-6, 5-8, 5-10, 5-12, 5-16 and the DFF 5-14 in the first feedback loop. A half rate clock signal from CBUF1 is supplied to the master latch circuit 9-15-1 in the DFF 5-15 of the second feedback loop 14-2 and the half rate clock signal 180 degrees out of phase with this half rate clock signal. The signal is sent to DFF 5-3, 5-5, 5-7, 5-9, 5-11, 5-13, 5-17 in the second feedback loop and slave latch circuit 9-15-2 in DFF 5-15. This is supplied to the master latch circuit 9-14-1 in the DFF 5-14 of the first feedback loop.

FIG. 22 shows a timing chart of outputs from DFFs 5-1 to 5-3 and 5-12 to 5-17 in FIG. 21, and FIG. 23 shows signal data strings output from 17 DFFs 5-1 to 5-17. Show. In FIG. 22, bit A _X is equal to the result of the exclusive OR of bit A _X-17 and bit A _X-14 (X is an arbitrary value). The vertical axis in FIG. 23 is voltage.

  In the example of FIG. 21, the output of DFF5-1 is input to DFF5-2 and 5-3. DFFs 5-2, 5-4, 5-6, 5-8, 5-10, 5-12, and 5-16 of the first feedback loop are the first half-rate clock signals output from the clock distribution circuit 2. At the rising edge, the output bit of the preceding DFF is retimed for identification and reproduction, and the bit is held for the period of 2 × T1 of the first half-rate clock signal. The master latch circuit 9-14-1 in the DFF 5-14 of the first feedback loop receives a second half rate clock signal that is 180 degrees out of phase with the first half rate clock signal output from the clock distribution circuit 2. When it is at “H” level, the output of the preceding DFF 5-12 is output as it is to the subsequent stage, and when the second half rate clock signal is at “L” level, the data output at the previous “H” level is held. The slave latch circuit 9-14-2 in the DFF 5-14 of the first feedback loop uses the output of the master latch circuit 9-14-1 in the previous stage as it is when the first half-rate clock signal is at “H” level. When the first half rate clock signal is at “L” level, the data output at the immediately preceding “H” level is held.

  The DFFs 5-3, 5-5, 5-7, 5-9, 5-11, 5-13, and 5-17 of the second feedback loop are second different in phase by 180 degrees from the first half-rate clock signal. At the rise of the half-rate clock signal, the output bit of the preceding DFF is retimed for identification and reproduction, and the bit is held for the period of 2 × T1 of the second half-rate clock signal. The master latch circuit 9-15-1 in the DFF 5-15 of the second feedback loop outputs the output of the previous DFF 5-13 to the subsequent stage as it is when the first half-rate clock signal is at the “H” level. When the first half-rate clock signal is at “L” level, the data output at the previous “H” level is held. The slave latch circuit 9-15-2 in the DFF 5-15 of the second feedback loop uses the output of the master latch circuit 9-15-1 at the previous stage as it is when the second half-rate clock signal is at “H” level. When the second half-rate clock signal is “L” level, the data output at the previous “H” level is held.

The MUX 4 captures and outputs the output of the XOR circuit 7-1 of the first feedback loop at the rising edge of the first half-rate clock signal, and outputs the second feedback loop at the rising edge of the second half-rate clock signal. The output of the XOR circuit 7-2 is taken in and output. Thus, the MUX 4 multiplexes the outputs of the XOR circuits 7-1 and 7-2 by alternately taking and outputting the outputs of the XOR circuits 7-1 and 7-2. Therefore, the output signal of MUX4 is converted to the full rate.
As a result, the circuit of FIG. 21 operates at the timing as shown in FIG. According to FIG. 23, it can be seen that 2 ¹⁷ -1 PRBS signals can be generated in the DFF 5-1.

FIG. 24 is a block diagram showing another specific example of the PRBS generator of the present embodiment, and is a block diagram showing a circuit configuration of a 2 ²³ -1 PRBS generator using a half-rate clock signal. FIG. 24 shows an example when N = 23 and K = 18. The PRBS generator of FIG. 24 has a configuration using two feedback loops that operate with a half-rate clock signal, and the operation thereof is the same as the circuit configuration of FIG. 21, and thus detailed description of the operation is omitted.
As described in the first embodiment, when N is an odd number, it is necessary to arrange DFF5-1 in the subsequent stage of MUX4. When N is an even number, DFF5-1 is arranged. There is no need.

[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described. FIG. 25 is a block diagram showing a configuration of a PRBS generator according to the fourth embodiment of the present invention. This embodiment shows another configuration example of the 2 ^N −1 PRBS generator described in the third embodiment. As in the third embodiment, N is a natural number of 3 or more, K is a natural number of 2 or more smaller than N, and NK is an odd number.

The operations of CBUF1, clock distribution circuit 2, frequency multiplier 3, MUX4, DFF5-1, and OBUF6 are as described in the third embodiment.
The difference between this embodiment and the third embodiment is the configuration of each feedback loop, and the arrangement of the XOR circuit 7 is different in this embodiment. In the third embodiment, the XOR circuit 7 is arranged at the output part of each feedback loop. However, since the XOR circuit 7 is not controlled by the clock signal, the output waveform quality is inferior to the output of the DFF. . Since the DFF operates in synchronization with the clock signal, the jitter characteristic and the fluctuation amount of the signal in the time axis direction are usually small. Since the output signal of each feedback loop is multiplexed by the MUX 4 at the next stage, good waveform quality is required.

  Therefore, in the present embodiment, this problem is solved by arranging H DFFs 5-l and 5-o in the subsequent stage of the XOR circuits 7-1 and 7-2, respectively. The total sum of DFFs to be arranged in the feedback loop is determined by the previous circuit configuration described in the third embodiment. Here, the value of H must be an integer in the range of 0 to K / 2. Considering the demultiplexer operation at the first DFF in the feedback loop and the waveform quality input to the MUX 4, it is desirable to arrange the DFFs to be the same number before and after the XOR circuits 7-1 and 7-2. .

  The first feedback loop consists of Int [(K-1) / 2] -H DFF5-j, 1 DFF5- (KH) and Int [(N-K) / 2] DFF5- k, one XOR circuit 7-1 and H DFF5-1. The DFF5- (KH) is composed of a master latch circuit 9- (KH) -1 and a slave latch circuit 9- (KH) -2.

  The second feedback loop consists of Int [(K-1) / 2] -H DFF5-m, 1 DFF5- (K-H + 1) and Int [(N-K) / 2] DFF5-. n, one XOR circuit 7-2, and H DFF5-o. The DFF5- (K-H + 1) is composed of a master latch circuit 9- (K-H + 1) -1 and a slave latch circuit 9- (K-H + 1) -2.

  In the example of FIG. 25, the output of DFF5-1 is input to the first stage DFF5-j and the first stage DFF5-m. The DFFs 5-j and 5-k of the first feedback loop recognize and reproduce the output bit of the preceding DFF by retiming the output bit of the preceding DFF at the rising edge of the first half-rate clock signal output from the clock distribution circuit 2. Bits are held for a period of 2 × T1 of the half rate clock signal. Master latch circuit 9- (KH) -1 in DFF5- (KH) in the first feedback loop is 180 degrees out of phase with the first half-rate clock signal output from clock distribution circuit 2. When the second half-rate clock signal is at “H” level, the output of the preceding DFF5-j is output as it is to the subsequent stage, and when the second half-rate clock signal is at “L” level, the output of the immediately preceding “H” level is output. Holds the data output when. The slave latch circuit 9- (KH) -2 in the DFF5- (KH) of the first feedback loop is the master latch circuit 9 in the previous stage when the first half-rate clock signal is at “H” level. The output of − (K−H) −1 is output to the subsequent stage as it is, and when the first half-rate clock signal is at “L” level, the data output at the previous “H” level is held.

  The DFFs 5-m and 5-n in the second feedback loop re-identify and reproduce the output bit of the preceding DFF at the rising edge of the second half-rate clock signal, and the period 2 of the second half-rate clock signal. X Hold the bit for T1. The master latch circuit 9- (K-H + 1) -1 in the DFF5- (K-H + 1) of the second feedback loop is connected to the DFF5-m of the preceding stage when the first half-rate clock signal is at "H" level. The output is output to the subsequent stage as it is, and when the first half-rate clock signal is at “L” level, the data output at the previous “H” level is held. The slave latch circuit 9- (K−H + 1) -2 in the DFF5- (K−H + 1) in the second feedback loop is the master latch circuit 9 in the previous stage when the second half-rate clock signal is “H” level. The output of − (K−H + 1) −1 is output to the subsequent stage as it is, and when the second half rate clock signal is at “L” level, the data output at the previous “H” level is held.

  The XOR circuit 7-1 in the first feedback loop includes the output of the DFF5-k in the first feedback loop and Int [(K-1) / 2] -H DFF5- in the second feedback loop. An exclusive OR operation with the output of the master latch circuit 9- (K−H + 1) −1 of DFF5− (K−H + 1) arranged at the next stage of m is performed. On the other hand, the XOR circuit 7-2 in the second feedback loop includes the output of the DFF5-n in the second feedback loop and Int [(K-1) / 2] -H pieces in the first feedback loop. An exclusive OR operation is performed on the output of the master latch circuit 9- (KH) -1 of DFF5- (KH) arranged at the next stage of DFF5-j.

  The DFF 5-1 in the first feedback loop re-identifies and reproduces the output bit of the XOR circuit 7-1 in the preceding stage at the rising edge of the first half-rate clock signal, and the period 2 of the first half-rate clock signal. X Hold the bit for T1. The DFF5-o of the second feedback loop re-identifies and reproduces the output bit of the preceding XOR circuit 7-2 at the rising edge of the second half-rate clock signal, and the period 2 of the second half-rate clock signal. X Hold the bit for T1.

  The MUX 4 captures and outputs the output of the DFF 5-1 at the final stage of the first feedback loop at the rising edge of the first half-rate clock signal, and outputs the second feedback loop at the rising edge of the second half-rate clock signal. The output of DFF5-o at the final stage is taken in and output. Thus, the MUX 4 multiplexes the outputs of the DFFs 5-l and 5-o by alternately taking and outputting the outputs of the DFFs 5-l and 5-o. Therefore, the output signal of MUX4 is converted to the full rate.

  According to the present embodiment, since the inside of the feedback loop operates at a half rate similarly to the circuit of the third embodiment, it has the same effect that the operating speed margin can be widened.

  The present invention can be applied to a technique for generating a pseudo random bit string.

  DESCRIPTION OF SYMBOLS 1 ... Clock buffer, 2 ... Clock distribution circuit, 3 ... Frequency multiplier, 4 ... Multiplexer, 5 ... Delay flip-flop, 6 ... Output buffer, 7 ... Exclusive OR circuit, 8 ... Feedback loop, 9 ... Latch circuit.

Claims (6)

The number of first delay flip-flops corresponding to the integer part of K / (2V) and the number corresponding to the integer part of (N−K) / (2V) (N is a natural number of 3 or more, and K is smaller than N 2 2V feedback loops each including a second delay flip-flop, each of which is a natural number, NK is an even number, and V is a natural number up to a number given by (N−K) / 2.
A clock distribution circuit for supplying 2V first clock signals whose phases are shifted by 360 degrees / (2V) to the first and second delay flip-flops of the corresponding feedback loop;
A multiplexer for multiplexing the outputs of the 2V feedback loops;
The output signal of the multiplexer is discriminated and reproduced by a second clock signal having a frequency 2V times that of the first clock signal, and the output signal obtained by the discriminating reproduction is used as the first delay flip-flop in the first stage of each feedback loop. A third delay flip-flop input to the
Each feedback loop
A number of cascaded first delay flip-flops corresponding to an integer part of K / (2V) for identifying and reproducing an input signal at a predetermined timing of a first clock signal corresponding to the own loop;
Using the output of the first delay flip-flop of the own loop as an input, the input signal is identified and reproduced at a predetermined timing of the first clock signal corresponding to the own loop, and the integer part of (NK) / (2V) A corresponding number of cascaded second delay flip-flops;
Performs an exclusive OR operation on the signal passing through the first delay flip-flop of the own loop and the signal passed through the second delay flip-flop of the own loop, and outputs the result of the exclusive OR operation to the multiplexer. And an exclusive OR circuit that
A pseudo-random bit string generator which outputs a bit string having a bit string length of 2 ^N -1 from the third delay flip-flop. The number of first delay flip-flops obtained by subtracting H from the number corresponding to the integer part of K / (2V), and the number of second delay flip-flops corresponding to the integer part of (N−K) / (2V) H (N is a natural number of 3 or more, K is a natural number of 2 or more smaller than N, NK is an even number, V is a natural number up to the number given by (N−K) / 2, and H is from 0 2V feedback loops, each including a third delay flip-flop in a range of K / (2V)
A clock distribution circuit for supplying 2V first clock signals whose phases are shifted by 360 degrees / (2V) to the first, second and third delay flip-flops of the corresponding feedback loop;
A multiplexer for multiplexing the outputs of the 2V feedback loops;
The output signal of the multiplexer is discriminated and reproduced by a second clock signal having a frequency 2V times that of the first clock signal, and the output signal obtained by the discriminating reproduction is used as the first delay flip-flop in the first stage of each feedback loop. And a fourth delay flip-flop input to the
Each feedback loop
The number of cascaded first delays obtained by subtracting H from the number corresponding to the integer part of K / (2V) for identifying and reproducing the input signal at a predetermined timing of the first clock signal corresponding to the own loop Flip-flops,
Using the output of the first delay flip-flop of the own loop as an input, the input signal is identified and reproduced at a predetermined timing of the first clock signal corresponding to the own loop, and the integer part of (NK) / (2V) A corresponding number of cascaded second delay flip-flops;
An exclusive OR circuit that performs an exclusive OR operation on the signal that has passed through the first delay flip-flop of the own loop and the signal that has passed through the second delay flip-flop of the own loop;
The output of the exclusive OR circuit of the own loop is input, the input signal is identified and reproduced at a predetermined timing of the first clock signal corresponding to the own loop, and is output to the multiplexer. A third delay flip-flop,
A pseudo random bit string generator which outputs a bit string having a bit string length of 2 ^N -1 from the fourth delay flip-flop. The pseudo-random bit string generator according to claim 1 or 2,
The pseudo-random bit string generator further includes a frequency multiplier that generates the second clock signal by multiplying the frequency of the first clock signal by 2V. The number of first delay flip-flops corresponding to the integer part of (K-1) / 2, one second delay flip-flop, and the number corresponding to the integer part of (NK) / 2 (N is 3 Two feedback loops each including a third delay flip-flop of each of the above natural numbers, K is a natural number of 2 or more smaller than N, and NK is an odd number),
A clock distribution circuit for supplying two first clock signals whose phases are shifted by 180 degrees to the first, second and third delay flip-flops of the corresponding feedback loop;
A multiplexer for multiplexing the outputs of the two feedback loops;
The output signal of the multiplexer is discriminated and reproduced by a second clock signal having a frequency twice that of the first clock signal, and the output signal obtained by the discriminating reproduction is used as the first delay flip-flop in the first stage of each feedback loop. And a fourth delay flip-flop input to the
Each feedback loop
A number of cascaded first delay flip-flops corresponding to an integer part of (K-1) / 2, for identifying and reproducing an input signal at a predetermined timing of a first clock signal corresponding to the own loop;
One said second delay flip-flop which receives the output of the first delay flip-flop of its own loop as input and identifies and reproduces the input signal at a predetermined timing of the first clock signal corresponding to its own loop and another loop And
The output of the second delay flip-flop of the own loop is input, and the input signal is identified and reproduced at a predetermined timing of the first clock signal corresponding to the own loop, which corresponds to an integer part of (NK) / 2. A number of cascaded third delay flip-flops;
An exclusive OR operation is performed between the signal passing through the third delay flip-flop of its own loop and the signal passing through the master latch circuit in the second delay flip-flop of another loop, and this exclusive OR operation is performed. An exclusive OR circuit that outputs a result to the multiplexer,
The second delay flip-flop of one loop is
A master latch circuit that receives the output of the first delay flip-flop of its own loop and operates with a first clock signal corresponding to another loop;
An output of the master latch circuit of the own loop is input, and a slave latch circuit that operates with a first clock signal corresponding to the own loop is configured.
The second delay flip-flop of the other loop is
A master latch circuit that receives the output of the first delay flip-flop of its own loop and operates with a first clock signal corresponding to its own loop;
It is composed of a slave latch circuit that receives the output of the master latch circuit of its own loop and operates with a first clock signal corresponding to another loop,
A pseudo random bit string generator which outputs a bit string having a bit string length of 2 ^N -1 from the fourth delay flip-flop. Corresponds to the number of first delay flip-flops obtained by subtracting H from the number corresponding to the integer part of (K-1) / 2, one second delay flip-flop, and the integer part of (NK) / 2. The number of third delay flip-flops and H (N is a natural number of 3 or more, K is a natural number of 2 or more smaller than N, NK is an odd number, and H is a natural number in the range of 0 to K / 2). Two feedback loops including a fourth delay flip-flop per loop;
A clock distribution circuit for supplying two first clock signals whose phases are shifted by 180 degrees to the first, second, third, and fourth delay flip-flops of the corresponding feedback loop;
A multiplexer for multiplexing the outputs of the two feedback loops;
The output signal of the multiplexer is discriminated and reproduced by a second clock signal having a frequency twice that of the first clock signal, and the output signal obtained by the discriminating reproduction is used as the first delay flip-flop in the first stage of each feedback loop. A fifth delay flip-flop that inputs to the
Each feedback loop
The input signal is identified and reproduced at a predetermined timing of the first clock signal corresponding to the own loop, and the number of the first cascade-connected numbers obtained by subtracting H from the number corresponding to the integer part of (K-1) / 2. Delay flip-flops,
One said second delay flip-flop which receives the output of the first delay flip-flop of its own loop as input and identifies and reproduces the input signal at a predetermined timing of the first clock signal corresponding to its own loop and another loop And
The output of the second delay flip-flop of the own loop is input, and the input signal is identified and reproduced at a predetermined timing of the first clock signal corresponding to the own loop, which corresponds to an integer part of (NK) / 2. A number of cascaded third delay flip-flops;
An exclusive OR circuit that performs an exclusive OR operation between a signal that has passed through the third delay flip-flop of its own loop and a signal that has passed through the master latch circuit in the second delay flip-flop of another loop;
The output of the exclusive OR circuit of the own loop is input, the input signal is identified and reproduced at a predetermined timing of the first clock signal corresponding to the own loop, and is output to the multiplexer. A fourth delay flip-flop,
The second delay flip-flop of one loop is
A master latch circuit that receives the output of the first delay flip-flop of its own loop and operates with a first clock signal corresponding to another loop;
An output of the master latch circuit of the own loop is input, and a slave latch circuit that operates with a first clock signal corresponding to the own loop is configured.
The second delay flip-flop of the other loop is
A master latch circuit that receives the output of the first delay flip-flop of its own loop and operates with a first clock signal corresponding to its own loop;
It is composed of a slave latch circuit that receives the output of the master latch circuit of its own loop and operates with a first clock signal corresponding to another loop,
A pseudo-random bit string generator which outputs a bit string having a bit string length of 2 ^N -1 from the fifth delay flip-flop. The pseudo-random bit string generator according to claim 4 or 5,
The pseudo random bit string generator further comprises a frequency multiplier for generating the second clock signal by doubling the frequency of the first clock signal.

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