JPH05142302A - Sampling clock supplier of digital/analog mixed lsi tester - Google Patents

Abstract

PURPOSE:To provide a sampling clock supplier for controlling start timing at good reproducibility. CONSTITUTION:A clock part C for supplying an original oscillation pulse P from an original pulse oscillator G is provided on both of a plurality of an arbitrary waveform generator W and a plurality of waveform digitizer D of a sampling clock supplier of a digital/analog mixed LSI tester. The clock part C is composed of a start controller for gating the original oscillation pulse P given from the original pulse oscillator G by a trigger signal, and of a frequency divider for dividing the output of the start controller into the required number of sampling clocks.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sampling clock supply device for a digital / analog mixed LSI test device, and more particularly to operating a plurality of arbitrary waveform generators and a plurality of waveform digitizers by different asynchronous sampling clocks. Sampling clock starter for digital / analog mixed LSI test equipment
The present invention relates to a sampling clock supply device that controls timing or trigger timing with good reproducibility.

[0002]

2. Description of the Related Art A conventional example of a sampling clock supply device for a digital / analog mixed LSI test device will be described with reference to FIG. In FIG. 1, T is a mixed digital / analog LSI test apparatus, which is provided with a plurality of arbitrary waveform generators 7 and 8 and a plurality of waveform digitizers 9 and 10. C is a sampling clock supply device, which includes an original pulse oscillator 1 and frequency dividers 3 and 4 thereof, and an original pulse oscillator 2 and frequency dividers 5 and 6 thereof. The arbitrary waveform generator 7 is connected to the original pulse oscillator 1 via the frequency divider 3, the arbitrary waveform generator 2 is connected to the original pulse oscillator 1 via the frequency divider 4, and the waveform digitizer 9 is used for frequency division. It is connected to the original pulse oscillator 2 via the frequency divider 5, and the waveform digitizer 10 is connected to the original pulse oscillator 2 via the frequency divider 6. Multiple arbitrary waveform generators 7, 8
The plurality of waveform digitizers 9 and 10 are supplied with the sampling clocks, which are frequency-divided separately as described above.

Here, referring to FIG. 2A, the problem is that when the waveform digitizer 1 receives a trigger pulse, the waveform digitizer 9 has a sampling clock * 1.
It is uncertain whether to start with or with the sampling clock * 2. After all, the start timing is uncertain for one clock. Large sampling clock frequency Figure 2
In the case of (a), the time difference for one clock is small and the problem is small. However, in the case where the sampling clock frequency is smaller as shown in FIG. 2 (b), the time difference for one clock becomes large and this is ignored. You can't do it. That is, the reproducibility of the measured data deteriorates because the waveform digitizer supplied with the sampling clock having a small clock frequency has a large error in the start timing.

[0004]

SUMMARY OF THE INVENTION The present invention is intended to provide a sampling clock supply apparatus for a digital / analog mixed LSI test apparatus which solves the above problems.

[0005]

In a sampling clock supply device of a digital / analog mixed LSI test device, a clock in which an original oscillation pulse is supplied from an original pulse oscillator to each of a plurality of arbitrary waveform generators and a plurality of waveform digitizers. The clock section comprises a start controller that gates the original oscillation pulse supplied from the original pulse oscillator by a trigger signal, and a divider that divides the output of the start controller into the required sampling clock. And

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described with reference to FIG. FIG. 3 (a) is a diagram showing an outline of a sampling clock supply device of a digital / analog mixed LSI test device according to the present invention, wherein an original pulse oscillator G is provided for each of a plurality of arbitrary waveform generators W and a plurality of waveform digitizers D.
The clock section C to which the original oscillation pulse P is supplied from is provided.

FIG. 3B is a diagram showing the configuration of each clock section C. The start controller 11 that gates the original oscillation pulse P supplied from the original pulse oscillator G by a trigger signal and the outputs of the start controller 11 Is divided into a necessary sampling clock. The step-down rate of these frequency dividers 12 is set to a predetermined value corresponding to each arbitrary waveform generator W and waveform digitizer D.

FIG. 3 (c) is a timing chart when starting each arbitrary waveform generator W and waveform digitizer D, and FIG. 3 (d) is a partially enlarged view thereof. That is, the original oscillation pulse P supplied to the start controller 11 is gated here by the trigger signal and output to the frequency divider 12. The above is a description of the clock section C provided in each of the arbitrary waveform generator W and the waveform digitizer D. As shown in FIG. 4, each clock section C is used as a clock source unit at one location. You can also focus on.

[0009]

The start of the output to the frequency divider 12 means the start of each arbitrary waveform generator W and the waveform digitizer D, and this start is also started by the sampling clock * 1 as in the conventional example, or There is a trigger error as to whether to start with the sampling clock * 2. However, this trigger error corresponds to one cycle of the constant oscillation pulse P which is always constant regardless of the sampling clock of any arbitrary waveform generator W and waveform digitizer D, and this is usually a pole. It is a short time. The influence of the trigger error in this extremely short time on the reproducibility of the measured data is hardly considered.

[Brief description of drawings]

FIG. 1 is a diagram showing a conventional example of a sampling clock supply device of a digital / analog mixed LSI test device.

FIG. 2 is a timing chart when starting an arbitrary waveform generator and a waveform digitizer, (a) showing a case where a sampling clock frequency is high,
FIG. 6B is a diagram showing a case where the sampling clock frequency is small.

FIG. 3 is a digital / analog mixed LS according to the present invention.
3A and 3B are diagrams illustrating a sampling clock supply device of the I test apparatus, FIG. 1A is a diagram showing an outline thereof, FIG. 1B is a diagram showing the configuration of each clock unit, and FIG. 2C is an arbitrary waveform generator and a waveform digitizer. Timing when starting
The chart and (d) are partially enlarged views.

FIG. 4 is a diagram showing another embodiment of the present invention.

[Explanation of symbols]

 W Arbitrary waveform generator D Waveform digitizer G Original pulse oscillator C Clock section P Original oscillation pulse 11 Start controller 12 Frequency divider

Claims (1)

[Claims] 1. A plurality of arbitrary waveform generators and a plurality of waveform digitizers are each provided with a clock unit to which an original oscillation pulse is supplied from an original pulse oscillator, and the clock unit supplies the original oscillation pulse supplied from the original pulse oscillator. Sampling clock supply for digital / analog mixed LSI test equipment characterized by comprising a start controller gated by a trigger signal and a frequency divider for dividing the output of the start controller into a required sampling clock apparatus.