JP3049127B2 - Calibration method for variable delay circuit, timing signal generator, and semiconductor test apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing generator suitable for an electronic measuring device such as a semiconductor test device.

[0002]

2. Description of the Related Art In a semiconductor test apparatus, improvement in time accuracy is required with the recent increase in speed of a semiconductor integrated circuit. In order to improve the time accuracy of the semiconductor test device, it is necessary to calibrate a variable delay circuit to be mounted.

[0003] As a method of calibrating such a variable delay circuit, "Proceeding of IEE International Test Conference (September 1988)"
Pages 108 to 113 (Proc. IEEE In
tl. , P108-113, Sep. 1988)] is known.

[0004] This technique will be described below.

FIG. 11 shows the configuration of a semiconductor test apparatus according to the prior art.

As shown in the figure, a conventional semiconductor test apparatus includes a test cycle generation circuit (PG) 50 and a timing generator (TG) 5 having a variable delay circuit to be calibrated.
1, waveform generation circuit (FMT) 8, driver (DRV) 3
0, analog comparator (CMP) 31, controller (PC) 52, reference timing generator (REF.T)
G) 53, standard comparator (S) 54, counter (COUN)
T) 55, and a broadband selector (SW) 56.

The test cycle generation circuit 50 generates a test cycle, generates a desired delay time by a variable delay circuit inside the timing generator 51, and performs the test through the waveform generation circuit 8 and the driver 30. A waveform 130 is generated. The test waveform 130 is the analog comparator 3
The response result from the device under test 32 is verified in the controller 52 via the device 1.

The calibration of the variable delay circuit in the timing generator 51 is performed by using a test waveform 130 whose timing is controlled by the timing generator 51 and a reference timing generator 53.
And the reference timing signal 153 from the standard comparator 54.
And the counter 55 is used to process the comparison result. The test waveform 130 is
The signal is supplied to the standard comparator 54 via the wideband selector 56. The reference for calibration of the time resolution of the variable delay circuit is a high-precision airline used inside the reference timing generator 53.

[0009]

The semiconductor elements constituting the variable delay circuit are easily affected by manufacturing variations, ambient temperature, power supply voltage, and the like, and it is essential to calibrate the time resolution of the variable delay circuit. However, when the number of pins of a semiconductor integrated circuit is increased in recent years, an increase in the time required for calibrating a variable delay circuit is unavoidable in the semiconductor test apparatus according to the related art.

If a high-precision air line or the like is used as a time reference for calibration, the size of the apparatus is increased, and the time required for the control is increased because the control takes time.

This tendency becomes conspicuous as the speed of the semiconductor test apparatus increases, and becomes a factor that hinders the increase in speed.

Accordingly, the present invention provides a variable delay circuit with high time accuracy and high-speed calibration with only a small-scale additional circuit.
The purpose is to reduce the size.

[0013]

In order to achieve the above object, the present invention provides a reference clock generator capable of controlling the cycle of an output signal with high precision, a predetermined repetition cycle and a coarse delay time. A coarse timing signal generation circuit for generating a fine delay time of the timing signal, and a variable delay circuit for finely controlling the timing signal in accordance with the time data set by the fine delay register. And a timing generator comprising: a phase comparator for comparing the phases of the outputs of the plurality of variable delay circuits; and a memory for storing calibration data.

[0014]

According to the method of calibrating a variable delay circuit according to the present invention,
The time reference is the period of the reference clock. Since the reference clock can be constituted by a frequency synthesizer or the like whose cycle can be controlled with high accuracy to the same level as a crystal oscillator, calibration can be performed with high accuracy.

Further, the phase comparator required for the method of calibrating the variable delay circuit according to the present invention may have a simple configuration for judging the delay / lead of the phase.
It can be easily provided inside a semiconductor integrated circuit on which a variable delay circuit is mounted. As a result, since the circuit operates near the variable delay circuit to be calibrated, calibration can be performed without being affected by disturbance due to wiring.

Further, by providing the phase comparator inside a semiconductor integrated circuit on which a variable delay circuit is mounted, the size of the device can be reduced.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a first embodiment showing a method of calibrating a variable delay circuit according to the present invention will be described with reference to FIGS. FIG.
FIG. 9 shows a configuration of a timing generator to which the calibration method according to the present embodiment is applied.

As shown, the timing generator in the present embodiment is divided into a calibration target timing generator 3 including a variable delay circuit 12 to be calibrated and a timing generator 4 that operates auxiliary during calibration. I have. The timing generators 3 and 4 include a reference clock generator 1 for generating a reference clock 101, a cycle counter 2 for controlling a repetition cycle of a timing signal, coarse delay registers 11 and 21,
Coarse delay counters 10 and 20, variable delay circuit 1 to be calibrated
2, a variable delay circuit 22, fine delay registers 13 and 23, a phase comparison circuit 5, a controller 6 for controlling a timing generator, and a memory 7 for storing calibration data.

First, the internal operation of the timing generator 3 will be described. The period counter 2 counts the reference clock 101 and generates a period signal 1 having a period that is an integral multiple of the reference clock period tc.
02 is generated. The coarse delay counter 10 outputs the periodic signal 10
2, the reference clock 101 is counted, and after counting the number of times specified by the coarse delay register 11, the coarse delay signal 110 is output. After passing through the variable delay circuit 12 which is a fine delay circuit, the timing signal 112 is obtained. Is output. The variable delay circuit 12 controls the delay time by a minute time specified by the fine delay register 13.

Similarly, the operation of the timing generator 4 is such that the coarse delay counter 20 starts counting the reference clock 101 by the periodic signal 102, counts the number of times specified by the coarse delay register 21, and then outputs the coarse delay signal 120. Then, after passing through the fine delay circuit 22, it becomes a timing signal 122 and is output. The variable delay circuit 22, which is a fine delay circuit, controls the delay time by a minute time specified by the fine delay register 23.

With reference to FIG. 2, an example of calibration for setting the resolution to Δt in the variable delay circuit 12 will be described. The calibration is performed by searching for a delay setting value 113 for changing the delay time of the variable delay circuit 12 in increments of Δt.

First, the set value N is written in the coarse delay register 11 inside the calibration target timing generator 3, and N− is stored in the register 21 in the other timing generator 4.
Write 1 in advance. Further, the set value of the fine delay register 13 sets the delay amount 0. In the example of FIG.
e = 4 × tc, N = 3. Then, while observing the output 105 of the phase comparator 5, the setting data of the fine delay register 23 is increased so that the phases of the timing signal 112 and the timing signal 122 match. FIG. 2A shows a state in which the phases of the timing signal 112 and the timing signal 122 match, and the variable delay circuit 22 outputs td (=
tc).

Next, when the reference clock period is reduced by Δt, the timing signal 112 advances by Δt with respect to the phase of the timing signal 122. Here, the phase comparator 5
While observing the output 105, the set value of the fine delay register 13 is increased so that the phases of the timing signal 112 and the timing signal 122 match. FIG. 2B shows a state where the phases of the timing signal 112 and the timing signal 122 match (shown by a broken line) . Here, the delay setting value 113
Is a set value for increasing the delay time of the variable delay circuit 12 by Δt.

Hereinafter, the cycle of the reference clock 101 is again denoted by Δ
Increase by t and restore. At this time, the delay setting value 11
3 is the value set immediately before, the phase of the timing signal 122 is advanced from the phase of the timing signal 112.
No. Therefore, the timing signal 112 and the timing signal 1
The set value of the fine delay register 23 is increased again so that the phases of the pulses 22 coincide. Subsequently, the period of the reference clock 101 is reduced by Δt, and the resulting phase difference is set to 0 by increasing the set value of the fine delay register 13 again. By repeating such an operation, it is possible to search for the delay setting value 113 that sequentially changes the delay time of the variable delay circuit 12 in increments of Δt. When the delay set value is stored in the memory 7 and the delay circuit 12 is controlled, the data in the memory 7 is used as a conversion table, and the delay is set in accordance with a predetermined delay amount so that the calibration of the variable delay circuit 12 is performed. Becomes possible.

In FIG. 1, the timing generator 3 to be calibrated and the timing generator 4 which operates auxiliary during calibration have exactly the same circuit configuration.
The same calibration can be performed even if the roles of the variable delay circuit 22 and the variable delay circuit 22 are replaced. That is, the variable delay circuit 12
Can be used as an auxiliary delay circuit to calibrate the variable delay circuit 22. Further, even when there are three or more timing generators, similar calibration can be performed by providing a selector at the input of the phase comparator.

A second embodiment showing a method of calibrating a variable delay circuit according to the present invention will be described below with reference to FIG.

As shown in the figure, a variable delay circuit to which the calibration method according to the present embodiment is applied includes a reference clock generator 1 for generating a reference clock 101, a cycle counter 2 for controlling a repetition cycle of a timing signal, and a coarse delay register. 11,2
1. Coarse delay control comparators 14 and 24, variable delay circuit 12 to be calibrated, variable delay circuit 22, fine delay registers 13 and 23, phase comparison circuit 5, controller 6 for controlling timing generator, and calibration data are stored. It comprises a memory 7.

The internal operation of the timing generator 3 is almost the same as in the first embodiment. First, the cycle counter 2 counts the reference clock 101 and generates a cycle signal 102 having a cycle that is an integral multiple of the reference clock cycle tc. The coarse delay control comparator 14 compares the periodic signal 102 with the coarse delay data 111 output from the coarse delay register 11, and outputs a coarse delay signal 110 at the same timing. Similarly, the coarse delay control comparator 24
And coarse delay data 121 output from the coarse delay register 21
Are compared with each other.
Is output. The variable delay circuit 12 to be calibrated, the variable delay circuit 22, the fine delay registers 13 and 23, the phase comparison circuit 5,
The operations of the controller 6 and the memory 7 are the same as in the first embodiment.

The procedure of calibration according to the present embodiment is the same as that of the first embodiment, and a description thereof will be omitted.

The method of calibrating the variable delay circuit according to the present invention shown in the first and second embodiments can be collectively shown by the configuration shown in FIG. 4 are a reference clock generator 1, a period counter 2, a coarse delay control circuit 15, a variable delay circuit 12 to be calibrated, and a variable delay circuit 2.
2. Fine delay registers 13 and 23, phase comparison circuit 5, controller 6, and memory 7 for storing calibration data. Although the operation principle and the configuration procedure are the same as those described above, the description thereof will be omitted. However, the method of calibrating the variable delay circuit according to the present invention has a function of generating a delay time difference of one cycle of the reference clock in the coarse delay control circuit, This is realized by a variable delay circuit that generates a delay time for one clock cycle.

FIGS. 5 and 6 show a third embodiment showing a method of calibrating a variable delay circuit inside a semiconductor test apparatus according to the present invention.
This will be described with reference to FIG.

As shown in the figure, a semiconductor test apparatus to which the calibration method according to the present embodiment is applied includes a reference clock generator 1 for generating a reference clock 101, a cycle counter 2 for controlling a repetition cycle of a timing signal, and a coarse delay register. 11,
21, coarse delay control comparators 14 and 24, variable delay circuit 12 to be calibrated, variable delay circuit 22, fine delay registers 13 and 23, pattern generator 9 for generating test waveforms,
It comprises a waveform generating circuit 8, a driver 30 for supplying a test waveform 130 to the device under test 32, an analog comparator 31, a controller 6 for controlling a timing generator, and a memory 7 for storing calibration data.

Reference clock generator 1 for generating timing signal 112 and timing signal 122, cycle counter 2, coarse delay registers 11 and 21, coarse delay control comparators 14 and 24, variable delay circuit 12 to be calibrated, variable delay circuit 22 and the operations of the fine delay registers 13 and 23 are the same as in the second embodiment, and will not be described. The waveform generation circuit 8 that generates a test waveform generates a waveform corresponding to the waveform pattern data 109 output from the pattern generator 9 at a timing determined by the timing signal 112. The driver 30 outputs an output signal of the waveform generation circuit 8 as a test waveform 130. The test waveform 130 is applied to the analog comparator 31 and outputs a comparison signal 131 at a timing specified by the timing signal 122.

Hereinafter, a calibration method for setting the resolution of the variable delay circuit 12 to Δt according to the present embodiment will be described with reference to FIG.

First, the pattern generator 9 is set so that a positive pulse is generated from the driver 30 at the timing of the timing signal 112. Then, the set value N is written in the coarse delay register 11 inside the calibration target timing generator 3, and N−1 is written in the other timing generator 4. In the example of FIG. 6, the period rate = 4 ×
tc, N = 3. And the analog comparator 3
1 while increasing the setting data 123 of the fine delay register 23 while observing the output 131 of the analog comparator 31.
Hold the setting data 123 at the point in time when the output level changes from 0 to 1.

At this time, the phase of the test waveform 130 and the phase of the timing signal 122 match. FIG. 6 (a)
FIG. 3B shows an initial state, and FIG. 3B shows a state in which the phases of the test waveform 130 and the timing signal 122 match.

Next, when the reference clock cycle is reduced by Δt, the timing signal 112 advances by Δt with respect to the phase of the timing signal 122. Then, since the test waveform 130 also advances by Δt with respect to the phase of the timing signal 122,
The output 131 of the analog comparator 31 becomes 0. Here, the set value of the fine delay register 13 is increased again so that the phase of the test waveform 130 matches the phase of the timing signal 122. Then, the setting data 113 at the time when the output level of the analog comparator 31 changes from 0 to 1 is held. The delay set value 113 is a set value for increasing the delay time of the variable delay circuit 12 by Δt.

Hereinafter, the cycle of the reference clock 101 is again denoted by Δ
If it is increased by t and returned, and the above procedure is repeated,
It is possible to search for a delay set value 113 that sequentially changes the delay time of the variable delay circuit 12 by Δt. When the delay set value is stored in the memory 7 and the delay circuit 12 is controlled, the data in the memory 7 is used as a conversion table and the delay is set in accordance with a predetermined delay amount. It becomes possible.

A fourth embodiment showing a method of calibrating a variable delay circuit according to the present invention will be described below with reference to FIGS.

As shown in the figure, the timing generator in the present embodiment includes a timing generator 3 to be calibrated including a variable delay circuit 12 to be calibrated, and a timing generator 4 which operates auxiliary during calibration. A reference clock generator 1 for generating a reference clock 101, a period counter 2 for controlling a repetition period of a timing signal, coarse delay registers 11 and 21, a coarse delay control comparator 1
4, 24, the variable delay circuit 12, the variable delay circuit 22, the fine delay registers 13 and 23, the phase comparison circuit 5, the up / down counters 40 and 47, the counter selector 48 for selecting the counter to be counted, the data selector, 4
1. Consists of a controller 6 for controlling the timing generator and a memory 7 for storing calibration data.

Reference clock generator 1, period counter 2, coarse delay registers 11 and 21, coarse delay control comparators 14 and 24, and variable delay circuit 1 to be calibrated for generating timing signal 112 and timing signal 122.
2. The operations of the variable delay circuit 22 and the fine delay registers 13 and 23 are the same as those in the second embodiment, and therefore will not be described.

Referring to FIG. 8, an example of calibration for setting the resolution to Δt in the variable delay circuit 12 will be described. The up / down counters 40 and 47 count up by the phase comparator 5 when they determine that they are “ advanced ”, and count down when they are determined to be “ lagged ”. As a preparation before calibration, the coarse delay register 11 inside the calibration target timing generator 3 stores the set value N
And the other timing generator 4 has N-
1 is written, and the data selectors 41 and 49
Select the b side. The up / down counters 40 and 47 are reset, and the counter selector 48 selects the X side. In the example of FIG. 8, the cycle rate = 4 × tc,
N = 3.

First, while observing the output 105 of the phase comparator 5, data is preset in the counter 47 so that the phases of the timing signal 112 and the timing signal 122 match. FIG. 8A shows a state where the phases of the timing signal 112 and the timing signal 122 match.
The variable delay circuit 22 is delayed by td (= tc).

Therefore, as a first step, the counter selector 48 is switched to select the X side, and the reference clock cycle tc is reduced by Δt. Then the timing signal 11
2 advances by Δt with respect to the phase of the timing signal 122
No reason, the phase comparator 5, it is determined that "advances" of the timing signal 112 side, the up-down counter 40,
Start counting up. Up / down counter 40
Is output to the variable delay circuit 12 via the data selector 41.
, The variable delay circuit 12 keeps increasing the delay time. When the phases of the timing signal 112 and the timing signal 122 become equal, the phase comparator 5 determines that the phases are the same, and stops the operation of the up / down counter 40. At this time, the data held in the up / down counter 40 is a set value for increasing the delay time of the variable delay circuit 12 by Δt. The data of the up / down counter 40 at this time is stored in the memory 7.

FIG. 8B shows an example in which the set value for increasing the delay time of the variable delay circuit 12 by Δt is “4”.

In the second stage, while the data of the counter 40 is held, the counter selector 48 is switched to the Y side, the reference clock cycle is increased by Δt, and returned to tc. Then, since the timing signal 112 is delayed by Δt from the phase of the timing signal 122, the phase comparator 5 determines that the timing signal 112 is “delayed”, and the up / down counter 47 starts counting up. Since the output of the up / down counter 47 is connected to the variable delay circuit 22 via the data selector 49, the variable delay circuit 22
Keeps increasing the delay time. Then, when the phases of the timing signal 122 and the timing signal 112 become equal,
The phase comparator 5 determines that the phases are the same, and stops the counting operation of the up / down counter 47.

As described above, in the first stage, a search for a set value for increasing the delay time of the variable delay circuit 12 by Δt is performed, and in the second stage, the variable delay circuit 22 also searches for Δt.
The timing signal 112 and the timing signal 12
Control is performed so that the two phases coincide.

As the next step, the reference clock 10
If the period of 1 is reduced by Δt and the procedures of the first and second stages are repeated, the delay set value 113 for sequentially changing the delay time of the variable delay circuit 12 in increments of Δt is searched for and stored in the memory 7. Can be. Then, using the setting data stored in the memory 7 as a conversion table and performing a delay setting according to a predetermined delay amount, the variable delay circuit 12 can be calibrated. In this embodiment, the operation of adjusting the phase of the timing signal can be automatically performed by the counter, so that the time required for calibration can be reduced.

FIG. 9 is a supplementary diagram showing the periphery of the phase comparator 5 in FIG. 7 in detail. For convenience, only 40 of the up / down counters 40 and 47 are shown. Actually, the counter selector 48 shown in FIG. 7 is also arranged before the up-down counters 40 and 47 in FIG. 8, and the counters 42, 43, 44 and the comparator 45 can be shared by both up-down counters. The phase comparator 5 outputs a phase comparison result of the timing signal 112 based on the timing signal 122. When the phase comparison result is "advance", the counter 42 counts up, and when the phase comparison result is "lag", the counter 43 counts up. The comparator 45 compares the count results of the counter 42 and the counter 43 to thereby obtain the phase comparator 5.
Determines which of “lead” and “delay” has been output more. Based on this determination result, the up / down counter 40 increases or decreases the set data. As described above, when the phases of the timing signal 112 and the timing signal 122 approach, the phase comparator becomes more susceptible to disturbance, and the count values of the counter 42 and the counter 43 also approach. The counter 44 counts the state in which the phases are approaching each other, and when the number reaches a predetermined value or more (that is, when a predetermined number of coincidence pulses are continuously counted), it is determined that the phase comparison result is equal to or lower than the noise level. , Calibration end signal 14
4 is output. In a usage environment in which the phase comparator may malfunction due to a disturbance due to disturbance, the operation as described above enables operation with noise margin. Further, by controlling the set value of the counter, it is possible to take noise countermeasures according to the noise environment in which the device is used.

In FIG. 7, the timing generator 3 to be calibrated and the timing generator 4 which operates auxiliary during calibration have exactly the same circuit configuration. The same calibration can be performed by replacing. That is, the variable delay circuit 22 can be calibrated using the variable delay circuit 12 as an auxiliary delay circuit. Further, even when there are three or more timing generators, the same calibration can be performed by providing a selector at the input of the phase comparator 5.

Hereinafter, a fifth embodiment of the semiconductor test apparatus according to the present invention will be described with reference to FIG.

As shown, the semiconductor test apparatus according to the present invention comprises a plurality of test waveform generating units 33 for supplying a test waveform to a device under test 32 having a plurality of input / output pins, a reference clock generator 1, and a controller. Consists of six.

The test waveform generation unit 33 includes a cycle counter 2 for controlling a test repetition cycle, a coarse delay register 1
1, 21; coarse delay control comparators 14 and 24; variable delay circuit 12 to be calibrated; variable delay circuit 22; fine delay registers 13 and 23; waveform generation circuit 8; pattern generator 9; driver 30; Phase comparison circuit 5, up / down counter 40, data selector 4
1 and a memory 7 for storing calibration data.

The operation of each part and the procedure of calibration are the same as in the fourth embodiment. The feature of this embodiment is that the plurality of test waveform generation units 33 connected to the pins of the device under test 32 are independent, so that the calibration of the variable delay circuit 12 mounted on each test waveform generation unit 33 is performed by all units. It is possible to do it at the same time. With this feature, the time required for calibration can be reduced.

Further, in this embodiment, a similar result can be obtained by performing a phase comparison using the output of the analog comparator 31 instead of the phase comparator 5. The same is true even if the roles of the variable delay circuit 12 and the variable delay circuit 22 are switched. In the present embodiment, a signal selector is provided at the input of the phase comparator 5 so that 3
Extension is possible up to the case where there are more than two variable delay circuits.

[0056]

As described above, according to the present invention, the delay time resolution of the variable delay circuit mounted on the timing generator and varying the delay time with high resolution is determined with reference to the high-precision reference clock oscillation cycle. By performing the calibration, it is possible to realize high accuracy of a semiconductor test device or the like.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a method of calibrating a variable delay circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the embodiment of FIG.

FIG. 3 is an explanatory diagram of a method of calibrating a variable delay circuit according to a second embodiment of the present invention.

FIG. 4 is an explanatory diagram of a method of calibrating a variable delay circuit, showing the first and second embodiments of the present invention as a whole.

FIG. 5 is a block diagram of a semiconductor test apparatus according to a third embodiment of the present invention.

FIG. 6 is a timing chart showing the operation of the embodiment of FIG.

FIG. 7 is an explanatory diagram of a method of calibrating a variable delay circuit according to a fourth embodiment of the present invention.

FIG. 8 is a timing chart showing the operation of the embodiment of FIG.

FIG. 9 is a supplementary explanatory diagram of the embodiment in FIG. 7;

FIG. 10 is a block diagram of a semiconductor test apparatus according to a fifth embodiment of the present invention.

FIG. 11 is a configuration diagram of a conventional semiconductor test apparatus.

[Explanation of symbols]

1: Reference clock generator, 2: Period counter, 3, 51
… Calibration target generator, 4… Timing generator, 5
... Phase comparator, 6,52 ... Controller, 7 ... Memory,
8 ... waveform generation circuit, 9 ... pattern generator, 10,20 ...
Coarse delay counter, 11,21 ... Coarse delay register, 12,2
2 ... variable delay circuit, 13,23 ... fine delay register, 14,
24: coarse delay control comparator, 15: coarse delay control circuit, 30: driver, 31: analog comparator, 3
2: Device under test, 33: Test waveform generation unit, 40,
47 ... Up / down counter, 41,46 ... Data selector, 42,43,44 ... Counter, 45 ... Comparator, 48 ...
Counter selector, 50: Test cycle generation circuit, 53: Reference timing generator, 54: Standard comparator, 55: Counter, 56: Broadband selector.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-47573 (JP, A) JP-A-62-12880 (JP, A) JP-A-3-94181 (JP, A) JP-A-3-3 130678 (JP, A) JP-A-5-34412 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G01R 31/28 G01R 35/00

Claims (7)

(57) [Claims] A predetermined period of time from a reference clock having a predetermined period;
A timing signal generator for generating a timing signal,
Variable delay that can control delay amount by control data
A method for calibrating an extension circuit, comprising : (a) a phase difference of a unit cycle based on the reference clock;
(B) generating a first and a second coarse delay signal, respectively,
The variable delay circuit to be calibrated and the delay set to zero
And (c) first and second output from both variable delay circuits.
The auxiliary variable delay so that the phase difference of the fine delay signal becomes zero.
(D) Next, the period of the reference clock is set smaller than this period.
Only again time Δt is varied, (e) the first and second fine delay signal thereby caused
Variable delay of the calibration target so that the phase difference of
Controls the amount of delay in the circuit and
Storing that control data, then (f), possible to change the delay amount for both the variable delay circuits
By returning the cycle of the reference clock to the original cycle,
Newly generating a phase difference between the first and second fine delay signals.
Allowed time difference, until the stored (g) a desired number of the control data, the
Repeating steps (c) to (f)
How to configure a variable delay circuit. 2. A method for calibrating a variable delay circuit according to claim 1, wherein
And the variable delay circuit to be calibrated and the
First and second uploaders corresponding to the auxiliary variable delay circuit
Delay amount of one of the variable delay circuits
The phase difference between the first and second fine delay signals
Control the up / down counter so that the value becomes 0
A method for calibrating a variable delay circuit, characterized in that: 3. A semiconductor having a plurality of timing generators.
In the body test apparatus, each of the plurality of timing generators
2. A method for calibrating a variable delay circuit according to claim 1, further comprising:
Method for calibrating a variable delay circuit, characterized by performing the method
Law. 4. A reference clock generator for generating a frequency-variable reference clock; coarse delay means for generating first and second coarse delay signals having a phase difference of a unit period of the reference clock; First and second variable delay circuits for respectively delaying the first and second coarse delay signals of the delay means by a minute variable delay amount, and a phase comparison for comparing phases of output signals of both variable delay circuits Means, a first up / down counter for performing an increase / decrease operation in accordance with an output of the phase comparison means, and generating control data of the first variable delay circuit, and an increase / decrease operation in accordance with an output of the phase comparison means. performed, the second up-down counter for generating control data of the second variable delay circuit, the first or second up the output of said phase comparing means
A timing generator comprising: switching means for switching and inputting to a down counter; and storage means for storing an output of the first up / down counter as calibration data. 5. The timing generator according to claim 4, wherein the timing generator is configured as a semiconductor circuit in a one-chip semiconductor integrated circuit device. 6. A test clock generator for generating a frequency-variable reference clock, and a plurality of test waveform generating units for supplying a test waveform to a test element in correspondence with a pin, wherein the test waveform generating unit comprises: Coarse delay means for generating first and second coarse delay signals having a phase difference of a unit cycle of the reference clock; and finely variable first and second coarse delay signals of the coarse delay means, respectively. First and second variable delay circuits that delay by the delay amount, phase comparison means for comparing the phases of the output signals of both variable delay circuits, and an increase / decrease operation according to the output of the phase comparison means, A first up / down counter for generating control data for the variable delay circuit, and a second up / down counter for performing an increase / decrease operation in accordance with an output of the phase comparison means to generate control data for the second variable delay circuit. Mosquito Printers and the first or second up the output of said phase comparing means
Switching means for switching and inputting to the down counter; and storage means for storing the output of the first up / down counter as calibration data, wherein a plurality of the test waveform generation units are provided corresponding to the pins of the device under test. Characteristic semiconductor test equipment. 7. A reference for generating a variable frequency reference clock.
A first and a second clock generator having a phase difference corresponding to a unit period of the reference clock;
Coarse delay means for generating a first and a second coarse delay signal, and first and second coarse delay signals of the coarse delay means, respectively.
First and second variable delays delayed by a minute variable delay amount
Phase comparison hand comparing the circuit, the phase of the output signals of both the variable delay circuits
And when the cycle of the reference clock is a predetermined cycle,
The second signal is output so that the output of the phase comparing means indicates a phase difference of zero.
Means for setting the control data of the variable delay circuit, and setting the cycle of the reference clock to be longer than the predetermined cycle.
If the output of the phase comparison means is shifted by Δt,
The control data of the first variable delay circuit is set to indicate a phase difference of 0.
Means for setting data, and control data of the first variable delay circuit as calibration data.
And a storage unit for storing the timing.