JPS63148176A - Logic circuit testing device - Google Patents

Abstract

PURPOSE:To operate a logic circuit stably even when the logic circuit operates asynchronously with a testing device by synchronizing the output of a test pattern generating circuit with a clock of the logic circuit. CONSTITUTION:A probe 11 leads out the output of the clock generating circuit 4a of the logic circuit 4. A comparator 13 compares the output of a reference voltage generating circuit 12 with the output of the probe 11. The output of the comparator 13 is supplied to the phase comparing circuit 14a of a phase- locked oscillation circuit 14. The circuit 14 determines the frequency division ratio for the output of a frequency dividing circuit 14d so that the clock frequency led out of the circuit 4a is as high as the output frequency of a voltage- controlled oscillation circuit 14c. Therefore, the circuit 14 operates so that the clock led out of the circuit 4 and the output of the circuit 13d are in phase and have the same frequency. The output of the circuit 14d is sent to a frequency dividing circuit 15, whose output is supplied to the test pattern generating circuit 2 and a data sampling circuit 3. Consequently, a response to the test pattern of the circuit 4 is also synchronized.

Description

Detailed Description of the Invention (a) Technical Field of the Invention The present invention provides a method for generating a test pattern synchronized with a clock that operates the logic circuit when testing the logic circuit by adding a test pattern to the logic circuit. This is about a logic circuit testing device.

(b) Prior Art and Problems When testing a logic circuit, test patterns are added to the logic circuit's human power, and the output response of the logic circuit is analyzed to determine pass/fail.

In the conventional technology, a test pattern created by a pattern generator is added to a logic circuit, but if the logic circuit is operated by a clock within the logic circuit, the test pattern and the logic circuit operate asynchronously.

If the clock in the logic circuit and the test pattern are asynchronous, an unstable pulse output such as a glitch may appear in the logical operation output between the logic signal in the logic circuit and the test pattern.

Therefore, there is a problem that the output data is unstable and has low reproducibility, resulting in a lack of reliability.

Next, FIG. 3 shows a configuration diagram of a conventional logic circuit testing device.

In FIG. 3, 1 is a clock generation circuit, 2 is a test pattern generation circuit, 3 is a data sampling circuit, and 4 is a logic circuit to be tested.

Logic circuit test v2a t OB is clock generation circuit 1
, a test pattern generation circuit 2 and a data sampling circuit 3.

The logic circuit 4 in FIG. 3 is a clock generation circuit 4a.

An example is shown in which the circuit is composed of a flip-flop 4b and a gate circuit 4c.

Flip-flop 4b divides the output of clock generation circuit 4a into 172 frequencies. The gate circuit 4c receives the output of the test pattern generation circuit 2 and the output of the flip-flop 4b as inputs.

Next, FIG. 4 shows a waveform diagram of the third country name part.

FIG. 4(A) shows the output waveform of the clock generation circuit 4a, and FIG. 4(B) shows the output waveform of the flip-flop 4b.

FIG. 4(A) shows the output waveform of the test pattern generation circuit 2, and FIG. 4(A) and FIG. 4(T) are asynchronous.

FIG. 4(1) is the output waveform of the gate circuit 4C, and the fourth
This is an AND output of Figure (a) and Figure 4 (1), but since Figure 4 (1) and Figure 4 (2) are asynchronous, the waveform width in Figure 4 (1) changes depending on the state. .

Therefore, the sampling output of the data sampling circuit 3 becomes inaccurate.

When the logic circuit 4 is tested by the logic circuit testing device ff1OB and the output of the gate circuit 4c is used to test other logic circuits, the circuit may malfunction due to a glitch in the output signal of the gate circuit 4c.

(c) Purpose of the Invention This invention provides a logic circuit testing device that extracts a clock from a logic circuit and generates a test pattern synchronized with the extracted clock when the clock in the logic circuit and the test pattern are asynchronous. The purpose is to provide a solution to the problems of the prior art.

(d) Examples of the invention First, a block diagram of an embodiment according to the present invention is shown in FIG.

In FIG. 1, 11 is a probe, 12 is a reference voltage generation circuit, 1
3 is a comparator, 14 is a phase synchronized oscillation circuit, 15 is a frequency dividing circuit, and the other parts are the same as in FIG.

That is, the logic circuit test bag rH, IOA of FIG. 1 employs clock generation circuits 11 to 15 in place of the clock generation circuit 1 of the logic circuit test apparatus 11B of FIG.

The probe 11 in FIG. 1 is for taking out the output of the clock generation circuit 4a of the logic circuit 4. The probe 11 shown in FIG.

The comparator 13 compares the output of the base*i pressure generating circuit 12 and the probe 11 .

The reference voltage generated by the reference voltage generation circuit 12 determines the voltage threshold of the logic signal, and is used for TTL and CMO5%.
Set the appropriate voltage using a device such as ECL.

The phase synchronized oscillation circuit 14 includes a phase comparator circuit 14a, a low-pass filter 14b, a voltage controlled oscillation circuit 14c, and a frequency dividing circuit 1.
4d, and the output of the comparator 13 enters a phase comparison circuit 14a.

The output of the frequency dividing circuit 14d is connected to the input of the phase comparison circuit 14a for phase comparison with the clock taken out from the clock generation circuit 4a of the logic circuit 4.

The frequency dividing circuit 14d is a clock generating circuit 4a of the logic circuit 4.
Clock frequency and voltage controlled oscillator circuit 1 taken from
Set the frequency division ratio so that the output frequencies of 4c are the same.

Therefore, the phase synchronized oscillation circuit 14 operates so that the clock taken out from the logic circuit 4 and the output of the frequency dividing circuit 14d have the same phase and the same frequency.

For example, when the frequency of the clock taken out from the logic circuit 4 is IMHz, the oscillation frequency of the voltage controlled oscillation circuit 14C is set to about 40 MHz. In this case, frequency divider circuit 1
Set the frequency division ratio of 4d to 1/40.

The output of the frequency dividing circuit 14d enters the frequency dividing circuit 15, and the output of the frequency dividing circuit 15 is supplied to the test pattern generation circuit 2 and the data sampling circuit 3.

The test pattern generating circuit 2 in FIG. 1 generates a test pattern using the output of the frequency dividing circuit 15 as a clock, and applies it to the logic circuit 4.

Since the test pattern generation circuit 2 is synchronized with the clock of the logic circuit 4, the response corresponding to the test butter 7 of the logic circuit 4 is also synchronized.

Next, a waveform diagram of the first ward name section is shown in FIG.

FIG. 2(A) shows a clock waveform of the clock generation circuit 4a, and FIG. 2(B) shows a signal waveform operated by a clock in the logic circuit 4.

Figure 2 (1) shows the waveform obtained by shaping the clock taken out from the logic circuit 4 by the comparator 13.
) is a waveform obtained by dividing the output of the phase synchronized oscillation circuit 14 by the frequency dividing circuit 15.

The frequency dividing circuit 15 is for setting a test rate, and FIG. 2 illustrates a case where the frequency dividing ratio=1.

FIG. 2 (1) is an example of the output waveform of the test pattern generation circuit 2, and FIG. 2 (power) is the output response waveform of the logic circuit 4.

FIG. 2 (g) is data obtained by sampling the waveform of FIG. 2 (o) in FIG. 2 (X), and stable data can be obtained.

In FIG. 2, the data sampling circuit 3 is configured to sample at the falling edge of the output clock of the frequency dividing circuit 15.

(e) Effects of the Invention According to this invention, since the output of the test pattern generation circuit is synchronized with the clock of the logic circuit, the logic circuit can be stabilized even if the logic circuit operates asynchronously with the test equipment. data can be reliably sampled from the response output signal of the logic circuit.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an embodiment according to the present invention, and FIG.
Figure 3 is a configuration diagram of a conventional logic circuit testing device, and Figure 4 is a waveform diagram of the third country name part. 1... Clock generation circuit, 2... Test pattern generation circuit, 3... Data sampling circuit, 4... Logic circuit, 4a...・Clock generation circuit, 4b...Flip-flop N
4 c...Gate circuit, 10A...
Logic circuit test device, 10B...Logic circuit test device, 11...Probe, 12...Reference voltage generation circuit, 13...Comparator, 14.
... Phase synchronized oscillation circuit, 14a ... Phase comparison circuit, 14b ... Low-pass filter, 14c.
...Voltage controlled oscillation circuit, 14d... Frequency dividing circuit, 15... Frequency dividing circuit. Agent Patent Attorney Kinma Omata Figure 1 Figure 2 Figure 3 Logical Residence Figure 4

Claims (1)

[Scope of Claims] 1. A logic circuit testing device that adds the output of a test pattern generation circuit to a logic circuit to be tested and inputs the output of the logic circuit to a data sampling circuit to determine the quality of the logic circuit, comprising: A probe for extracting a circuit clock; a comparator for shaping the waveform of the clock extracted by the probe; a phase-locked oscillator circuit that receives the output of the comparator as an input; and a frequency divider circuit that divides the output of the phase-locked oscillator circuit. A logic circuit testing device comprising: supplying the frequency dividing circuit output to the test pattern generation circuit and the data sampling circuit to extract a test pattern generation circuit output synchronized with a clock extracted from the logic circuit. .