JPH08262082A - Sampling digitizer - Google Patents

Abstract

PURPOSE: To measure easily a jitter being the amount of fluctuation of a phase on a time basis and a frequency component of the jitter by generating a sampling clock of a sampler by using a periodic pulse waveform of a signal to be measured. CONSTITUTION: A waveform shaper 1 is provided in an input part and a signal therefrom is made an input signal of a sampler 2, while a signal from the input part is branched, passed through a PLL circuit 7 and a delay 6 and made a sampling clock of the sampler 2. Besides, it is converted into a digital signal by an A/D converter 3 at each clock of the sampler and outputted to a memory 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sampling digitizer capable of measuring the jitter of a periodic pulse waveform and analyzing the frequency of the jitter.

[0002]

2. Description of the Related Art Jitter measurement by a conventional sampling digitizer will be described with reference to FIGS. As shown in FIG. 9, the conventional sampling digitizer has a sampler 2, an A / D converter 3, a memory 4, and a clock generator 5.

When measuring jitter in a conventional sampling digitizer, as shown in FIG. 9, the output of the periodic pulse generator is input to the DUT of the device under test, and the output of the DUT is connected to input 1. , As the input signal of the sampler 2. Further, the synchronizing signal is obtained from the signal of the periodic pulse generator, and the sampling clock of the sampler 2 is generated from the clock generator 5. As shown in FIG. 10, the timing in the sampler 2 in this case is such that the sampler input signal is sampled by a sampling clock having a slightly different phase, and a sampling waveform of the frequency difference is output. As shown in FIG. 9, the sampled analog data is digitally converted by the A / D converter 3 for each clock, and the output data is stored in the memory 4. As shown in FIG. 11, the obtained data is measured as the amount of time fluctuation on the time axis of the periodic waveform, which is the jitter that is generated by passing through the DUT. can do. In FIG. 11, the rising and falling waveforms are separated and displayed as a plurality of traces for the sake of clarity, but they are usually observed as thick and wide traces.

Here, the DUT has a periodic pulse waveform of D
It is a device under test in which the jitter generated by passing through the UT is measured. As shown in Fig. 12, the sampling digitizer is a waveform digitizer that samples repetitive waveforms of several hundred MHz to several GHz while shifting the phase at a cycle lower than the frequency under test, and AD-converts them while maintaining similarity to the input waveform. (According to the 3rd edition of the dictionary of semiconductor manufacturing equipment published by Nikkan Kogyo Shimbun)

[0005]

As described above, it is possible to measure the jitter, which is the fluctuation amount of the temporal phase of the periodic pulse waveform, but the jitter is the fluctuation amount of time on the time axis. Therefore, there is a problem that the frequency component of the jitter cannot be analyzed. Therefore, the problem to be solved by the present invention is to generate a sampling clock of a sampler by using a periodic pulse waveform of a signal under measurement and convert a jitter, which is a temporal phase variation amount, into a voltage with respect to time. However, the purpose is to simplify the analysis of the frequency component of the jitter.

[0006]

FIG. 1 shows a first embodiment of the present invention.
It shows the solution of. In order to solve the above problems,
In the configuration of the present invention, the waveform shaper 1 is provided in the input section, and the waveform is shaped so that the rising and falling slew rates of the measured periodic pulse waveform connected to the input 2 are constant values. Use as input signal for sampler 2. In addition, a signal having a periodic pulse waveform is branched from the input section to be used as a sampling clock for the sampler 2 through the PLL circuit 7 and the delay 6, and the A / D converter 3 is provided for each clock.
Is converted into digital data and output to the memory 3.

The waveform shaper 1 functions to shape the rising or falling slew rate of the periodic pulse waveform into a constant magnitude. The PLL circuit 7 can output a periodic waveform with little jitter, which is locked to the phase of the averaged period of the input periodic pulse waveform. Fig. 2 is a block diagram of a standard PLL circuit, which uses a phase comparator and a voltage controlled oscillator VCO in combination, and uses a negative feedback loop of integral control type with respect to frequency, and a periodic output synchronized with the average phase of a periodic input wave. It is a structure to get waves.

FIG. 6 shows a second solution according to the present invention. In order to solve the above problems, in the configuration of the present invention, the periodic pulse waveform to be measured connected to the input 2 is
Through the PLL circuit 7 provided in the input section and the waveform shaper 1,
Use as input signal for sampler 2. In addition, the signal of the periodic pulse waveform to be measured is branched at the input section to be used as the sampling clock of the sampler 2 via the 1 / n frequency divider 10 and the delay 6, and A / D for each clock. The converter 3 converts it into digital data and outputs it to the memory 3.

The 1 / n frequency divider 10 has a function of making it possible to measure an input signal having a cycle earlier than that of a sampling clock which can be sampled by the sampler 2. The delay 6 can be adjusted so that the phase of the sampling clock with respect to the input waveform of the sampler 2 falls within the rising or falling range of the input waveform of the sampler 2.

FIG. 8 shows a third solution according to the present invention. In the case of the present solution, the configuration is such that the rising or falling slew rate of the measured periodic pulse waveform is constant and known, and is the same as the case where the waveform shaper 1 of the first solution is not provided. It will be composed. Therefore, in this configuration, the measured periodic pulse waveform connected to the input 2 becomes the input signal of the sampler 2 as it is. Also,
A signal having a periodic waveform is branched from the input section and is used as a sampling clock for the sampler 2 through the PLL circuit 7 and the delay 6, and the A / D converter 3 is provided for each clock.
Is converted into digital data and output to the memory 3.

[0011]

【Example】

(Embodiment 1) Embodiment 1 of the present invention will be described with reference to FIGS.
Will be described with reference to. As shown in FIG. 1, the sampler 2
The A / D converter 3, the memory 4, and the clock generator 5 have the same configuration as that of the sampling digitizer of the prior art.
The circuit 7 and the delay 6 are added. When the switches 8 and 9 are respectively switched to the b side, the measurement is performed by the conventional technique, and the jitter, which is the variation amount of the temporal phase of the periodic pulse waveform connected to the input 1, can be measured.

When the switch 8 and the switch 9 are respectively switched to the side a, the jitter measurement by the configuration of the present invention can be performed. The slew rate of rising or falling of the periodic pulse waveform connected to the input 2 is fixed to a constant value A (V / sec) by the waveform shaper 1 and is used as the input waveform of the sampler 2. On the other hand, when the input periodic pulse waveform is branched and input to the PLL circuit 7, the PLL circuit 7
Gives a periodic pulse waveform with little jitter that is locked at the phase of the average period of the periodic pulse.
Sampling clock waveform.

As shown in FIG. 3, the sampling clock timing is set by the delay 6 so that the sampler input waveform can be sampled within the range of rising or falling. The sampling clock timing is preferably near the center of rising or falling. The set timing does not need to be changed because the phase relationship between the input waveform of the sampler 2 and the sampling clock does not change even if the cycle of the input periodic pulse waveform changes.

The output of the sampler 2 is converted into a digital signal for each clock by the A / D converter 3 and output.
It is stored in the memory 4. The obtained data can be displayed as a voltage variation ΔV (V) with respect to time, as shown in FIG. 4, and thus the phase variation with time of the periodic pulse waveform can be obtained by the following equation. Jitter (sec) = ΔV / A Here, ΔV is the amount of voltage fluctuation with respect to time of the periodic pulse waveform, and A is the slew rate of the waveform shaper 1. Further, the variation amount ΔV of the voltage with respect to time of the periodic pulse waveform can be analyzed as a frequency component of jitter as shown in FIG. 5 by performing a fast Fourier transform.

(Embodiment 2) Regarding Embodiment 2 of the present invention,
This will be described with reference to FIGS. 6 and 7. As shown in FIG. 6, the sampler 2, the A / D converter 3, the memory 4, and the clock generator 5 have the same configuration as that of the sampling digitizer of the prior art.
It has a configuration in which a PLL circuit 7, a delay 6, and a 1 / n frequency divider 10 are added. When the switches 8 and 9 are respectively switched to the b side, the measurement is performed by the conventional technique, and the jitter, which is the variation amount of the temporal phase of the periodic pulse waveform connected to the input 1, can be measured.

When the switch 8 and the switch 9 are respectively switched to the side a, the jitter measurement by the configuration of the present invention can be performed. When the measured periodic pulse waveform connected to the input 2 is input to the PLL circuit, the PLL circuit locks the periodic pulse waveform at the average period phase of the periodic pulse waveform into the waveform shaper 1 with less jitter. Is output. The periodic pulse waveform becomes the input waveform of the sampler 2 by shaping the rising or falling slew rate into a constant magnitude A by a waveform shaper. On the other hand, the sampling pulse of the sampler 2 is obtained via the 1 / n frequency divider 10 and the delay 6 by branching the input periodic pulse waveform.

As shown in FIG. 7, the sampling clock timing is set by the delay 6 so that the sampler input waveform can be sampled within the range of rising or falling. The sampling clock timing is preferably near the center of rising or falling. The set timing does not need to be changed because the phase relationship does not change even if the cycle of the input periodic pulse waveform changes.
In principle, the second embodiment and the first embodiment only change the input signal of the sampler 2 and the sampling clock. Therefore, the amount of fluctuation in the temporal phase of the periodic pulse waveform shown in FIG. Further, it is possible to analyze the frequency component of the jitter as shown in FIG.

(Embodiment 3) Regarding Embodiment 3 of the present invention,
This will be described with reference to FIGS. 8, 3, 4, and 5. As shown in FIG. 8, this embodiment is the same as the embodiment 1 except that the waveform shaper 1 is not provided. When the switches 8 and 9 are respectively switched to the b side, the measurement is performed by the conventional technique, and the jitter, which is the variation amount of the temporal phase of the periodic pulse waveform connected to the input 1, can be measured. When the switch 8 and the switch 9 are respectively switched to the a side, the jitter measurement by the configuration of the present invention can be performed.

The first and second embodiments are functions required when the rising or falling of the measured periodic pulse waveform is unknown, and the slew rate of the rising or falling of the periodic pulse waveform is known. For example, it can be implemented without a waveform shaper as shown in FIG. The input signal of the sampler 2 in this case and the timing of the sampling clock are as shown in FIG. 3 as in the case of the first embodiment. Therefore, the jitter, which is the amount of temporal phase variation of the periodic pulse waveform shown in FIG. 4, is required. Further, as shown in FIG. 5, the frequency component of the jitter can be analyzed.

[0020]

Since the present invention is constructed as described above, it has the following effects. Since the sampler input signal and the sampling clock are the same signal, it is not necessary to input the clock generator signal to the device under test. That is, the jitter can be measured only by the received periodic pulse signal. In addition, the fluctuation amount ΔV of the voltage of the periodic pulse waveform with respect to time
Since the jitter can be obtained as, the jitter can be analyzed as the frequency component of the jitter by performing the fast Fourier transform.

[Brief description of drawings]

FIG. 1 is a configuration diagram (block) of a sampling digitizer according to a first exemplary embodiment of the present invention.

FIG. 2 is a configuration diagram of a standard PLL circuit.

FIG. 3 is a diagram showing timings of an input signal and a sampling clock of the sampler according to the first embodiment of the present invention.

FIG. 4 is a measurement diagram of jitter according to the present invention.

FIG. 5 is a characteristic diagram obtained by frequency analysis of jitter according to the present invention.

FIG. 6 is a configuration diagram (block) of a sampling digitizer according to a second exemplary embodiment of the present invention.

FIG. 7 is a diagram showing timings of an input signal and a sampling clock of the sampler according to the second embodiment of the present invention.

FIG. 8 is a configuration diagram (block) of a sampling digitizer according to a third embodiment of the present invention.

FIG. 9 is a configuration diagram (block) of jitter measurement of a conventional sampling digitizer.

FIG. 10 is a diagram showing timings of an input signal and a sampling clock of a prior art sampler.

FIG. 11 is an observed waveform of jitter by a conventional sampling digitizer.

FIG. 12 is a diagram showing the principle of sampling by a conventional sampling digitizer.

[Explanation of symbols]

 1 waveform shaper 2 sampler 3 A / D converter 4 memory 5 clock generator 6 delay 7 PLL circuit 8 and 9 switch 10 1 / n frequency divider

Claims (3)

[Claims] 1. A sampling digitizer having a sampler (2), an A / D converter (3), a memory (4) and a clock generator (5), the signal under measurement is waveform shaped and the sampler (2) is formed. ), A PLL circuit (7) that locks and outputs the phase of the average period of the signal under measurement, and a phase delay of the signal output from the PLL circuit (7). A sampling digitizer comprising: a delay (6) which outputs a sampling clock to the sampler (2). 2. In a sampling digitizer having a sampler (2), an A / D converter (3), a memory (4) and a clock generator (5), the phase of the average period of the signal under measurement is measured. PL to lock and output
An L circuit (7), a waveform shaper (1) for waveform-shaping the signal output from the PLL circuit (7) and outputting it to the sampler (2), and 1 / n minutes for dividing the signal under measurement. Circulator (1
0) and the phase delay of the signal divided by the 1 / n frequency divider (10) is adjusted and sampling is performed by the sampler (2).
A sampling digitizer characterized by comprising a delay (6) for outputting as a clock. 3. A sampling digitizer having a sampler (2), an A / D converter (3), a memory (4) and a clock generator (5), wherein a signal under measurement is input to the sampler (2). A circuit directly connected to the terminal and P that locks and outputs the phase of the average period of the measured signal
An LL circuit (7), and a delay (6) for adjusting the phase delay of the signal output from the PLL circuit (7) and outputting it as a sampling clock to the sampler (2). Sampling digitizer.