WO2001038888A1

WO2001038888A1 - Apparatus and method for measuring jitter, and tester for semiconductor integrated circuit equipped with the apparatus for measuring jitter

Info

Publication number: WO2001038888A1
Application number: PCT/JP2000/008076
Authority: WO
Inventors: Takahiro Nakajima
Original assignee: Advantest Corporation
Priority date: 1999-11-19
Filing date: 2000-11-16
Publication date: 2001-05-31
Also published as: JP3609780B2; DE10083886T1

Abstract

An apparatus and method for measuring jitter while controlling the timing of a clock signal to a measuring point of jitter in a short time. The apparatus has a thinning circuit (22) for limiting the number of passing clock signals on a clock signal supply path from a clock generating section (12) of a sampling digitizer comprising a sampling head (11), the clock generating section (12), and a digitizer (13) to the digitizer and a trigger circuit (21) for controlling the thinning operation of the thinning circuit between the output end of the sampling head and the input end of the thinning circuit. In the trigger circuit, the level (amplitude) of a signal with respect to which jitter is measured and the edge data of the signal waveform are preset, and an equivalent sampling method is applied to the sampling digitizer.

Description

Description Jitter measuring apparatus and method, and semiconductor integrated circuit provided with the jitter measuring apparatus

Technical field

The present invention relates to a jitter measuring apparatus and a jitter measuring method for measuring a jitter of a high-speed repetitive signal by converting a high-speed repetitive signal into a low-speed repetitive signal, and a semiconductor integrated circuit test provided with the jitter measuring apparatus. Related to the device. Background art

When measuring the jitter of a high-speed repetitive signal, sample the point at which you want to measure or observe the jitter of the high-speed repetitive signal (for example, a specific level point at the rising edge of the signal waveform) at a fixed period. There is a need. In such a case, a device that converts the frequency of a high-speed repetitive signal into a low-speed repetitive signal and performs observation, measurement, analysis, etc. (hereinafter referred to as “sampling digitizer” in the art) (Referred to as a sampling digitizer). As shown in FIG. 4, the sampling digitizer includes a sampling head 11, a clock generation unit 12, and a device for observing, measuring, and / or analyzing a low-speed repetitive signal (usually its waveform) (hereinafter, referred to as a “sampler”). , A digitizer) 13, and a high-speed repetitive signal input to the sampling head (usually configured by a circuit having a diode bridge) 1 1 This is a device that converts the frequency into a low-speed repetitive signal, and observes, measures, and / or analyzes the low-speed signal and / or its waveform in the digitizer 13.

The above-mentioned equivalent sampling method is, for example, when a high-speed repetitive signal HSIG shown in FIG. 5A is input to the sampling head 11, the repetitive signal HSIG as shown in FIG. At a constant sampling rate (period) tl such that the phase of the sampling point with respect to is sequentially shifted by a fixed small time (equivalent sampling time) (in the second example, the phase is sequentially delayed by Δt). Generates clock signal CLK1 and supplies it to sampling head 11. As a result, as shown in FIG. 5C, the output signal OUT 1 whose amplitude level changes stepwise according to the sampling points a, b, c,... Generated by When the amplitude data of the sampling points a, b, c,... Of the output signal OUT 1 are synthesized by the digitizer 13 at the time interval of the equivalent sampling time (the time interval of At), the result is shown in FIG. 5D. Thus, a low-speed repetitive signal LS IG having a cycle obtained by multiplying the sampling rate t 1 by the number of measurement data (the number of samples) per one cycle (for example, I ns) of the high-speed signal HS IG is obtained. The waveform of the low-speed signal LSIG is substantially the same as the waveform of the high-speed signal HSIG.

To explain using specific numerical values, for example, when the frequency of the high-speed signal HS IG is 1 GHz (therefore, the period is Ins) and the frequency of the clock signal is 100 kHz, the high-speed signal HS If the number of samplings per IG cycle (Ins) is 100, the interval between two adjacent sampling points is 10 ps. That is, the equivalent sampling time is 10 ps. Therefore, the clock generator 1 2 force, et al, clock generation period (100 kHz der clock signal frequency in this example Runode 1 1 0 ⁵ sec) sampling was added the equivalent sampling time 10 ps Great tl = 10 / s Generates clock signal CL 1 at +10 ps and supplies it to sampling head 11. As a result, the output signal OUT 1 whose amplitude level changes stepwise according to the sampling points a, b, c,... Is changed to the sampling rate tl−l O s + l O Generated by ps. The amplitude data of the sampling points a, b, c,... Of the output signal OUT 1 are synthesized by the digitizer 13 at the interval between the sampling points, that is, at the time interval of the equivalent sampling time of 10 ps (the time interval of Δt). Then, when reproduced, a low-speed repetitive signal LSIG having a period of (10 / iS + 10ps) X100 is obtained.

By the way, when measuring the jitter of a high-speed repetitive signal, it is necessary to sample the point at which the jitter of the repetitive signal is to be measured or to be observed (hereinafter, simply referred to as the jitter measurement point) at a fixed period as described above. For this reason, the sampling method conventionally called inphase sampling is referred to as sampling digital. Jitter is measured at the jitter measurement point of a high-speed repetitive signal by applying it to a tether.

Next, the interface sampling method will be briefly described with reference to FIG. When the high-speed repetitive signal HSIG shown in Fig. 6B is input to the sampling digitizer, the jitter measurement point of this signal HSIG, in this example, a specific point m of the rising edge of the signal waveform is sampled. Generates a CLK signal with a sampling rate of T1. The jitter value at the jitter measurement point m shown in Figure 6A sampled by the peak signal CLK is input to the digitizer and analyzed, and the jitter at the jitter measurement point m of the high-speed signal HSIG is reduced. Observe, measure and / or analyze. In other words, the inclination (A VZ At) of the waveform of the high-speed signal H S IG converts the jitter (A t) into a voltage (Δν) by in-face sampling.

FIG. 7 is a block diagram showing an example of a jitter measuring circuit that measures the jitter of a high-speed repetitive signal by applying the in-face sampling method to a sampling digitizer. As shown in the figure, a timing control circuit 15 is inserted in the clock signal supply path from the clock generation unit 12 to the sampling head 11, and the clock applied to the sampling head 11 from the clock generation unit 12 is The timing of the clock signal CLK is controlled according to a control signal input from the digitizer 13 through the feedback circuit 14. In FIG. 7, portions corresponding to those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted unless necessary.

When the high-speed repetitive signal HSIG shown in Fig. 8 に is input to the sampling head 11, the clock generator 12 generates a signal to correctly sample the jitter measurement point of the high-speed signal HSIG. It is necessary to match the timing of clock signal generation to this jitter measurement point. For example, assuming that the jitter measurement point is a search point SP at the rising edge of the waveform as shown in FIG. 8A, the timing of the clock signal CLK having a period T1 generated from the clock generator 12 is calculated as shown in FIG. Must be matched to this search point SP as shown in. Therefore, the data (amplitude value) of the high-speed signal HSIG sampled by the clock signal CLK is taken into the digitizer 13 and its level is detected. A control signal is applied to the timing control circuit 15 through 14 to control (delay or advance) the timing of applying the clock signal CL to the sampling head 11. By repeating this operation, the rising edge of the waveform is detected first. For example, the rising edge point k or p of the waveform can be detected by detecting the data level of the high-speed signal HSIG sampled by the clock signal CLK shown in FIG. 8C or 8D. Furthermore, the search point SP at the detected rising edge is detected by repeating the same operation, and the timing of the click signal CLK is matched with the search point SP as shown in FIG. 8B. Is required. For example, after the rising edge point k of the waveform is detected, the edge point k is gradually approached to the search point SP to make it match, or after the rising edge point P of the waveform is detected, the edge point p is searched. An operation of gradually approaching and matching the point SP is performed.

By the way, the above-mentioned sampling digitizer is also used in a semiconductor integrated circuit test device (IC test device) for testing a semiconductor integrated circuit (hereinafter referred to as IC). For example, write a test pattern signal to the IC under test at high speed, measure the jitter of the test pattern signal read from this IC under high speed, and reliably respond to how fast the IC under test responds to high-speed signals Sampling digitizers are used to test whether or not they are true.

As is well known, in this technical field, I C refers to those having a main logic circuit portion (logic portion) as logic I C and those having a main memory portion as memory IC. Also, the logic part and the memory part were mixed on one chip.

IC is called System LSI, System on Chip (SOC), etc. Fig. 9 shows the schematic configuration of a conventional IC test apparatus (hereinafter referred to as an IC tester) that has been conventionally used. The illustrated IC tester is composed of an IC tester main body 100 and a test head 200, and in this example, the IC tester main body 100 includes a controller 101 and a timing generator. 10 2, pattern generator 10 3, waveform formatter 10 4, driver 10 5, comparator 10 6, logical comparator 10

7, a failure analysis memory 108, and a voltage generator 109.

The test head 200 is configured separately from the IC tester main body 100, A predetermined number of IC sockets (not shown) are mounted on the upper part. A printed circuit board called a pin card in this technical field is housed inside the test head 200. Usually, the driver 105 and the comparator of the IC tester 100 are stored. The circuit including the data 106 is mounted on this pin card. This pin card is provided for each of the 10 pins (input / output terminals) of the IC to be tested (IC under test) 300. Generally, the test head 200 is attached to a test section of an IC transport and processing device, which is called a handler in this technical field, and the test head 200 and the IC tester main body 100 are connected to a cable, an optical fiber, or the like. Are electrically connected by the signal transmission means.

The IC under test 300 is attached to the IC socket of the test head 200, and the test pattern signal is sent from the IC tester main body 100 to the IC under test (generally called DUT) 300 through this IC socket. Is applied, and a response signal from the IC under test 300 is supplied to the IC tester main body 100, and the test and measurement of the IC 300 under test are performed.

The controller 101 is constituted by a computer system, stores a test program created by a user (programmer) in advance, and controls the entire IC tester according to the test program. The controller 101 is a timing generator 102, a pattern generator 103, a waveform formatter 104, a logical comparator 107, a failure analysis memory 108, a voltage generator via the tester bus 111. These are connected to 109, etc., these timing generators 102, pattern generators 103, waveform formatters 104, logical comparators 107, failure analysis memory 108, voltage generators 1 09 operates as a terminal, and executes a test of the IC under test 300 in accordance with a control command output from the controller 101.

The test of the IC under test, for example, the functional test, is performed as follows.

Before starting the test, the pattern generator 103 stores the pattern generation order described in the test program stored in the controller 101 in advance. When a test start instruction is given from 01, the test pattern data to be applied to the IC under test 300 is stored in accordance with the stored pattern generation order. Output. Generally, an ALPG (Algorithmic Pattern Generator) is used as the pattern generator 103. ALPG is a pattern generator that generates a test pattern to be applied to a semiconductor device (for example, an IC) by using a register with an internal calculation function.

Before starting the test, the timing generator 102 stores in advance the timing data to be output for each test cycle described in the test program stored in the controller 101, and the timing generator 102 A clock pulse is output at each test cycle according to the stored timing data. This clock pulse is supplied to the waveform formatter 104, the logical comparator 107, and the like.

The waveform formatter 104 determines the rising and falling timings of the logical waveform based on the test pattern data output from the pattern generator 103 and the clock pulse output from the timing generator 102. It generates a test pattern signal with an actual waveform that changes to H logic (logic "1") and L logic (logic "0"), and applies this test to the IC under test through dry loop 105. Apply pattern signal.

The driver 105 sets the amplitude of the test pattern signal output from the waveform formatter 104 to a desired amplitude (H logic, that is, voltage VIH of logic "1" and L logic, that is, voltage VIL of logic "0"). The voltage is applied to the IC socket of the test head 200 to drive the IC 3 • 0 under test.

The comparator 106 determines whether or not the logic value of the response signal output from the IC under test has a normal voltage value. That is, it is determined whether the H logic voltage indicates a value equal to or higher than the specified voltage value VOH and the L logic voltage indicates a value equal to or lower than the specified voltage value VOL.

When the judgment result is good, the output signal of the judgment result output from the comparator 106 is input to the logical comparator 107, and is given from the pattern generator 103 in the logical comparator 107. It is compared with the expected value pattern data to determine whether or not the IC under test 300 has output a normal response signal. The comparison result of the logical comparator 107 is taken into the failure analysis memory 108. When a failure occurs, the failure test pattern address, the output logic data of the failure pin of the IC under test 300, and the The expected value pattern data is stored in the failure analysis memory 108 and used for LSI evaluation after the test.

The voltage generator 109, according to the set value sent from the controller 101, controls the amplitude voltages VIH and VIL applied to the driver 105 and the comparison voltage applied to the comparator 106. Generates VOH and VOL. As a result, a driver signal having an amplitude value conforming to the standard of the IC under test 300 is generated from the driver 105, and a response signal of the IC 300 under test is received by the comparator 106. It is possible to determine whether or not the test IC has a logical value of voltage that conforms to the standard of 3◦0.

The above-mentioned sampling digitizer is mounted on a pin card housed inside the test head 200, and measures the jitter of a response signal read at high speed from the IC 300 under test. First, a test pattern signal is written into the IC under test 300 at high speed, and the jitter of the test pattern signal read at high speed from each pin of the IC under test is measured by the sampling digitizer having the above configuration. The measured value of the jitter is compared with a preset reference value. If the measured value of the jitter is larger than the reference value, the test IC 300 is determined to be defective. This test classifies the operating speed of the IC under test into several categories, and also tests whether the IC under test can reliably respond to high-speed signals. it can.

As described above, conventionally, it is necessary to take sampling data into a digitizer, detect the level, and control the timing of the clock signal to the jitter measurement point according to this detection level. A considerable amount of data had to be acquired before the timing of the clock signal was matched, and there was a disadvantage that it took a long time to adjust the timing. In addition, since a timing control circuit is added, the jitter component of the timing control circuit cannot be ignored, and the jitter component may be increased. In addition, in an IC tester equipped with a sampling digitizer, there is a problem that the test time becomes longer. Disclosure of the invention

One object of the present invention is to quickly adjust the timing of a clock signal to a jitter measurement point. It is to provide a jitter measuring device which can be controlled at a time.

Another object of the present invention is to provide a jitter measuring method capable of controlling the timing of a clock signal to a jitter measuring point in a short time.

Still another object of the present invention is to provide an IC test apparatus capable of shortening a test time and performing highly accurate jitter measurement.

In order to achieve the above object, according to a first aspect of the present invention, there is provided a clock generating means for generating a clock signal, and a sampling unit for outputting data obtained by sampling an input high-speed repetitive signal by the clock signal. Trigger means to which output data from the sampling unit is supplied; thinning means for passing a clock signal supplied from the click generation means only when a trigger signal is supplied from the trigger means; Among the output data from the sampling unit, only a data sampled by the clock signal output from the thinning means is supplied, and a jitter measuring apparatus including signal analyzing means for measuring jitter of the supplied data is provided. Provided.

In a preferred embodiment, the sampling section, the clock generation means, and the signal analysis means constitute a sampling digitizer. Instead, the sampling unit, the click generation unit, and the signal analysis unit may constitute a sampling oscilloscope.

Also, the trigger means has preset signal level and signal waveform edge data for which jitter is to be measured, and the preset signal level and signal waveform edge data have been output from the sampling section. Only when is the trigger means activated and outputs a trigger signal.

The decimation number of the decimation circuit is set to a number smaller by one than the sampling number per cycle of the high-speed repetitive signal.

The clock generating means includes a sampling rate obtained by adding an equivalent sampling time of a value obtained by dividing a time corresponding to one cycle of the high-speed repetitive signal by the number of samplings per cycle of the high-speed repetitive signal to the clock generating cycle. A click signal is generated at the bottom.

In the second aspect of the present invention, a high-speed repetition symbol is output from the clock generation means. Sampling with the supplied sampling clock signal, and comparing the sampling data of the high-speed repetitive signal sampled with the clock signal with preset data, and finding that both data match. Generating a trigger signal only when the trigger signal is generated; outputting a clock signal supplied from the click generating means only when the trigger signal is generated; and outputting the sampling data of the high-speed repetitive signal. A jitter that is sampled with a peak signal output when the trigger signal is generated and supplied to a signal analyzing unit; and the signal analyzing unit measures the jitter of the supplied data. A measurement method is provided.

In a preferred embodiment, the sampling step includes, in a clock generation cycle, an equivalent sampling time obtained by dividing a time corresponding to one cycle of the high-speed repetitive signal by the number of samples per one cycle of the high-speed repetitive signal. The high-speed repetitive signal is sampled at the sampling rate to which is added.

Further, the trigger signal generating step includes a step of comparing a preset signal level for which jitter is to be measured, edge data of a signal waveform, and sampling data of the high-speed repetitive signal.

The step of outputting the peak signal only when the trigger signal is generated includes the step of reducing the clock signal supplied from the peak generation means by one less than the number of samplings per cycle of the high-speed repetitive signal. Output with thinning.

In a third aspect of the present invention, a test pattern signal is applied to a semiconductor integrated circuit under test, a response signal read from the semiconductor integrated circuit under test is logically compared, and a semiconductor integrated circuit under test is performed based on the comparison result. In a semiconductor integrated circuit test device for judging pass / fail, there is provided a semiconductor integrated circuit test device including any one of the jitter measuring devices described in the first aspect.

In a preferred embodiment, the jitter measuring device is mounted on a pin card housed in a test head of a semiconductor integrated circuit test device.

According to the above configuration, the sampling of the clock signal can be performed at the jitter measurement point only by waiting for a time corresponding to one cycle of the low-speed signal obtained by sampling the high-speed repetitive signal with the clock signal at the maximum. Timing can be matched . In addition, since the data at the jitter measurement point can be taken into the signal analysis means at a constant sampling rate by thinning out the clock signal by the thinning means, highly accurate jitter measurement can be performed. Furthermore, since there is no need to add a circuit for searching for a jitter measurement point such as a timing control circuit, there is no possibility that extra jitter is added to the measured jitter value. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram showing an embodiment of a jitter measuring apparatus according to the present invention. FIG. 2 is a timing chart for explaining the operation of the jitter measuring apparatus shown in FIG. 1 and the jitter measuring method according to the present invention.

FIG. 3 is a diagram showing sampling data taken into the digitizer of the jitter measuring apparatus shown in FIG.

FIG. 4 is a block diagram showing a configuration of a conventional sampling digitizer.

FIG. 5 is a timing chart illustrating an equivalent sampling method applied to the sampling digitizer shown in FIG.

FIG. 6 is a timing chart illustrating the in-face sampling method applied to the sampling digitizer shown in FIG.

FIG. 7 is a block diagram showing an example of a conventional jitter measuring device.

FIG. 8 is a timing chart for explaining the operation of the jitter measuring apparatus shown in FIG.

FIG. 9 is a block diagram showing an example of a conventional IC test apparatus. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, an embodiment of a jitter measuring apparatus and method according to the present invention will be described in detail with reference to FIGS. In FIG. 1, portions corresponding to those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted unless necessary.

FIG. 1 is a block diagram showing an embodiment of a jitter measuring apparatus according to the present invention. The illustrated jitter measuring apparatus includes a sampling digitizer constituted by a sampling head 11, a clock generator 12, and a digitizer 13. This sump The functions and operations of the ring digitizer have already been described with reference to FIGS. 5 to 8, and will not be described here.

According to the present invention, a thinning circuit 22 for limiting the number of passing clock signals is inserted in a clock signal supply path from the clock generator 12 of the sampling digitizer having the above configuration to the digitizer 13. A trigger circuit 21 for controlling the thinning operation of 22 is provided between the output terminal of the sampling head 11 and the input terminal of the thinning circuit 22 to configure a jitter measuring device and a sampling digitizer. Apply the equivalent sampling method.

In this embodiment, the level (amplitude) of the signal whose jitter is to be measured and the edge data (rising edge data or falling edge data) of the signal waveform are set in the trigger circuit 21 in advance. The trigger circuit 21 compares the input sampling data with a preset value, and outputs a trigger signal when the input sampling data has a value equal to the preset value. In the decimation circuit 21, a decimation number (a number to be reduced) of the clock signal CLK supplied from the clock generation unit 12 is set. Therefore, the trigger circuit 21 operates only when a preset signal level is output from the sampling head 11 at the edge of the preset signal waveform, and the thinning circuit 22: outputs this trigger signal. I do. On the other hand, the decimation circuit 22 allows the click signal to pass only when the trigger signal is input.

The equivalent sampling method is applied to the sampling digitizer of the jitter measuring apparatus having the above configuration, but this equivalent sampling method is the same as the conventional equivalent sampling method already described with reference to FIG. Omitted.

The operation of the jitter measuring apparatus according to the present invention having the above configuration will be described with reference to FIG. As described above, the clock signal generated from the clock generator 12 at the sampling rate t1 (the same sampling rate as the clock signal CLK1 in Fig. 5B), which is the sum of the clock generation cycle and the equivalent sampling time Δt CLK (FIG. 2B) is supplied to the sampling head 11 and the thinning circuit 22 respectively. Therefore, when the high-speed repetitive signal HSIG is input to the sampling head 11, the low-speed data SAM (sampled by the clock signal CLK as shown in FIG. The data shown in white circles in Fig. 2A) is output. It is provided to the rigger circuit 21 and the digitizer 13. The period T of the data signal output from the sampling head 11 is a value (time) obtained by multiplying the sampling rate t1 of the peak signal by the number of samples.

The trigger circuit 21 operates only when data of the preset edge data and level (in this example, the rising edge data and the trigger level TLV) are supplied and triggers the thinning circuit 22. When the trigger level TLV data a, a ', a "(a" is not shown in FIG. 2A), and the data of the trigger level TLV at the rising edge of the data SAM are supplied to the trigger circuit 21 Only in this case, the thinning circuit 22 operates to output the input clock signal CLK. The decimated clock signal CLK 2 (FIG. 2C) output from the decimating circuit 22 is supplied to the digitizer 13 and the data SAM supplied from the sampling head 11 to the digitizer 13 is output. Only the data a, a ', a〃,... Of the trigger level TLV at the rising edge are input to the digitizer 13. As a result, the digitizer 13 receives the data shown in Fig. 3 at the period of the clock signal CLK2 output from the thinning circuit 22 (equal to the period T of the data signal SAM output from the sampling head 11). Therefore, based on this data, the digitizer 13 can measure the jitter of the trigger level TLV data a, a ', a ", a ·' at the rising edge.

To explain using specific numerical values, for example, the frequency of the high-speed signal HSIG input to the sampling head 11 is 1 GHz (therefore, the period is 1 ns), and the frequency of the clock signal is 10 ns. Assuming that the number of samples per cycle (1 ns) of this high-speed signal HSIG is 100, the equivalent sampling time Δt is 10 ps as described above. The sample rate tl of the clock signal CLK is 10 / s + 1 0 ps. Therefore, the clock generators 12 generate a clock signal CLK at a sampling rate t 1 of 10 μs + 10 ps, and supply the clock signal CLK to the sampling head 11 and the thinning circuit 22. Since the thinning circuit 22 operates only when the trigger level TLV data a, a ',... At the rising edge is supplied to the trigger circuit 21, the interrogating circuit per one cycle of the high-speed signal HSIG is used. The decimation factor of 2 2 is 1 0 0 — 1 = 99. Setting the thinning number like this (10 / is + 10 ps) X 100 = One clock signal CL K2 is supplied to digitizer 13 from decimation circuit 22 every 1 ms, so that the trigger level of the rising edge of the input high-speed signal is always Data can be taken into digitizer 13 in terms of TLV.

Generally speaking, when expressed numerically, the equivalent sampling time is set such that the value obtained by multiplying the equivalent sampling time Δt by the number of samplings n (a positive integer) per one cycle of the high-speed signal HSIG becomes one cycle of the high-speed signal HS IG. Then, set the decimation factor of the decimation circuit 22 per one cycle T of the sampling output SAM to (n-1).

According to the jitter measuring apparatus and method according to the present invention described above, the high-speed signal HS IG is sampled, the sampling data is taken into the digitizer 13, and it is not necessary to detect the edge and level of the high-speed signal HS IG. The trigger signal is supplied from the trigger circuit 21 to the decimation circuit 22 only by waiting for a period corresponding to one period T of AM, so that the jitter can be measured in a very short time. The sampling timing of the clock signal CLK generated from the clock generator 12 can be matched to the edge trigger level TLV.

As a specific example, if the number of samples is 1000 points and the sampling rate is 10 μs + 10 ps, the jitter measurement device to which the conventional interface sampling method is applied (see Fig. 7) The time required to search for a preset point for measuring jitter was 20 Oms (actually measured value), but in the case of the jitter measuring device according to the present invention (see Fig. 1), the maximum time was (10 μm). the _{s + 10 p S) X 1000} 1 Om s. Therefore, according to the present invention, the time required for searching for a jitter measurement point is reduced to at least about 1Z20.

In addition, since the data at the jitter measurement point is taken into the digitizer 13 at a constant sampling rate by thinning out the clock signal CLK by the thinning circuit 22, highly accurate jitter measurement can be performed. Furthermore, there is no need to add a circuit to search for jitter measurement points such as a timing control circuit, so there is no risk that extra jitter will be added to the jitter measurement value.

The jitter measuring device with the above configuration is installed in the IC tester test head 200 shown in Fig. 9. When mounted on a pin card housed in the IC, the test pattern signal is written to the IC under test 300 at a high speed, and the jitter of the test pattern signal read out from each pin of the IC under test at a high speed can be measured with this jitter measuring device. It can be measured with high accuracy. By comparing the measured value of this jitter with a preset reference value, the quality of the IC under test can be correctly determined, so that the test speed of the IC under test is classified into several categories. Also, it is possible to execute a test to determine whether or not the IC under test can respond to a high-speed signal without fail, thereby providing a useful IC test apparatus. In addition, the test time can be reduced.

In the above embodiment, a high-speed repetitive signal is frequency-converted into a low-speed repetitive signal, and a sampling digitizer is used as a device for observing, measuring, and analyzing or analyzing the low-speed signal. However, the present invention is not limited to this. It goes without saying that another device having a similar function such as an oscilloscope may be used.

As is clear from the above description, according to the present invention, the jitter measurement point can be closed just by waiting for a time corresponding to one cycle of the low-speed signal obtained by sampling the high-speed signal with the clock signal. The sampling timing of the clock signal can be matched. Also, by thinning out the clock signal by the thinning-out circuit, the data at the jitter measurement point can be taken into the signal analysis means at a fixed sampling rate, so that highly accurate jitter measurement can be performed. Further, since it is not necessary to add a circuit for searching for a jitter measurement point such as a timing control circuit, there is an advantage that there is no possibility that extra jitter is added to the measured jitter value.

In addition, if the jitter measuring device according to the present invention is mounted on a pin card housed in the test head of the IC tester, the jitter of the test pattern signal read from each pin of the IC under test at high speed can be accurately determined. Can be measured. Therefore, a test that classifies the operating speed of the IC under test into several categories and a test as to how fast the IC under test can reliably respond to a high-speed signal can be performed. Test equipment can be provided. In addition, the test time can be reduced. Although the present invention has been described with reference to preferred embodiments, it is understood that various modifications, changes, and improvements can be made in the embodiments described above without departing from the spirit and scope of the invention. Will be obvious to others. Therefore, this The invention is not limited to the illustrated embodiments, but encompasses all such variations, modifications and improvements that fall within the scope of the invention as defined by the appended claims.

Claims

The scope of the claims

1. Clock generating means for generating a clock signal;

A sampling unit that outputs data obtained by sampling the input high-speed repetitive signal by the clock signal;

Trigger means to which output data from the sampling unit is supplied;

Thinning means for passing the clock signal supplied from the click generating means only when a trigger signal is given from the trigger means;

Of the output data from the sampling section, only data sampled by the CK signal output from the thinning means is supplied, and signal analysis means for measuring the jitter of the supplied data.

A jitter measuring apparatus comprising:

2. The jitter measuring apparatus according to claim 1, wherein the sampling section, the clock generating means, and the signal analyzing means constitute a sampling digitizer.

3. The jitter measuring apparatus according to claim 1, wherein the sampling section, the clock generating section, and the signal analyzing section constitute a sampling oscilloscope.

4. The signal level and the edge data of the signal waveform whose jitter is to be measured are preset in the trigger means, and the preset signal level and the edge data of the signal waveform are output from the sampling unit. 2. The jitter measuring apparatus according to claim 1, wherein the trigger means operates and outputs a trigger signal only when the trigger is issued.

5. The number of interrogations of the thinning circuit is set to a number that is one less than the number of samplings per cycle of the high-speed repetitive signal. 3. The jitter measuring device according to 1.

6. The clock generating means performs sampling by adding an equivalent sampling time of a value obtained by dividing a time corresponding to one cycle of the high-speed repetitive signal by the number of samplings per cycle of the high-speed repetitive signal to the clock generation cycle. 2. The jitter measuring device according to claim 1, wherein a clock signal is generated at a rate.

7. sampling a high-speed repetitive signal with a sampling clock signal supplied from a clock generating means;

Comparing sampling data of the high-speed repetitive signal sampled by the mouth signal with preset data, and generating a trigger signal only when both data match;

Outputting a clock signal supplied from the click generating means only when the trigger signal is generated;

Sampling the sampling data of the high-speed repetitive signal with a clock signal output when the trigger signal is generated, and supplying the sampled data to signal analysis means; and measuring the jitter of the supplied data in the signal analysis means. A jitter measuring method, comprising:

8. The sampling step is a sampling rate obtained by adding an equivalent sampling time obtained by dividing a time corresponding to one cycle of the high-speed repetitive signal by the number of samples per one cycle of the high-speed repetitive signal to a clock generation cycle. 8. The jitter measuring method according to claim 7, wherein the high-speed repetitive signal is sampled with a unit.

9. The trigger signal generating step includes a step of comparing a preset signal level at which jitter is to be measured, edge data of the signal waveform, and sampling data of the high-speed repetitive signal. 7. The jitter measurement method according to item 7, wherein

10. In the step of outputting the peak signal only when the trigger signal is generated, the clock signal supplied from the peak generation means is set to be one more than the sampling number per cycle of the high-speed repetitive signal. 8. The jitter measuring method according to claim 7, wherein the number is reduced and output.

11. Apply a test pattern signal to the semiconductor integrated circuit under test, logically compare the response signals read out from the semiconductor integrated circuit under test, and judge the quality of the semiconductor integrated circuit under test based on the comparison result. In a semiconductor integrated circuit test apparatus,

A semiconductor integrated circuit test apparatus, comprising the jitter measuring apparatus according to any one of claims 1 to 6.

12. The semiconductor integrated circuit test device according to claim 11, wherein the jitter measuring device is mounted on a pin card housed in a test head of a semiconductor integrated circuit test device. .