WO2001038888A1 - Appareil et procede de mesure d'instabilite et appareil de controle pour circuit integre a semi-conducteur equipe de l'appareil de mesure d'instabilite - Google Patents

Appareil et procede de mesure d'instabilite et appareil de controle pour circuit integre a semi-conducteur equipe de l'appareil de mesure d'instabilite Download PDF

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Publication number
WO2001038888A1
WO2001038888A1 PCT/JP2000/008076 JP0008076W WO0138888A1 WO 2001038888 A1 WO2001038888 A1 WO 2001038888A1 JP 0008076 W JP0008076 W JP 0008076W WO 0138888 A1 WO0138888 A1 WO 0138888A1
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WIPO (PCT)
Prior art keywords
signal
sampling
jitter
data
clock
Prior art date
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PCT/JP2000/008076
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English (en)
Japanese (ja)
Inventor
Takahiro Nakajima
Original Assignee
Advantest Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corporation filed Critical Advantest Corporation
Priority to JP2001540385A priority Critical patent/JP3609780B2/ja
Priority to DE10083886T priority patent/DE10083886T1/de
Publication of WO2001038888A1 publication Critical patent/WO2001038888A1/fr

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R25/00—Arrangements for measuring phase angle between a voltage and a current or between voltages or currents
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
    • G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
    • G01R29/027—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values
    • G01R29/0273—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values the pulse characteristic being duration, i.e. width (indicating that frequency of pulses is above or below a certain limit)

Definitions

  • the present invention relates to a jitter measuring apparatus and a jitter measuring method for measuring a jitter of a high-speed repetitive signal by converting a high-speed repetitive signal into a low-speed repetitive signal, and a semiconductor integrated circuit test provided with the jitter measuring apparatus.
  • a jitter measuring apparatus and a jitter measuring method for measuring a jitter of a high-speed repetitive signal by converting a high-speed repetitive signal into a low-speed repetitive signal, and a semiconductor integrated circuit test provided with the jitter measuring apparatus.
  • sampling digitizer When measuring the jitter of a high-speed repetitive signal, sample the point at which you want to measure or observe the jitter of the high-speed repetitive signal (for example, a specific level point at the rising edge of the signal waveform) at a fixed period. There is a need.
  • a device that converts the frequency of a high-speed repetitive signal into a low-speed repetitive signal and performs observation, measurement, analysis, etc. hereinafter referred to as “sampling digitizer” in the art
  • sampling digitizer Referred to as a sampling digitizer
  • the above-mentioned equivalent sampling method is, for example, when a high-speed repetitive signal HSIG shown in FIG. 5A is input to the sampling head 11, the repetitive signal HSIG as shown in FIG. At a constant sampling rate (period) tl such that the phase of the sampling point with respect to is sequentially shifted by a fixed small time (equivalent sampling time) (in the second example, the phase is sequentially delayed by ⁇ t). Generates clock signal CLK1 and supplies it to sampling head 11. As a result, as shown in FIG. 5C, the output signal OUT 1 whose amplitude level changes stepwise according to the sampling points a, b, c,... Generated by When the amplitude data of the sampling points a, b, c,...
  • a low-speed repetitive signal LS IG having a cycle obtained by multiplying the sampling rate t 1 by the number of measurement data (the number of samples) per one cycle (for example, I ns) of the high-speed signal HS IG is obtained.
  • the waveform of the low-speed signal LSIG is substantially the same as the waveform of the high-speed signal HSIG.
  • the high-speed signal HS IG is 1 GHz (therefore, the period is Ins) and the frequency of the clock signal is 100 kHz
  • the output signal OUT 1 whose amplitude level changes stepwise according to the sampling points a, b, c,... Is changed to the sampling rate tl ⁇ l O s + l O Generated by ps.
  • the amplitude data of the sampling points a, b, c,... Of the output signal OUT 1 are synthesized by the digitizer 13 at the interval between the sampling points, that is, at the time interval of the equivalent sampling time of 10 ps (the time interval of ⁇ t). Then, when reproduced, a low-speed repetitive signal LSIG having a period of (10 / iS + 10ps) X100 is obtained.
  • the sampling method conventionally called inphase sampling is referred to as sampling digital. Jitter is measured at the jitter measurement point of a high-speed repetitive signal by applying it to a tether.
  • the interface sampling method will be briefly described with reference to FIG.
  • the jitter measurement point of this signal HSIG in this example, a specific point m of the rising edge of the signal waveform is sampled.
  • the jitter value at the jitter measurement point m shown in Figure 6A sampled by the peak signal CLK is input to the digitizer and analyzed, and the jitter at the jitter measurement point m of the high-speed signal HSIG is reduced.
  • the inclination (A VZ At) of the waveform of the high-speed signal H S IG converts the jitter (A t) into a voltage ( ⁇ ) by in-face sampling.
  • FIG. 7 is a block diagram showing an example of a jitter measuring circuit that measures the jitter of a high-speed repetitive signal by applying the in-face sampling method to a sampling digitizer.
  • a timing control circuit 15 is inserted in the clock signal supply path from the clock generation unit 12 to the sampling head 11, and the clock applied to the sampling head 11 from the clock generation unit 12 is The timing of the clock signal CLK is controlled according to a control signal input from the digitizer 13 through the feedback circuit 14.
  • portions corresponding to those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted unless necessary.
  • the clock generator 12 When the high-speed repetitive signal HSIG shown in Fig. 8 ⁇ is input to the sampling head 11, the clock generator 12 generates a signal to correctly sample the jitter measurement point of the high-speed signal HSIG. It is necessary to match the timing of clock signal generation to this jitter measurement point. For example, assuming that the jitter measurement point is a search point SP at the rising edge of the waveform as shown in FIG. 8A, the timing of the clock signal CLK having a period T1 generated from the clock generator 12 is calculated as shown in FIG. Must be matched to this search point SP as shown in. Therefore, the data (amplitude value) of the high-speed signal HSIG sampled by the clock signal CLK is taken into the digitizer 13 and its level is detected.
  • a control signal is applied to the timing control circuit 15 through 14 to control (delay or advance) the timing of applying the clock signal CL to the sampling head 11.
  • the rising edge of the waveform is detected first.
  • the rising edge point k or p of the waveform can be detected by detecting the data level of the high-speed signal HSIG sampled by the clock signal CLK shown in FIG. 8C or 8D.
  • the search point SP at the detected rising edge is detected by repeating the same operation, and the timing of the click signal CLK is matched with the search point SP as shown in FIG. 8B. Is required.
  • the edge point k of the waveform is detected, the edge point k is gradually approached to the search point SP to make it match, or after the rising edge point P of the waveform is detected, the edge point p is searched. An operation of gradually approaching and matching the point SP is performed.
  • the above-mentioned sampling digitizer is also used in a semiconductor integrated circuit test device (IC test device) for testing a semiconductor integrated circuit (hereinafter referred to as IC).
  • IC test device semiconductor integrated circuit test device
  • Sampling digitizers are used to test whether or not they are true.
  • I C refers to those having a main logic circuit portion (logic portion) as logic I C and those having a main memory portion as memory IC. Also, the logic part and the memory part were mixed on one chip.
  • IC is called System LSI, System on Chip (SOC), etc.
  • Fig. 9 shows the schematic configuration of a conventional IC test apparatus (hereinafter referred to as an IC tester) that has been conventionally used.
  • the illustrated IC tester is composed of an IC tester main body 100 and a test head 200, and in this example, the IC tester main body 100 includes a controller 101 and a timing generator. 10 2, pattern generator 10 3, waveform formatter 10 4, driver 10 5, comparator 10 6, logical comparator 10
  • the test head 200 is configured separately from the IC tester main body 100, A predetermined number of IC sockets (not shown) are mounted on the upper part. A printed circuit board called a pin card in this technical field is housed inside the test head 200. Usually, the driver 105 and the comparator of the IC tester 100 are stored. The circuit including the data 106 is mounted on this pin card. This pin card is provided for each of the 10 pins (input / output terminals) of the IC to be tested (IC under test) 300. Generally, the test head 200 is attached to a test section of an IC transport and processing device, which is called a handler in this technical field, and the test head 200 and the IC tester main body 100 are connected to a cable, an optical fiber, or the like. Are electrically connected by the signal transmission means.
  • the IC under test 300 is attached to the IC socket of the test head 200, and the test pattern signal is sent from the IC tester main body 100 to the IC under test (generally called DUT) 300 through this IC socket. Is applied, and a response signal from the IC under test 300 is supplied to the IC tester main body 100, and the test and measurement of the IC 300 under test are performed.
  • the controller 101 is constituted by a computer system, stores a test program created by a user (programmer) in advance, and controls the entire IC tester according to the test program.
  • the controller 101 is a timing generator 102, a pattern generator 103, a waveform formatter 104, a logical comparator 107, a failure analysis memory 108, a voltage generator via the tester bus 111. These are connected to 109, etc., these timing generators 102, pattern generators 103, waveform formatters 104, logical comparators 107, failure analysis memory 108, voltage generators 1 09 operates as a terminal, and executes a test of the IC under test 300 in accordance with a control command output from the controller 101.
  • test of the IC under test for example, the functional test, is performed as follows.
  • the pattern generator 103 Before starting the test, the pattern generator 103 stores the pattern generation order described in the test program stored in the controller 101 in advance. When a test start instruction is given from 01, the test pattern data to be applied to the IC under test 300 is stored in accordance with the stored pattern generation order. Output.
  • an ALPG Algorithmic Pattern Generator
  • ALPG is a pattern generator that generates a test pattern to be applied to a semiconductor device (for example, an IC) by using a register with an internal calculation function.
  • the timing generator 102 stores in advance the timing data to be output for each test cycle described in the test program stored in the controller 101, and the timing generator 102 A clock pulse is output at each test cycle according to the stored timing data. This clock pulse is supplied to the waveform formatter 104, the logical comparator 107, and the like.
  • the waveform formatter 104 determines the rising and falling timings of the logical waveform based on the test pattern data output from the pattern generator 103 and the clock pulse output from the timing generator 102. It generates a test pattern signal with an actual waveform that changes to H logic (logic "1") and L logic (logic "0"), and applies this test to the IC under test through dry loop 105. Apply pattern signal.
  • the driver 105 sets the amplitude of the test pattern signal output from the waveform formatter 104 to a desired amplitude (H logic, that is, voltage VIH of logic “1” and L logic, that is, voltage VIL of logic “0").
  • H logic that is, voltage VIH of logic "1”
  • L logic that is, voltage VIL of logic "0”
  • the voltage is applied to the IC socket of the test head 200 to drive the IC 3 • 0 under test.
  • the comparator 106 determines whether or not the logic value of the response signal output from the IC under test has a normal voltage value. That is, it is determined whether the H logic voltage indicates a value equal to or higher than the specified voltage value VOH and the L logic voltage indicates a value equal to or lower than the specified voltage value VOL.
  • the output signal of the judgment result output from the comparator 106 is input to the logical comparator 107, and is given from the pattern generator 103 in the logical comparator 107. It is compared with the expected value pattern data to determine whether or not the IC under test 300 has output a normal response signal.
  • the comparison result of the logical comparator 107 is taken into the failure analysis memory 108.
  • the failure test pattern address, the output logic data of the failure pin of the IC under test 300, and the The expected value pattern data is stored in the failure analysis memory 108 and used for LSI evaluation after the test.
  • the voltage generator 109 controls the amplitude voltages VIH and VIL applied to the driver 105 and the comparison voltage applied to the comparator 106. Generates VOH and VOL. As a result, a driver signal having an amplitude value conforming to the standard of the IC under test 300 is generated from the driver 105, and a response signal of the IC 300 under test is received by the comparator 106. It is possible to determine whether or not the test IC has a logical value of voltage that conforms to the standard of 3 ⁇ 0.
  • the above-mentioned sampling digitizer is mounted on a pin card housed inside the test head 200, and measures the jitter of a response signal read at high speed from the IC 300 under test.
  • a test pattern signal is written into the IC under test 300 at high speed, and the jitter of the test pattern signal read at high speed from each pin of the IC under test is measured by the sampling digitizer having the above configuration.
  • the measured value of the jitter is compared with a preset reference value. If the measured value of the jitter is larger than the reference value, the test IC 300 is determined to be defective.
  • This test classifies the operating speed of the IC under test into several categories, and also tests whether the IC under test can reliably respond to high-speed signals. it can.
  • One object of the present invention is to quickly adjust the timing of a clock signal to a jitter measurement point. It is to provide a jitter measuring device which can be controlled at a time.
  • Another object of the present invention is to provide a jitter measuring method capable of controlling the timing of a clock signal to a jitter measuring point in a short time.
  • Still another object of the present invention is to provide an IC test apparatus capable of shortening a test time and performing highly accurate jitter measurement.
  • a clock generating means for generating a clock signal, and a sampling unit for outputting data obtained by sampling an input high-speed repetitive signal by the clock signal.
  • Trigger means to which output data from the sampling unit is supplied; thinning means for passing a clock signal supplied from the click generation means only when a trigger signal is supplied from the trigger means; Among the output data from the sampling unit, only a data sampled by the clock signal output from the thinning means is supplied, and a jitter measuring apparatus including signal analyzing means for measuring jitter of the supplied data is provided.
  • the sampling section, the clock generation means, and the signal analysis means constitute a sampling digitizer.
  • the sampling unit, the click generation unit, and the signal analysis unit may constitute a sampling oscilloscope.
  • the trigger means has preset signal level and signal waveform edge data for which jitter is to be measured, and the preset signal level and signal waveform edge data have been output from the sampling section. Only when is the trigger means activated and outputs a trigger signal.
  • the decimation number of the decimation circuit is set to a number smaller by one than the sampling number per cycle of the high-speed repetitive signal.
  • the clock generating means includes a sampling rate obtained by adding an equivalent sampling time of a value obtained by dividing a time corresponding to one cycle of the high-speed repetitive signal by the number of samplings per cycle of the high-speed repetitive signal to the clock generating cycle.
  • a click signal is generated at the bottom.
  • a high-speed repetition symbol is output from the clock generation means.
  • a jitter that is sampled with a peak signal output when the trigger signal is generated and supplied to a signal analyzing unit; and the signal analyzing unit measures the jitter of the supplied data.
  • a measurement method is provided.
  • the sampling step includes, in a clock generation cycle, an equivalent sampling time obtained by dividing a time corresponding to one cycle of the high-speed repetitive signal by the number of samples per one cycle of the high-speed repetitive signal.
  • the high-speed repetitive signal is sampled at the sampling rate to which is added.
  • the trigger signal generating step includes a step of comparing a preset signal level for which jitter is to be measured, edge data of a signal waveform, and sampling data of the high-speed repetitive signal.
  • the step of outputting the peak signal only when the trigger signal is generated includes the step of reducing the clock signal supplied from the peak generation means by one less than the number of samplings per cycle of the high-speed repetitive signal. Output with thinning.
  • a test pattern signal is applied to a semiconductor integrated circuit under test, a response signal read from the semiconductor integrated circuit under test is logically compared, and a semiconductor integrated circuit under test is performed based on the comparison result.
  • a semiconductor integrated circuit test device for judging pass / fail there is provided a semiconductor integrated circuit test device including any one of the jitter measuring devices described in the first aspect.
  • the jitter measuring device is mounted on a pin card housed in a test head of a semiconductor integrated circuit test device.
  • the sampling of the clock signal can be performed at the jitter measurement point only by waiting for a time corresponding to one cycle of the low-speed signal obtained by sampling the high-speed repetitive signal with the clock signal at the maximum. Timing can be matched .
  • the data at the jitter measurement point can be taken into the signal analysis means at a constant sampling rate by thinning out the clock signal by the thinning means, highly accurate jitter measurement can be performed.
  • there is no need to add a circuit for searching for a jitter measurement point such as a timing control circuit, there is no possibility that extra jitter is added to the measured jitter value.
  • FIG. 1 is a block diagram showing an embodiment of a jitter measuring apparatus according to the present invention.
  • FIG. 2 is a timing chart for explaining the operation of the jitter measuring apparatus shown in FIG. 1 and the jitter measuring method according to the present invention.
  • FIG. 3 is a diagram showing sampling data taken into the digitizer of the jitter measuring apparatus shown in FIG.
  • FIG. 4 is a block diagram showing a configuration of a conventional sampling digitizer.
  • FIG. 5 is a timing chart illustrating an equivalent sampling method applied to the sampling digitizer shown in FIG.
  • FIG. 6 is a timing chart illustrating the in-face sampling method applied to the sampling digitizer shown in FIG.
  • FIG. 7 is a block diagram showing an example of a conventional jitter measuring device.
  • FIG. 8 is a timing chart for explaining the operation of the jitter measuring apparatus shown in FIG.
  • FIG. 9 is a block diagram showing an example of a conventional IC test apparatus. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 portions corresponding to those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted unless necessary.
  • FIG. 1 is a block diagram showing an embodiment of a jitter measuring apparatus according to the present invention.
  • the illustrated jitter measuring apparatus includes a sampling digitizer constituted by a sampling head 11, a clock generator 12, and a digitizer 13. This sump The functions and operations of the ring digitizer have already been described with reference to FIGS. 5 to 8, and will not be described here.
  • a thinning circuit 22 for limiting the number of passing clock signals is inserted in a clock signal supply path from the clock generator 12 of the sampling digitizer having the above configuration to the digitizer 13.
  • a trigger circuit 21 for controlling the thinning operation of 22 is provided between the output terminal of the sampling head 11 and the input terminal of the thinning circuit 22 to configure a jitter measuring device and a sampling digitizer. Apply the equivalent sampling method.
  • the level (amplitude) of the signal whose jitter is to be measured and the edge data (rising edge data or falling edge data) of the signal waveform are set in the trigger circuit 21 in advance.
  • the trigger circuit 21 compares the input sampling data with a preset value, and outputs a trigger signal when the input sampling data has a value equal to the preset value.
  • a decimation number (a number to be reduced) of the clock signal CLK supplied from the clock generation unit 12 is set. Therefore, the trigger circuit 21 operates only when a preset signal level is output from the sampling head 11 at the edge of the preset signal waveform, and the thinning circuit 22: outputs this trigger signal. I do.
  • the decimation circuit 22 allows the click signal to pass only when the trigger signal is input.
  • the equivalent sampling method is applied to the sampling digitizer of the jitter measuring apparatus having the above configuration, but this equivalent sampling method is the same as the conventional equivalent sampling method already described with reference to FIG. Omitted.
  • the clock signal generated from the clock generator 12 at the sampling rate t1 (the same sampling rate as the clock signal CLK1 in Fig. 5B), which is the sum of the clock generation cycle and the equivalent sampling time ⁇ t CLK (FIG. 2B) is supplied to the sampling head 11 and the thinning circuit 22 respectively. Therefore, when the high-speed repetitive signal HSIG is input to the sampling head 11, the low-speed data SAM (sampled by the clock signal CLK as shown in FIG. The data shown in white circles in Fig. 2A) is output. It is provided to the rigger circuit 21 and the digitizer 13.
  • the period T of the data signal output from the sampling head 11 is a value (time) obtained by multiplying the sampling rate t1 of the peak signal by the number of samples.
  • the trigger circuit 21 operates only when data of the preset edge data and level (in this example, the rising edge data and the trigger level TLV) are supplied and triggers the thinning circuit 22.
  • the trigger level TLV data a, a ', a "(a" is not shown in FIG. 2A)
  • the thinning circuit 22 operates to output the input clock signal CLK.
  • the decimated clock signal CLK 2 (FIG. 2C) output from the decimating circuit 22 is supplied to the digitizer 13 and the data SAM supplied from the sampling head 11 to the digitizer 13 is output. Only the data a, a ', a ⁇ ,...
  • the digitizer 13 receives the data shown in Fig. 3 at the period of the clock signal CLK2 output from the thinning circuit 22 (equal to the period T of the data signal SAM output from the sampling head 11). Therefore, based on this data, the digitizer 13 can measure the jitter of the trigger level TLV data a, a ', a ", a ⁇ ' at the rising edge.
  • the frequency of the high-speed signal HSIG input to the sampling head 11 is 1 GHz (therefore, the period is 1 ns), and the frequency of the clock signal is 10 ns.
  • the equivalent sampling time ⁇ t is 10 ps as described above.
  • the sample rate tl of the clock signal CLK is 10 / s + 1 0 ps. Therefore, the clock generators 12 generate a clock signal CLK at a sampling rate t 1 of 10 ⁇ s + 10 ps, and supply the clock signal CLK to the sampling head 11 and the thinning circuit 22.
  • the thinning circuit 22 Since the thinning circuit 22 operates only when the trigger level TLV data a, a ',... At the rising edge is supplied to the trigger circuit 21, the interrogating circuit per one cycle of the high-speed signal HSIG is used.
  • X 100 One clock signal CL K2 is supplied to digitizer 13 from decimation circuit 22 every 1 ms, so that the trigger level of the rising edge of the input high-speed signal is always Data can be taken into digitizer 13 in terms of TLV.
  • the equivalent sampling time is set such that the value obtained by multiplying the equivalent sampling time ⁇ t by the number of samplings n (a positive integer) per one cycle of the high-speed signal HSIG becomes one cycle of the high-speed signal HS IG. Then, set the decimation factor of the decimation circuit 22 per one cycle T of the sampling output SAM to (n-1).
  • the high-speed signal HS IG is sampled, the sampling data is taken into the digitizer 13, and it is not necessary to detect the edge and level of the high-speed signal HS IG.
  • the trigger signal is supplied from the trigger circuit 21 to the decimation circuit 22 only by waiting for a period corresponding to one period T of AM, so that the jitter can be measured in a very short time.
  • the sampling timing of the clock signal CLK generated from the clock generator 12 can be matched to the edge trigger level TLV.
  • the jitter measurement device to which the conventional interface sampling method is applied see Fig. 7
  • the time required to search for a preset point for measuring jitter was 20 Oms (actually measured value), but in the case of the jitter measuring device according to the present invention (see Fig. 1), the maximum time was (10 ⁇ m).
  • the data at the jitter measurement point is taken into the digitizer 13 at a constant sampling rate by thinning out the clock signal CLK by the thinning circuit 22, highly accurate jitter measurement can be performed. Furthermore, there is no need to add a circuit to search for jitter measurement points such as a timing control circuit, so there is no risk that extra jitter will be added to the jitter measurement value.
  • the jitter measuring device with the above configuration is installed in the IC tester test head 200 shown in Fig. 9.
  • the test pattern signal is written to the IC under test 300 at a high speed, and the jitter of the test pattern signal read out from each pin of the IC under test at a high speed can be measured with this jitter measuring device. It can be measured with high accuracy.
  • the quality of the IC under test can be correctly determined, so that the test speed of the IC under test is classified into several categories.
  • the test time can be reduced.
  • a high-speed repetitive signal is frequency-converted into a low-speed repetitive signal
  • a sampling digitizer is used as a device for observing, measuring, and analyzing or analyzing the low-speed signal.
  • the present invention is not limited to this. It goes without saying that another device having a similar function such as an oscilloscope may be used.
  • the jitter measurement point can be closed just by waiting for a time corresponding to one cycle of the low-speed signal obtained by sampling the high-speed signal with the clock signal.
  • the sampling timing of the clock signal can be matched.
  • the data at the jitter measurement point can be taken into the signal analysis means at a fixed sampling rate, so that highly accurate jitter measurement can be performed.
  • a circuit for searching for a jitter measurement point such as a timing control circuit, there is an advantage that there is no possibility that extra jitter is added to the measured jitter value.
  • the jitter measuring device is mounted on a pin card housed in the test head of the IC tester, the jitter of the test pattern signal read from each pin of the IC under test at high speed can be accurately determined. Can be measured. Therefore, a test that classifies the operating speed of the IC under test into several categories and a test as to how fast the IC under test can reliably respond to a high-speed signal can be performed. Test equipment can be provided. In addition, the test time can be reduced.

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Abstract

L'invention concerne un appareil et un procédé de mesure d'instabilité tout en régulant la synchronisation d'un signal d'horloge sur un point de mesure d'instabilité en un temps court. L'appareil comprend un circuit d'amincissement (22) destiné à limiter le nombre de signaux d'horloge passant dans un chemin d'alimentation en signaux d'horloge à partir d'une partie génératrice de rythme (12) d'un numériseur d'échantillonnage comprenant une tête d'échantillonnage (11), la partie génératrice de rythme (12) et un numériseur (13), vers le numériseur et un circuit de déclenchement (21) afin de réguler l'opération d'amincissement du circuit d'amincissement entre l'extrémité de sortie de la tête d'échantillonnage et l'extrémité d'entrée du circuit d'amincissement. Dans le circuit de déclenchement, le niveau (amplitude) d'un signal par rapport auquel l'instabilité est mesurée et les données de bord de la forme d'onde du signal sont présents, et un procédé d'échantillonnage équivalent est appliqué au numériseur d'échantillonnage.
PCT/JP2000/008076 1999-11-19 2000-11-16 Appareil et procede de mesure d'instabilite et appareil de controle pour circuit integre a semi-conducteur equipe de l'appareil de mesure d'instabilite WO2001038888A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2001540385A JP3609780B2 (ja) 1999-11-19 2000-11-16 ジッタ測定装置及び方法、並びにこのジッタ測定装置を備えた半導体集積回路試験装置
DE10083886T DE10083886T1 (de) 1999-11-19 2000-11-16 Jittermessgerät und -verfahren sowie das Jittermessgerät aufweisendes Halbleiter-IC-Testgerät

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Application Number Priority Date Filing Date Title
JP33038999 1999-11-19
JP11/330389 1999-11-19

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WO2001038888A1 true WO2001038888A1 (fr) 2001-05-31

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DE (1) DE10083886T1 (fr)
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JP2004144748A (ja) * 2002-10-22 2004-05-20 Agilent Technol Inc アイ・ダイヤグラム解析用ディジタル波形の効率的サンプリング方法及び装置

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Publication number Priority date Publication date Assignee Title
US7856330B2 (en) 2006-02-27 2010-12-21 Advantest Corporation Measuring apparatus, testing apparatus, and electronic device

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JPH08179013A (ja) * 1994-12-26 1996-07-12 Hitachi Ltd Ｌｓｉテスタ
JPH08262082A (ja) * 1995-03-23 1996-10-11 Advantest Corp サンプリング・デジタイザ

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Publication number Priority date Publication date Assignee Title
JPH08179013A (ja) * 1994-12-26 1996-07-12 Hitachi Ltd Ｌｓｉテスタ
JPH08262082A (ja) * 1995-03-23 1996-10-11 Advantest Corp サンプリング・デジタイザ

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004144748A (ja) * 2002-10-22 2004-05-20 Agilent Technol Inc アイ・ダイヤグラム解析用ディジタル波形の効率的サンプリング方法及び装置

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