JPS62293736A - Integrated circuit with test circuit - Google Patents
Integrated circuit with test circuitInfo
- Publication number
- JPS62293736A JPS62293736A JP61138815A JP13881586A JPS62293736A JP S62293736 A JPS62293736 A JP S62293736A JP 61138815 A JP61138815 A JP 61138815A JP 13881586 A JP13881586 A JP 13881586A JP S62293736 A JPS62293736 A JP S62293736A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- test
- integrated circuit
- signal
- integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 56
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 abstract 4
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- 230000000644 propagated effect Effects 0.000 description 2
- 230000001902 propagating effect Effects 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
Landscapes
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
発明の詳細な説明
〔産業上の利用分野〕
本発明は集積回路の内部に試験回路を有する集積回路に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit having a test circuit inside the integrated circuit.
従来、この種の試験回路を有する集積回路は、集積回路
内部の動作を試験する機構を備えるものとなっていた。Conventionally, integrated circuits having this type of test circuit have been equipped with a mechanism for testing the internal operation of the integrated circuit.
上述した従来の集積回路は、集積回路の内部の動作のみ
を試験対象としているため、集積回路での演算結果が、
出力端子へ正確な信号値が伝播しているかどうかの試験
が行なえないという問題があり、また試験回路を持たな
い集積回路では、回路外部の試験装置を使用したり、実
使用条件下で試験しなければ、試験ができないという欠
点を有していた。In the conventional integrated circuits mentioned above, only the internal operation of the integrated circuit is tested, so the calculation results on the integrated circuit are
There is a problem in that it is not possible to test whether accurate signal values are being propagated to the output terminal, and for integrated circuits that do not have a test circuit, it is difficult to test using test equipment external to the circuit or under actual usage conditions. Without it, there was a drawback that the test could not be performed.
本発明の目的は、これらの欠点を除き、回路内部の試験
ができるようにした試験回路つき集積回路を提供するこ
とにある。An object of the present invention is to provide an integrated circuit with a test circuit which eliminates these drawbacks and allows testing of the inside of the circuit.
本発明の試験回路つき集積回路の構成は、集積回路の内
部に、回路の外部への出力を可能とし所定パターンのデ
ジタル出力をつくる試験系列信号生成回路と、回路外部
からの所定パターン信号を入力し基準信号と比較あるい
は判定を行う試験判定回路との少くとも一方を備え、こ
れら各回路を接続することにより、回路試験を行うこと
が出来るようにしたことを特徴とする。The configuration of the integrated circuit with a test circuit of the present invention includes a test series signal generation circuit that enables output to the outside of the circuit and creates a predetermined pattern of digital output, and a predetermined pattern signal inputted from outside the circuit. The present invention is characterized in that it includes at least one of a test determination circuit that performs comparison or determination with a reference signal, and by connecting these circuits, a circuit test can be performed.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例のブロック図である0本実施
例は、試験系列信号生成回路1と、試験対象回路2と、
試験結果の判定回路3とを集積回路内に含んでいる。こ
れらの試験回路1,3は集積回路の内部を試験するため
に使用され、かつ所定パターンのシリアルまたはパラレ
ル系列信号を出力する試験系列信号生成回路1の出力を
集積回路の出力端子11に出力し、入力端子10からの
入力信号を試験結果判定回路10の入力としている。こ
れより、集積回路の内部及び外部の試験を行なうことを
可能としている。FIG. 1 is a block diagram of an embodiment of the present invention. This embodiment includes a test series signal generation circuit 1, a circuit under test 2,
A test result determination circuit 3 is included in the integrated circuit. These test circuits 1 and 3 are used to test the inside of the integrated circuit, and output the output of the test sequence signal generation circuit 1, which outputs a serial or parallel sequence signal of a predetermined pattern, to the output terminal 11 of the integrated circuit. , the input signal from the input terminal 10 is input to the test result determination circuit 10. This makes it possible to perform internal and external tests on the integrated circuit.
第2図は本実施例の集積回路を使用した回路の試験を行
なう場合の一例のブロック図である。試験系列生成回路
1を有する集積回路21と、試験結果判定結果3を有す
る集積回路23とを使用し、その間に挿入さられな集積
回路22の試験を行うものである。FIG. 2 is a block diagram of an example of testing a circuit using the integrated circuit of this embodiment. An integrated circuit 21 having a test sequence generation circuit 1 and an integrated circuit 23 having a test result determination result 3 are used to test an integrated circuit 22 inserted between them.
第3図は本実施例による集積回路を使用した試験方法の
他のブロック図である。集積回路の試験系列生成回路1
から、試験結果判定回路3へ、集積回路31の外部配線
32を介して接続されている。これにより、入出力端子
へ伝播している信号の直接試験が可能となる。FIG. 3 is another block diagram of the test method using the integrated circuit according to this embodiment. Integrated circuit test sequence generation circuit 1
The integrated circuit 31 is connected to the test result determination circuit 3 via external wiring 32 of the integrated circuit 31 . This makes it possible to directly test the signals propagating to the input/output terminals.
以上説明したように、本発明は、試験系列生成回路の集
積回路の出力端子に、試験結果判定回路の入力を集積回
路の入力端にも割り当てることにより、入出力端子に正
常に信号に伝播しているかの試験を可能とする。また、
集積回路の内部だけでなく、集積回路の外部をも試験可
能とする。集積回路内部の試験回路を集積回路の外部の
試験回路としても使用することにより、試験回路の全体
を縮小できる効果もある。As explained above, the present invention allows signals to be normally propagated to the input/output terminals by assigning the input of the test result determination circuit to the output terminal of the integrated circuit of the test sequence generation circuit as well as to the input terminal of the integrated circuit. This makes it possible to test whether the Also,
It is possible to test not only the inside of an integrated circuit but also the outside of the integrated circuit. By using the test circuit inside the integrated circuit as a test circuit outside the integrated circuit, there is also the effect that the entire test circuit can be reduced in size.
第1図は本発明の一実施例のブロック図、第2図、第3
図は本実施例の集積回路を用いた二側の試験回路のブロ
ック図である。
1・・・試験系列生成回路、2・・・試験対象回路、3
・・・試験結果判定回路、10・・・入力端子、11・
・・出力端子、21・・・試験系列生成回路を有する集
積回路、22・・・試験回路のない集積回路、23・・
・試験結果判定回路を有する集積回路、31・・・集積
回路、32・・・外部配線。
第 1図FIG. 1 is a block diagram of one embodiment of the present invention, FIG.
The figure is a block diagram of a second-side test circuit using the integrated circuit of this embodiment. 1... Test sequence generation circuit, 2... Test target circuit, 3
...Test result judgment circuit, 10...Input terminal, 11.
...Output terminal, 21...Integrated circuit having test sequence generation circuit, 22...Integrated circuit without test circuit, 23...
- Integrated circuit having a test result determination circuit, 31... integrated circuit, 32... external wiring. Figure 1
Claims (1)
パターンのデジタル出力をつくる試験系列信号生成回路
と、回路外部からの所定パターン信号を入力し基準信号
と比較あるいは判定を行う試験判定回路との少くとも一
方を備え、これら各回路を接続することにより、回路試
験を行うことが出来るようにしたことを特徴とする試験
回路つき集積回路。Inside the integrated circuit, there is a test series signal generation circuit that enables output to the outside of the circuit and creates a digital output of a predetermined pattern, and a test judgment circuit that inputs a predetermined pattern signal from outside the circuit and compares it with a reference signal or makes a judgment. 1. An integrated circuit with a test circuit, characterized in that the integrated circuit includes at least one of the above circuits, and is capable of performing a circuit test by connecting each of these circuits.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61138815A JPS62293736A (en) | 1986-06-13 | 1986-06-13 | Integrated circuit with test circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61138815A JPS62293736A (en) | 1986-06-13 | 1986-06-13 | Integrated circuit with test circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62293736A true JPS62293736A (en) | 1987-12-21 |
Family
ID=15230888
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61138815A Pending JPS62293736A (en) | 1986-06-13 | 1986-06-13 | Integrated circuit with test circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62293736A (en) |
-
1986
- 1986-06-13 JP JP61138815A patent/JPS62293736A/en active Pending
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