JP3189744B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device, and more particularly, to a test circuit for a semiconductor device integrated using CMOS transistors.

[0002]

2. Description of the Related Art In a CMOS LSI, there is a method of detecting a fault from the magnitude of a static current flowing in a circuit in a stable state. Usually, IDDQ test (quiescent power
This method is called supply current test. Generally, a method of measuring the static power supply current while supplying a pattern to an LSI under test by using an external LSI tester or running the pattern to a measurement pattern. Take
For example, it is used for detecting a short-circuit failure or the like.

However, in this method, a current other than the intended static current is also measured, such as detection of a current due to switching of an output buffer and measurement of a current flowing through an input terminal with a resistor. Therefore, it is difficult to determine whether or not the LSI has a failure.

In addition, since the location (positional information) of the fault location of the internal circuit and the fault information must be propagated to the output terminal, as the circuit scale increases, the test pattern becomes longer and the test pattern becomes enormous. It takes time to create

In order to solve these problems, for example, Japanese Patent Laid-Open Publication No. Hei 6-3407 proposes a test circuit as shown in FIG. Referring to FIG. 4, the test circuit 1 includes a PMOS transistor P1 and an NMOS transistor N1 whose drain electrodes are connected to each other, and an NMOS transistor N3 whose drain electrode is connected to the gate electrode of the NMOS transistor N1. .

[0006] The binary control signal 3 input from the test switching terminal 3 is set to a high level during normal operation, and
S transistor N3 is turned on, PMOS transistor P1
Is turned off, and the ground line 6
The S transistor N1 is turned off, and the failure detection terminal 2 is set to a high impedance state.

On the other hand, when detecting a failure, the binary control signal input from the test switching terminal 3 is set to low level, the NMOS transistor N3 is turned off, the PMOS transistor P1 is turned on, and the ground line 6 is opened. Therefore, the output of the failure detection terminal 2 depends on the potential of the ground line 6. If the internal gate 4A is in a stable state and the static current is zero, the ground line 6 retains the state (ground potential) before being opened,
The failure detection terminal 2 has the potential of the power supply line 5. In addition,
In the figure, the internal gate 4A includes a PMOS transistor P2 connected in series between the power supply line 5 and the ground line 6,
It comprises an NMOS transistor N2.

If a static current is present in the internal gate 4A, the potential of the ground line 6 rises and the NMOS transistor N1 turns on, so that the potential of the failure detection terminal 2 drops below the potential of the high power supply 5. This makes it possible to know that a failure has occurred in the internal gate 4A.

[0009]

As described above, the ID
When performing a DQ test, use a CMOS LSI with an LSI tester.
When measuring the static power supply current, there is a problem that it is difficult to determine the presence or absence of a failure only by measuring the power supply current. The reason is that there is a possibility of measuring a current other than the current resulting from the failure.

In the test circuit described in Japanese Patent Application Laid-Open No. Hei 6-3407, the static current in a stable state of a normal circuit is assumed to be zero, and when a small leak current exists in the circuit, the circuit is opened. Since the potential of the ground line 6 gradually rises, the potential of the failure detection terminal 2 depends on the measurement timing. Then, when a large-scale circuit is tested, the leak current becomes a value that cannot be ignored. Consequently, even with the test circuit described in JP-A-6-3407, it is extremely difficult to judge a failure.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a test for detecting a failure with higher accuracy in consideration of a leak current in a stable state of a circuit. It is to provide a semiconductor device provided with a circuit.

[0012]

In order to achieve the above object, a semiconductor device according to the present invention comprises a semiconductor device having an internal circuit.
Equipped with a test circuit for fault detection to the ground line, Tess
In the auto mode, a static current due to a fault flows in the internal circuit.
If the test circuit detects a change in the DC voltage of the power supply wiring,
As a change in the DC voltage of the power supply wiring.
Output from the fault detection terminal as the corresponding DC potential signal
And the test circuit is connected to the ground line.
Inserted between ground potential and turned on during test mode
Current drive capability of one or more NMOS transistors
By adjusting, the flow when the internal circuit is normal
Fluctuations in the potential of the ground line due to leakage current
If the static current caused by the fault flows through the internal circuit,
In this case, it is configured so that the potential of the ground line fluctuates.
Have been. The present invention includes a first PMOS transistor and a first NMOS transistor having drains connected to each other, and a second NMOS transistor having a drain electrode connected to a gate electrode of the first NMOS transistor. A binary control signal is input to a second NMOS transistor, an inverted signal of the binary control signal is input to the first PMOS transistor, and a gate electrode of the first NMOS transistor is connected to a ground line of an internal circuit of a semiconductor chip. A test circuit configured to extract an output signal from the drain electrodes of the first PMOS transistor and the first NMOS transistor to the outside of the semiconductor chip;

[0013]

Embodiments of the present invention will be described below. The semiconductor device of the present invention, in a preferred embodiment thereof, includes a test circuit for detecting a failure in the ground line of the internal circuit, and in the test mode, when a static current due to the failure flows in the internal circuit, the test circuit includes: It is detected as a change in the DC voltage of the power supply wiring, and is output from a defect detection terminal as a DC potential signal according to the level of the change. A change in the power supply voltage due to a minute leak current of a normal internal circuit is suppressed by the NMOS transistor provided on the ground line.

In the embodiment of the present invention, the test circuit judges the level of the leak current flowing through the internal circuit in a stable state, and when a leak current occurs due to a failure of the circuit, the test circuit sets a potential outside the chip. Output as a signal change.

That is, as a feature of the embodiment of the present invention, at the time of testing, instead of opening the ground line of the internal circuit in a stable state, a minute amount is provided by an NMOS transistor inserted between the ground line and the ground potential. The ground line is driven to the ground potential with an appropriate force (current driving capability).

This NMOS transistor suppresses a change in the potential of the ground line due to a small leak current flowing in the normal circuit, and detects a change in the DC potential of the ground line only when a leak current due to a circuit failure flows. And outputs a signal having a potential corresponding to the DC current potential value. Therefore, in a CMOS LSI, the accuracy of a test for detecting a failure by measuring a power supply current is improved, and the determination of the presence or absence of a failure is facilitated.

[0017]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

Embodiment 1 FIG. 1 is a diagram showing a circuit configuration of a first embodiment of the present invention. With reference to FIG. 1, a first embodiment of the present invention
6 is provided with a test circuit 21 and an internal circuit 24
Consists of CMOS LSI circuit blocks, such as logic gates or logic circuits combining them.

The test circuit 21 includes a PMOS transistor P11 connected in series with a common drain electrode.
And an NMOS transistor N11 having a drain electrode connected to the gate electrode of the NMOS transistor N11.
The test switching terminal 23 is connected to the gate electrode of the transistor N13, and the inverted signal 28 of the test switching terminal 23 by the inverter INV1 is input to the gate electrode of the PMOS transistor P11. The gate electrode of the NMOS transistor N11 and the drain electrode of the NMOS transistor N13 are connected to the ground line 26 of the internal circuit 24 for performing a failure verification. PMOS transistor P1
1 and the drain electrode of the NMOS transistor N11 are connected to the failure detection terminal 22, from which a test result is output. The inverter INV1 includes a CMOS inverter composed of a series-connected PMOS transistor P12 and NMOS transistor N12 that commonly connects a gate electrode to input an input signal and commonly connects drain electrodes to each other to output an output signal. .

In this embodiment, during normal operation, the test switching terminal 23 is set to low level, the NMOS transistor N13 is turned off, and the PMOS transistor P13 is turned off.
11 is also turned off. Further, the ground potential is input to the terminal 27, the NMOS transistor N11 is turned off, and the failure detection terminal 22 enters a high impedance state.

At the time of a test for detecting a failure, the test switching signal 23 is set to a high level and the NMOS transistor N
13 and the PMOS transistor P11 are turned on.
When the internal circuit 24 is in a stable state, the terminal 27 is opened, and the ground line 26 is driven to the ground potential by the NMOS transistor N13. NMO
The drive capability of the S transistor N13 is determined from the value of the leak current flowing through the normal internal circuit 24, and is set so that a potential change occurs in the ground line 26 with respect to a large leak current flowing due to a circuit failure.

When the internal circuit 24 is normal, even if a small leak current flows through the ground line 26, the NMO
The ground line 26 is kept at a low level by the drive capability of the S transistor N13, the NMOS transistor N11 is turned off, and the defect detection terminal 22 becomes the potential of the high potential power supply line 25.

On the other hand, when a large leak current flows due to the failure of the internal circuit 24, the potential of the ground line 26 rises above the ground potential according to the magnitude of the current value, and When the potential exceeds the threshold voltage of the NMOS transistor N11, the NMOS transistor N
11 turns on, and the failure detection terminal 22 is connected to the high-potential power line 2
5 lower than the potential. This makes it possible to know that the internal circuit 24 has failed.

[Embodiment 2] FIG. 2 is a diagram showing a circuit configuration of a second embodiment of the present invention. Referring to FIG. 2, a second embodiment of the present invention includes a plurality of NMOS transistors N13 of the first embodiment shown in FIG. 1 arranged in parallel and a decoder. Is the first
This is the same as the embodiment.

The plurality of NMOS transistors N13A, N13B and N13C arranged in parallel are provided for the purpose of making the allowable leak current variable.

A plurality of NMOS transistors N13A, N13B, N1 arranged in parallel by the decoder 30 which receives the decoder control signal 33 and the test switching signal 23 as inputs.
By controlling the potential applied to the 3C gate electrode, it is possible to perform a test according to conditions such as a temperature and a high power supply potential, and to determine an optimum allowable current. Here, three NMOS transistors N13A, N13B, and N13C are used to make the allowable leak current variable, but any number may be used as needed.

Third Embodiment FIG. 3 is a diagram showing a circuit configuration of a third embodiment of the present invention. Referring to FIG. 3, in a third embodiment of the present invention, a plurality of test circuits 21 having the configuration of the first embodiment or the second embodiment are provided, and a decoder control signal 36 and test switching are provided. A decoder 35 to which the signal 23 is input is provided. The decoder 35 selects a circuit to be tested from the internal circuits 24B, 24C, and 24D, and outputs the selected circuit from the non-detection terminal 22. As a result, it is possible to narrow down a part of the internal circuit that has failed to some extent.

[0028]

As described above, according to the present invention,
The following effects are obtained.

A first effect of the present invention is that, in a test for detecting a circuit fault by detecting a static current when the circuit is in a stable state, a fluctuation in the potential of the ground line due to a leak current flowing through a normal circuit is suppressed. By doing so, the accuracy of failure detection is improved.

A second effect of the present invention is that when a failure is detected, the ground line is driven by an NMOS transistor having an appropriate smile current drive capability, thereby enabling failure detection independent of measurement timing. .

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of a first embodiment of the present invention.

FIG. 2 is a diagram showing a circuit configuration of a second embodiment of the present invention.

FIG. 3 is a diagram showing a circuit configuration of a third embodiment of the present invention.

FIG. 4 is a diagram showing a circuit configuration of a conventional test circuit.

[Description of Signs] 1,21 test circuit 2,22 failure detection terminal 3,23 test switching terminal 4,24,24B, 24C, 24D test switching terminal 5,25 high potential power supply line 6,26 ground line 7,27 terminal 9, 29 Ground potential 30, 35 Decoder 33, 36 Decoder control signals N1, N11, N12, N13, N13B, N13C,
N13D, N2, N3 N-channel transistors P11, P12, P13, P1, P2, P3 P-channel transistors

Claims (7)

(57) [Claims] A test circuit for detecting a failure is provided on a ground line of an internal circuit of a semiconductor chip. In a test mode, when a static current due to a failure flows through the internal circuit, the test circuit operates by a direct current of a power supply wiring. Detected as a voltage change, and output from a fault detection terminal as a DC potential signal according to the level of the DC voltage change of the power supply wiring, and the test circuit is connected between the ground line and a ground potential. among the plurality of NMOS transistors that will be inserted, by one or more of NMOS transistors that are turned on in the test mode, suppressing the change in the potential of the ground line by a leakage current the internal circuit flows normal case, so that is configured, furthermore, decodes and inputs the decoded control signal, said decoding binding
The ground line and the ground of the test circuit
A plurality of NMOS transistors inserted between the plurality of NMOS transistors
A semiconductor device comprising a decoder circuit for controlling on / off of the data. 2. A test circuit for detecting a failure is provided on a ground line of an internal circuit of a semiconductor chip. In a test mode, when a static current due to a failure flows through the internal circuit, the test circuit is configured to supply a direct current to a power supply line. Detected as a voltage change, and output from a fault detection terminal as a DC potential signal according to the level of the DC voltage change of the power supply wiring, and the test circuit is connected between the ground line and a ground potential. The current drive capability of one or a plurality of NMOS transistors inserted and turned on in the test mode suppresses fluctuations in the potential of the ground line due to leakage current flowing when the internal circuit is normal, causing a failure in the internal circuit. Wherein the potential of the ground line fluctuates when a static current flows through the semiconductor device. 3. The ground line is connected in series to a power supply potential and a ground potential, and a drain is commonly connected to a gate electrode of an NMOS transistor of the PMOS transistor and the NMOS transistor connected to the failure detection terminal; , in the test mode, the a PMOS transistor in an on state, according to claim 1 or, characterized in that
3. The semiconductor device according to 2 . 4. A decoding control signal is input and decoded.
3. The semiconductor device according to claim 2, further comprising a decoder circuit that controls on / off of the plurality of NMOS transistors based on the decoding result. 5. The test circuit according to claim 2, wherein :
3. The semiconductor device according to claim 1, wherein the semiconductor device is switched to a normal operation or a test mode . 6. A test circuit comprising: a first PMOS transistor having a source electrode connected to a high power supply potential; a drain electrode connected to a drain electrode of the first PMOS transistor; and a source electrode connected to a ground potential. and a first NMO S transistor includes a second NMOS transistor having a source electrode connected to the gate electrode of the drain electrode of the first NMOS transistor is connected to the ground potential, a of the second NMOS transistor A binary control signal is input to a gate electrode, an inverted signal of the binary control signal is input to a gate electrode of the first PMOS transistor, and a gate electrode of the first NMOS transistor is connected to the ground line of the internal circuit. And the first PMOS transistor and the first NM
OS and the drain electrode of the transistor is configured to take out an output signal to the outside of the semiconductor chip during normal operation, the ground potential of the ground line of said internal circuit, said first NMOS transistor and the first PMO S 3. The semiconductor device according to claim 2, wherein both of the transistors are turned off, and in the test mode, the second NMOS transistor and the first PMOS transistor are turned on by the binary control signal. . 7. A test circuit comprising: a first PMOS transistor having a source electrode connected to a high power supply potential; a drain electrode connected to a drain electrode of the first PMOS transistor; and a source electrode connected to a ground potential. and a first NMO S transistor, the second to m to the commonly connected source electrode to the gate electrode of the drain electrode of the first NMOS transistor are commonly connected to the ground potential (where, m is a predetermined three or more integer)
And a binary control signal output from the decoder circuit is input to a gate electrode of each of the second to m-th NMOS transistors. A gate electrode of the first PMOS transistor is An inverted signal of the binary control signal supplied to the gate electrode of the second NMOS transistor is input, the gate electrode of the first NMOS transistor is connected to the ground line of the internal circuit, and the first PMOS transistor And the first NM
OS and the drain electrode of the transistor is configured to take out an output signal to the outside of the semiconductor chip during normal operation, the ground potential of the ground line of said internal circuit, said first NMOS transistor and the first PMO S In the test mode, the transistors are turned off. The output of the decoder circuit which receives the decode control signal and a test switching signal for switching between the test mode and the normal operation causes the second to m-th NMOS transistors to be turned on. 2. The semiconductor device according to claim 1, wherein said first PMOS transistor is selectively turned on and said first PMOS transistor is set on.