JPH0727816A - Circuit device for evaluating characteristic of semiconductor transistor and semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To provide a circuit device for evaluating characteristics of semiconductor transistors which uses a self-oscillating circuit and can evaluate the characteristics of semiconductor transistors in conformity with the actual condition of the self-oscillating circuit. CONSTITUTION:The output terminal of a NAND logic circuit 110-l in a certain stage is connected to the gates of a p-MOSFET 103 and n-MOSFET 101 which are the input terminals of a NAND logic circuit 110-2 in the next stage and the gates of an n-MOSFET 102 and p-MOSFET 104 constituting the circuit 110-2 are connected to the high-potential side of a power supply voltage. Then, the output terminal of the NAND logic circuit 110-n in the final stage is connected to a pad 106 for measurement and, at the same time, to the input terminal of the initial stage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for evaluating characteristics of a circuit composed of semiconductor transistors,
The present invention relates to a semiconductor transistor characteristic evaluation circuit device that constitutes a self-oscillation circuit, and a semiconductor integrated circuit device including the semiconductor transistor characteristic evaluation circuit device.

[0002]

2. Description of the Related Art The following is one of the methods for evaluating the characteristics of semiconductor transistors in a circuit manner. As shown in FIG. 6, an n-channel MOS field effect transistor (hereinafter referred to as n-MOSFET) 10 and a p-channel MOS
Type field effect transistor (hereinafter referred to as p-MOSFET) 20 is used to configure a CMOS inverter circuit 30, and the output terminal of the first-stage inverter circuit 30 is connected to the input terminal of the second-stage inverter circuit 31. Are connected so that the total number of stages is an odd number, and the output terminal of the final stage inverter circuit is connected to the first stage inverter circuit 3
In this method, the self-oscillation circuit 40 is configured by connecting to the 0 input terminal, and the semiconductor transistor characteristic is evaluated by evaluating the oscillation frequency of the self-oscillation circuit. This evaluation method can also be used to evaluate the durability of a semiconductor transistor, and by measuring how much the oscillation frequency after self-oscillation for a certain period of time has changed from the initial oscillation frequency. The characteristic deterioration of the semiconductor transistor can be evaluated.

[0003]

When the self-oscillation circuit 40 as described above is constructed and is oscillated for a predetermined time to evaluate the durability of the semiconductor transistor, as shown in FIG. 6, the inverter circuit is constructed. N-MOSFE
Source electrode of T10 is pad 1 at ground level
07, the source electrode of the p-MOSFET 20 is connected to the pad 105 having the power supply potential (Vcc), and each potential remains constant. However, in an actual circuit, for example, in a commonly used NAND logic circuit or NOR logic circuit, the n-MOSF
The source potential of the ET or the source potential of the p-MOSFET may change in the range from the ground to the power source potential of Vcc during signal transmission. At that time, each MOSF
Since the substrate potential or well potential of ET is fixedly connected to the ground in the n-MOSFET and to Vcc in the p-MOSFET, a change in the source potential of each MOSFET causes a substrate bias effect in each MOSFET. The threshold voltage of the MOSFET will change. As described above, in the conventional evaluation circuit of the semiconductor transistor using the self-oscillation circuit, the characteristic evaluation of the semiconductor transistor cannot be performed in consideration of the substrate bias effect, that is, the characteristic evaluation according to the actual circuit cannot be performed. is there. The present invention has been made in order to solve such a problem, and therefore provides a semiconductor transistor characteristic evaluation circuit device which is an evaluation circuit using a self-oscillation circuit and which can evaluate the characteristics of a semiconductor transistor according to an actual circuit. It is another object of the present invention to provide a semiconductor integrated circuit device including the semiconductor transistor characteristic evaluation circuit device.

[0004]

According to the present invention, a source electrode is connected to a common source electrode to which a source electrode of the first p-channel field effect transistor and the source electrode of the first p-channel field effect transistor is connected. The drain electrode is connected to the common drain electrode which is connected to the drain electrode in the channel field effect transistor,
At least one second p-channel field effect transistor connected in parallel to the first p-channel field effect transistor, and a common drain electrode side to which the drain electrodes of the first and second p-channel field effect transistors are connected Connected to the first n-channel field-effect transistor and the source of the first n-channel field-effect transistor connected in series as one connection terminal on the source electrode side of the first n-channel field-effect transistor. Substrate bias effect generating means having at least one second n-channel type field effect transistor for making the potential at the electrode higher than the low potential of the power supply voltage, the gate of the first p-channel type field effect transistor and the first n-channel type Connect to the gate of field effect transistor A second input terminal connecting the first input terminal, the gate of the second p-channel field effect transistor and the gate of the second n-channel field effect transistor forming the substrate bias effect generating means, and the common drain electrode. In the NAND logic circuit having an odd number of NAND logic circuits each having an output terminal connected to, and arranged from the first stage to the (final-1) stage, the output terminals are arranged in the next stage. Connected to the first input terminal of the NAND logic circuit, and the output terminal of the NAND logic circuit arranged in the final stage has the first input terminal of the NAND logic circuit arranged in the first stage In a semiconductor transistor characteristic evaluation circuit device connected to an input terminal, each of the first and second p-channels provided in each of the NAND logic circuits. A high potential pad to which the common source electrode and the second input terminal of the field effect transistor are connected and which is supplied with a high potential of a power supply voltage, and an output terminal provided in the NAND logic circuit arranged in the final stage. A measurement pad connected to a measuring instrument for measuring an oscillation waveform of the semiconductor transistor characteristic evaluation circuit device, and the substrate bias serving as the other connection terminal in the substrate bias effect generating means provided in each NAND logic circuit. 2n in effect generation means
A low potential pad to which a source electrode of a channel field effect transistor is connected and which is supplied with a low potential of a power supply voltage.

[0005]

[Operation] By configuring in this way, each NAN
Connecting the output terminal of the D logic circuit to the first input terminal arranged in the next stage is performed by the self-oscillation of the semiconductor transistor characteristic evaluation circuit device, and is connected to the first input terminal for the first n-th channel whose characteristics are to be evaluated. Type field effect transistor is turned on and off. Also, connecting the gate of the second n-channel field effect transistor to the high potential pad keeps the second n-channel field effect transistor always on. Therefore, when the first n-channel field effect transistor is turned on and off,
Conduction and interruption of current from the drain side to the source side of the n-channel field effect transistor are performed. One NAN
When one stage is composed of D logic circuits and such NAND logic circuits are connected in an odd number of stages, as described above, the first
Connecting the first n-channel field effect transistor whose characteristics are to be evaluated to the input terminal and connecting the gate of the second n-channel field effect transistor to the high potential pad has the following effects. That is, after the first n-channel field effect transistor is turned on and its source side is connected to the low potential pad through the second n-channel field effect transistor, the potential of the output terminal is changed from the high (H) level by self-oscillation. When changing to the low (L) level, the source side potential of the first n-channel type field effect transistor is grounded due to the potential drop due to the resistance of the second n-channel type field effect transistor which constitutes the substrate bias effect generating means. The potential is higher than the existing substrate potential. Therefore, the substrate bias effect is generated in the first n-channel field effect transistor, and the operating characteristics of the n-channel field effect transistor can be measured in a state close to that used in an actual circuit. Also, by replacing the NAND logic circuit described above with a NOR logic circuit, it becomes possible to measure the operating characteristics of the p-channel field effect transistor in the same operation as described above.

[0006]

First Embodiment One embodiment of the semiconductor transistor characteristic evaluation circuit device of the present invention will be described below with reference to the drawings. FIG. 1 shows a semiconductor transistor characteristic evaluation circuit device of a type in which one stage is composed of a 2-input NAND logic circuit and is connected to odd stages. The configuration itself of the NAND logic circuit forming one stage is a generally known configuration. That is, the n-channel field-effect transistor 101, which corresponds to the first n-channel field-effect transistor and whose operating characteristics are desired to be evaluated, and the n-channel field-effect transistor which constitutes the substrate bias effect generating means.
The channel field effect transistor 102 is connected in series. A p-channel field effect transistor 103 corresponding to the first p-channel field effect transistor and a p-channel field effect transistor 104 corresponding to the second p-channel field effect transistor are connected in parallel. Then, the p-channel field effect transistor 10
The common drain electrode side to which the drain electrodes in 3, 104 are connected and the n-channel field effect transistor 1
The drain electrode side of 01 is connected to form one NAND logic circuit. The NAND logic circuit configured as described above is connected as described below and connected so that the total number is an odd number of stages, and the semiconductor transistor characteristic evaluation circuit device in this embodiment is configured. In the NAND logic circuits in each stage, the corresponding transistors have the same reference numerals as shown in the figure.

The above p-channel field effect transistor 1
03 and 104 and the n-channel field-effect transistor 101 common to the n-channel field-effect transistor 101 are provided in a NAND logic circuit arranged in the next stage as an output terminal of one NAND logic circuit.
And a first input terminal to which the gate of the p-channel field effect transistor 103 is connected. Similarly, the output terminal of the previous stage is connected to the first input terminal of the next stage, and the output terminal of the NAND logic circuit 110-n of the final stage is connected to the first input terminal of the NAND logic circuit 110 of the first stage. With this ring configuration, and because the number of NAND logic circuits connected is odd, the circuit performs self-oscillation by supplying a predetermined potential to the circuit, as described below. An H level signal and an L level signal are alternately supplied from the output terminal of each stage to the first input terminal of the next stage.

Further, the second input terminal connecting the gates of the n-channel field effect transistor 102 and the p-channel field effect transistor 104 in each NAND logic circuit and the p-channel field effect transistor 10 are connected.
Each source electrode side of 3, 104 is connected to the high potential pad 105 for supplying the high potential (Vcc) of the power supply voltage when oscillating the circuit connected in the ring shape as described above. Further, the source side of the n-channel field effect transistor 102 provided in each NAND logic circuit is connected to the low potential pad 107 to which the low potential of the power supply voltage is supplied. The output terminal of the NAND logic circuit at the final stage is also a measurement pad 1 for connecting an oscilloscope when observing the oscillation waveform of the circuit and obtaining the oscillation frequency.
06 is connected.

The operation of the semiconductor transistor characteristic evaluation circuit device thus configured will be described below. Focusing on the NAND logic circuit portion, the n-channel field effect transistor 102 and the p-channel field effect transistor 1
Since the gate of 04 is connected to the high potential pad 105, the n-channel field effect transistor 102 is always in the ON state, and the p-channel field effect transistor 1
04 is always off. Also, taking the NAND logic circuit 110-2 as an example, the signal level at the output terminal 120 of the NAND logic circuit 110-1 changes to H and L due to self-oscillation as described above, but the output terminal 120
, The n-channel field-effect transistor 101 is in the on state, the p-channel field-effect transistor 103 is in the off state, as described above.
Since the channel type field effect transistor 102 is always on and the p channel type field effect transistor 104 is always off, the output terminal 130 in the NAND logic circuit 110-2 is via the n channel type field effect transistors 101 and 102. Since it is connected to the low potential pad 107, the signal level of the output terminal 130 becomes L level.

On the other hand, when the signal level of the output terminal 120 is L level, the n-channel field effect transistor 1
01 is an off state, p-channel field effect transistor 1
03 is an on state, the n-channel field effect transistor 102 is always on, and the p-channel field effect transistor 104 is always off, as described above. Therefore, the output terminal 13 of the NAND logic circuit 110-2 is
0 is connected to the high potential pad 105 via the p-channel field effect transistor 103, and the output terminal 1
The signal level of 30 becomes H level. NAN like this
The D logic circuit performs a normal inverter operation of outputting a potential that is the inverse of the input potential. Since such NAND logic circuits are connected in odd stages, the high potential pad 10
By applying a high potential of the power supply voltage to 5, the semiconductor transistor characteristic evaluation circuit device causes self-oscillation. The portion that substantially performs the inverter operation during such oscillation is a circuit portion including the n-channel field effect transistor 101 and the p-channel field effect transistor 103.

When self-oscillation occurs in this way,
For example, when the signal level at the output terminal 130 changes from the H level to the L level, that is, when the n-channel field effect transistor 101 changes from the ON state to the OFF state, the source side 101a of the n-channel field effect transistor 101. Due to the potential drop of the n-channel field effect transistor 102, the potential does not completely reach the potential of the low potential pad 107, that is, the ground potential, that is, the grounded substrate potential, and is somewhat higher than the substrate potential. It becomes a potential. Therefore, a reverse bias voltage is applied between the source side 101a of the n-channel field effect transistor 101 and the substrate on which the n-channel field effect transistor 101 is formed, and the n-channel field effect transistor 101 is formed. The substrate bias effect will act on.

Therefore, in the semiconductor transistor characteristic evaluation circuit device of the present embodiment, a measuring instrument for measuring the operation characteristic is connected to the measurement pad 106 and the semiconductor transistor characteristic evaluation circuit device is oscillated to make the actual state of the circuit. It is possible to evaluate durability of the n-channel field effect transistor in a similar situation.

Although the NAND logic circuit has two inputs in the above-described embodiment, the present invention is not limited to this, and a semiconductor transistor characteristic evaluation circuit device provided with three or more input terminals is constructed as shown in FIG. May be. In addition, in FIG. 2, when four input terminals are provided, N of the first stage, the second stage, and the last stage
Only the AND logic circuit is shown. Further, the same components as those shown in FIG. 2 are designated by the same reference numerals, and the description thereof will be omitted. As the configuration of the NAND logic circuit, the common source electrode to which the source electrodes of the p-channel field effect transistors 103 and 104 are connected and the p-channel field effect transistors 103 and 10 are added every time the number of input terminals increases.
The number of p-channel field effect transistors to which the source electrode and the drain electrode are respectively connected is increased by one to the common drain electrode to which the four drain electrodes are connected, and in the case of four input terminals, p-channel field effect transistors 303 and 30
4 is further connected. In addition, each time the number of input terminals increases, the number of second n-channel type field effect transistors constituting the substrate bias effect generating means connected in series to the n-channel type field effect transistor 101 increases by one.
In the case of an input terminal, n connected in series in the case of 2 inputs
In addition to the channel type field effect transistor 102, n channel type field effect transistors 301 and 302 are connected in series. Then, similarly to the case described above, the gates of the p-channel field effect transistor 103 and the n-channel field effect transistor 101 are connected to form a first input terminal, and the p-channel field effect transistors 104 and 30 are formed.
3,304 and n-channel field effect transistor 10
2, 301, 302 are connected to the gates to form a second input terminal.
A common drain electrode of 3, 104, 303, 304 and the n-channel field effect transistor 101 is used as an output terminal. Other configurations are basically two input terminal N shown in FIG.
The explanation is omitted because it is the same as the case of the AND logic circuit.

NAN having four input terminals configured as described above
The semiconductor transistor characteristic evaluation circuit device composed of the D logic circuit also operates in the same manner as the semiconductor transistor characteristic evaluation circuit device composed of the NAND logic circuit of the two-input terminal described above, and the n-channel field effect transistor
01 operation characteristic evaluation can be performed. In addition, when three or more input terminals are provided, compared to the case of two input terminals, n
Since more n-channel type field effect transistors are connected in series on the source side of the channel type field effect transistor 101, the n channel type field effect transistor 10 is caused by the potential drop of these transistors.
The difference between the source-side potential of 1 and the substrate potential becomes large, and a larger substrate bias effect can be exerted on the n-channel field effect transistor 101.

Second Embodiment Next, FIG. 3 shows a semiconductor transistor characteristic evaluation circuit device of a type in which one stage is composed of a 2-input NOR logic circuit and is connected to odd stages. N that constitutes one step
The configuration itself of the OR logic circuit is a generally known configuration. That is, a p-channel type field-effect transistor 203 corresponding to the first p-channel type field-effect transistor, whose operation characteristics are desired to be evaluated, and a p-channel type field-effect transistor constituting the substrate bias effect generating means. Type field effect transistor 2
04 and 04 are connected in series. Further, an n-channel field effect transistor 201 corresponding to the first n-channel field effect transistor and an n-channel field effect transistor 202 corresponding to the second n-channel field effect transistor 202.
And are connected in parallel. Then, the common drain electrode side to which the drain electrodes of the n-channel field effect transistors 201 and 202 are connected and the drain electrode side of the p-channel field effect transistor 203 are connected to form one NOR logic circuit. N configured in this way
The OR logic circuits are connected as described below and connected so that the total number thereof is an odd number of stages, and the semiconductor transistor characteristic evaluation circuit device in the second embodiment is configured.
In the NOR logic circuit in each stage, the corresponding transistors are designated by the same reference numerals as shown in the figure.

The above n-channel field effect transistor 2
01, 202 and the common drain electrode side of the p-channel type field effect transistor 203 have one-stage NO
A p-channel field effect transistor 20 provided in a NOR logic circuit arranged in the next stage as an output terminal of the R logic circuit
It is connected to the first input terminal which connects the gates of the 3 and n-channel field effect transistors 201. Similarly, the output terminal of the previous stage is connected to the first input terminal of the next stage, and the output terminal of the NOR logic circuit 210-n of the final stage is connected to the first input terminal of the NOR logic circuit 210-1 of the first stage. It With this ring configuration, and since the number of NOR logic circuits connected is odd, the circuits perform self-oscillation as in the case of the NAND logic circuit described above, and H from the output terminal in the above to the first input terminal in the next stage
The level signal and the L level signal are supplied alternately.

Further, p in each NOR logic circuit
A second connection of the gates of the channel field effect transistor 204 and the n channel field effect transistor 202
Input terminal and n-channel field effect transistor 20
Each source electrode side of 1, 202 is connected to the low potential pad 107. Further, the source side of the p-channel field effect transistor 204 provided in each NOR logic circuit is connected to the high potential pad 105. Also, the last N
The output terminal of the OR logic circuit 210-n is connected to the measurement pad 106 as in the case of the first embodiment.

The operation of the semiconductor transistor characteristic evaluation circuit device thus constructed will be described below. Focusing on the NOR logic circuit portion, the p-channel field effect transistor 204 and the n-channel field effect transistor 20 are shown.
Since the gate of 2 is connected to the low potential pad 107, the p-channel field-effect transistor 202 is always in the ON state, and the n-channel field-effect transistor 20.
4 is always off. Also, for example, NOR logic circuit 2
Taking 10-2 as an example, the signal level at the output terminal 220 of the NOR logic circuit 210-1 changes to H and L due to self-oscillation as described above, but when the signal level at the output terminal 220 is at the H level, The p-channel field effect transistor 203 is off, the n-channel field effect transistor 201 is on, the p-channel field effect transistor 204 is always on, and the n-channel field effect transistor 202 is always off, as described above. Therefore, the output terminal 230 in the NOR logic circuit 210-2 is the n-channel field effect transistor 201.
Therefore, the signal level of the output terminal 230 becomes L level.

On the other hand, when the signal level of the output terminal 220 is L level, the p-channel field effect transistor 2 is used.
03 is an ON state, n-channel field effect transistor 2
01 is an off state, the p-channel field effect transistor 204 is always on, and the n-channel field effect transistor 202 is always off as described above. Therefore, the output terminal 230 of the NOR logic circuit 210-2 is
Is connected to the high potential pad 105 through the p-channel field effect transistors 203 and 204, and the signal level of the output terminal 130 becomes H level. In this way, the NOR logic circuit performs a normal inverter operation of outputting a potential that is the inverse of the input potential. NOR like this
Since the logic circuits are connected in odd stages, high potential pad 1
When a high potential of the power supply voltage is applied to 05, the semiconductor transistor characteristic evaluation circuit device causes self-oscillation. The portion that performs a substantial inverter operation during such oscillation is p
It is a circuit portion composed of a channel type field effect transistor 203 and an n channel type field effect transistor 201.

When self-oscillation occurs in this way,
For example, when the signal level at the output terminal 230 changes from the L level to the H level, that is, when the p-channel field effect transistor 203 changes from the ON state to the OFF state, the source side 203a of the p-channel field effect transistor 203. Is completely reduced by the potential drop of the p-channel type field effect transistor 204 which constitutes the substrate bias effect generating means.
That is, it does not match the high potential of the power supply voltage, that is, the substrate potential connected to the high potential, and becomes a potential slightly lower than the substrate potential. Therefore, a reverse bias voltage is applied between the source side 203a of the p-channel field effect transistor 203 and the semiconductor substrate on which the p-channel field effect transistor 203 is formed, and the p-channel field effect transistor is formed. The substrate bias effect acts on 203.

Therefore, in the semiconductor transistor characteristic evaluation circuit device of the second embodiment, by connecting a measuring instrument for measuring the operation characteristic to the measurement pad 106 and causing the semiconductor transistor characteristic evaluation circuit device to oscillate, the circuit is actually measured. The durability of the p-channel field effect transistor can be evaluated in a state close to the state.

In the second embodiment, the NOR logic circuit has two inputs. However, the NOR logic circuit is not limited to this, and the configuration shown in FIG. 4 allows the semiconductor transistor characteristic having three or more input terminals to be provided. An evaluation circuit device can also be constructed. Incidentally, FIG. 4 shows a case where four input terminals are provided.

Further, a semiconductor transistor characteristic evaluation circuit device having the configuration shown in the first or second embodiment is
It may be mounted on a part of a semiconductor chip in which a semiconductor integrated circuit having a certain function is formed. That is, as shown in FIG. 5, the semiconductor transistor characteristic evaluation circuit device 403 described in the first embodiment is formed in a part of the semiconductor chip 401 in which the semiconductor integrated circuit 402 is formed, and the semiconductor transistor characteristic evaluation circuit is formed. The high-potential pad 105, the measurement pad 106, and the low-potential pad 107, which are provided in the device, are formed on the semiconductor chip 401.
Although these pads 105 to 107 are provided separately from the pads connected to the semiconductor integrated circuit 402 in FIG. 5, they should be shared with the pads that supply power for driving the semiconductor integrated circuit 402. Good.

With such a configuration, when the semiconductor integrated circuit 402 is driven, the semiconductor transistor characteristic evaluation circuit device 403 is also driven at the same time, and the transistor characteristic evaluation in the semiconductor transistor characteristic evaluation circuit device 403 is performed by the measurement pad 106. The characteristics of the transistors included in the semiconductor integrated circuit 402 can be easily evaluated at any time by monitoring via the.

[0025]

As described above in detail, according to the present invention, the first n-channel field effect transistor whose characteristic is to be evaluated is connected to the first input terminal, and the gate of the second n-channel field effect transistor is connected to the high potential pad. The following effects are brought about by the connection. That is, after the first n-channel field effect transistor is turned on and its source side is connected to the low potential pad through the second n-channel field effect transistor, the potential of the output terminal is changed from H level to L level by self-oscillation. When changing, the source side potential of the first n-channel type field effect transistor is higher than the grounded substrate potential due to the potential drop due to the resistance of the second n-channel type field effect transistor which constitutes the substrate bias effect generating means. It becomes an electric potential. Therefore, the substrate bias effect is generated in the first n-channel field effect transistor, and the operating characteristics of the n-channel field effect transistor can be measured in a state close to that used in an actual circuit. Also, by replacing the NAND logic circuit described above with a NOR logic circuit, it becomes possible to measure the operating characteristics of the p-channel field effect transistor in the same operation as described above.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration in a first embodiment of a semiconductor transistor characteristic evaluation circuit device of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a semiconductor transistor characteristic evaluation circuit device in the case where the number of input terminals of the NAND logic circuit in the first embodiment is four, for example.

FIG. 3 is a circuit diagram showing a configuration of a semiconductor transistor characteristic evaluation circuit device according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a semiconductor transistor characteristic evaluation circuit device in the case where the number of input terminals of the NOR logic circuit in the second embodiment is four, for example.

FIG. 5 is a diagram showing a case where the semiconductor transistor characteristic evaluation circuit device of the present invention is mounted on a semiconductor chip forming a semiconductor integrated circuit.

FIG. 6 is a circuit diagram showing a configuration of a conventional semiconductor transistor characteristic evaluation circuit device.

[Explanation of symbols]

101, 102 ... N-channel field effect transistor,
103, 104 ... P-channel field effect transistor,
110-1, 110-2, 110-3, 110-n ... N
AND logic circuit, 105 ... High potential pad, 106 ... Measurement pad, 107 ... Low potential pad, 201, 202 ... N
Channel type field effect transistors 203, 204 ... P
Channel type field effect transistors, 210-1 and 210
-2, 210-3, 210-n ... NOR logic circuit, 40
1 ... Semiconductor chip, 402 ... Semiconductor integrated circuit, 403 ...
Semiconductor transistor characteristic evaluation circuit device.

Claims (6)

[Claims] 1. A source electrode is connected to a common source electrode connected to a first p-channel field effect transistor and a source electrode in the first p-channel field effect transistor, and a drain electrode in the first p-channel field effect transistor. A drain electrode is connected to a common drain electrode connected to the first p-channel field effect transistor, and at least one second p-channel field effect transistor connected in parallel to the first p-channel field effect transistor; and the first and second p-channel field effect transistors. A first n-channel type field effect transistor which is connected to a common drain electrode side to which each drain electrode of the effect transistor is connected and whose operation characteristics are evaluated, and a series connection as one connection terminal on the source electrode side of the first n-channel type field effect transistor. Connected to the first
Substrate bias effect generating means having at least one second n-channel type field effect transistor for making the potential at the source electrode of the n-channel type field effect transistor higher than the low potential of the power supply voltage, and the first p-channel type field effect transistor. A first input terminal connecting the gate of the first n-channel field effect transistor to the gate of the first n-channel field effect transistor, the gate of the second p-channel field effect transistor and the second n-channel field effect transistor forming the substrate bias effect generating means. One NAND logic circuit having a second input terminal connected to the gate of the above and an output terminal connected to the common drain electrode is arranged in odd stages and arranged from the first stage to the (final-1) stage. In the NAND logic circuit, the NAN in which the output terminal is arranged in the next stage Connected to the first input terminal provided in the logic circuit, and connected to the first input terminal provided in the NAND logic circuit arranged in the first stage in the output terminal provided in the NAND logic circuit arranged in the final stage In the semiconductor transistor characteristic evaluation circuit device according to the present invention, the common source electrode and the second input terminal in the first and second p-channel field effect transistors provided in each NAND logic circuit are connected, and a high potential of a power supply voltage And a measurement pad connected to the output terminal provided in the NAND logic circuit arranged in the final stage and connected to a measuring instrument for measuring the oscillation waveform of the semiconductor transistor characteristic evaluation circuit device. , The other connection terminal in the substrate bias effect generating means provided in each NAND logic circuit Comprising the substrate bias effect generating means in the 2n-channel field-effect transistor a source electrode connected, the semiconductor transistor characteristic evaluation circuit unit, wherein the low-potential power supply voltage and a low potential pads to be supplied. 2. The low potential pad is connected to a substrate or a well forming the n-channel field effect transistor, and the high potential pad is connected to a substrate or a well forming the p-channel field effect transistor. The
The semiconductor transistor characteristic evaluation circuit device according to claim 1. 3. A first n-channel field effect transistor, a source electrode connected to a common source electrode connected to a source electrode in the first n-channel field effect transistor, and a drain electrode in the first n-channel field effect transistor. A drain electrode is connected to a common drain electrode to which is connected, and at least one second n-channel field effect transistor connected in parallel to the first n-channel field effect transistor; and the first and second n-channel field effect transistors. A first p-channel type field effect transistor which is connected to a common drain electrode side to which each drain electrode of the effect transistor is connected and whose operation characteristics are evaluated, and a series connection as one connection terminal on the source electrode side of the first p-channel type field effect transistor Connected to the first
Substrate bias effect generating means having at least one second p-channel type field effect transistor for making the potential at the source electrode of the p-channel type field effect transistor lower than the high potential of the power supply voltage, and the first n-channel type field effect transistor. A second input terminal connecting the gate of the second p-channel field effect transistor to the gate of the first p-channel field effect transistor, the gate of the second n-channel field effect transistor and the second p-channel field effect transistor forming the substrate bias effect generating means. An odd number of NOR logic circuits each having a second input terminal connected to the gate and an output terminal connected to the common drain electrode and arranged from the first stage to the (final-1) stage. In the NOR logic circuit, the NOR logic in which the output terminals are arranged in the next stage Connected to the first input terminal provided in the road, in the above output terminal provided in the NOR logic circuit arranged in the final stage the first included in the NOR logic circuit arranged in a first stage
In a semiconductor transistor characteristic evaluation circuit device connected to an input terminal, the common source electrode and the second input terminal in the first and second n-channel field effect transistors provided in each NOR logic circuit are connected, and a power supply is connected. A low potential pad to which a low potential of voltage is supplied is connected to a measuring instrument which is connected to the output terminal of the NOR logic circuit arranged in the final stage and which measures the oscillation waveform of the semiconductor transistor characteristic evaluation circuit device. The measurement pad is connected to the source electrode of the second p-channel field effect transistor in the substrate bias effect generating means, which serves as the other connecting terminal of the substrate bias effect generating means provided in each NOR logic circuit, and the power supply voltage is high. And a high potential pad to which a potential is supplied. Njisuta characterization circuit device. 4. The low potential pad is connected to a substrate or a well forming the n-channel field effect transistor, and the high potential pad is connected to a substrate or a well forming the p-channel field effect transistor. The
The semiconductor transistor characteristic evaluation circuit device according to claim 3. 5. A semiconductor integrated circuit device comprising the semiconductor transistor characteristic evaluation circuit device according to claim 1. 6. A semiconductor integrated circuit device comprising the semiconductor transistor characteristic evaluation circuit device according to claim 3.