JPS6116657U - Digital data acquisition device - Google Patents

Digital data acquisition device

Info

Publication number
JPS6116657U
JPS6116657U JP3306584U JP3306584U JPS6116657U JP S6116657 U JPS6116657 U JP S6116657U JP 3306584 U JP3306584 U JP 3306584U JP 3306584 U JP3306584 U JP 3306584U JP S6116657 U JPS6116657 U JP S6116657U
Authority
JP
Japan
Prior art keywords
data
digital data
data acquisition
acquisition device
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3306584U
Other languages
Japanese (ja)
Inventor
光司 吉村
隆夫 野内
信一 岡部
敏夫 小沢
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP3306584U priority Critical patent/JPS6116657U/en
Publication of JPS6116657U publication Critical patent/JPS6116657U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はDIの回路図、第2図はDI回路のブロック図
、第3図は従来のデータ取り込み回路の構成図、第4図
は本考案の一実施例のデータ取り込み回路図である。 1・・・入カデータ、2・・・DI回路、.3・・・ラ
ッチ回路、4・・・アドレス・デコーダ。
FIG. 1 is a DI circuit diagram, FIG. 2 is a block diagram of the DI circuit, FIG. 3 is a configuration diagram of a conventional data acquisition circuit, and FIG. 4 is a data acquisition circuit diagram of an embodiment of the present invention. 1... Input data, 2... DI circuit, . 3...Latch circuit, 4...Address decoder.

Claims (1)

【実用新案登録請求の範囲】 デジタル・データを取り込むためのD1回路、′入カデ
ータを制御するためのアドレス・デコーダ、入力したデ
ータをラッチする回路を持つデータ取り込み回路におい
て、 データ入力をビット単位に取り込み、シリアル伝送でデ
ータ処理部へ出力する手段を設けたことを特徴とするデ
ジタル・データ取り込み装置。
[Claims for Utility Model Registration] In a data capture circuit that has a D1 circuit for capturing digital data, an address decoder for controlling input data, and a circuit for latching input data, data input is performed bit by bit. A digital data capture device characterized by having means for capturing data and outputting it to a data processing unit by serial transmission.
JP3306584U 1984-03-09 1984-03-09 Digital data acquisition device Pending JPS6116657U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3306584U JPS6116657U (en) 1984-03-09 1984-03-09 Digital data acquisition device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3306584U JPS6116657U (en) 1984-03-09 1984-03-09 Digital data acquisition device

Publications (1)

Publication Number Publication Date
JPS6116657U true JPS6116657U (en) 1986-01-30

Family

ID=30535161

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3306584U Pending JPS6116657U (en) 1984-03-09 1984-03-09 Digital data acquisition device

Country Status (1)

Country Link
JP (1) JPS6116657U (en)

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