JPS6332631A - Error detecting system for data processor - Google Patents

Abstract

PURPOSE:To add microinstructions with no change of hardware and to detect an undefined instruction with addition of a small quantity of hardware, by using an error detecting circuit consisting of plural AND gates, etc. CONSTITUTION:In a branch mode to a macroinstruction microprogram module, an address difference from the head address of a microinstruction is supplied from a signal line 12. Thus the signals equal logically to '1' are outputted to signal lines 15 and 19. Then an undefined instruction error is detected by an AND gate 7 and an error processing microinstruction is started. While the signals equal logically to '1' are outputted to signal lines 15 and 16 when branching is applied to such an address where a JIN bit 41 showing the head of a microprogram is equal logically to '0'. Then a jump error is detected via an AND gate 6. In such a way, the microinstructions can be added with no change of hardware and the undefined instruction errors and the program jump errors can be detected by using those gates 6 and 7, etc. serving as error detecting circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to detection of jump errors in undefined instructions and microprograms in data processing devices, and particularly to error detection suitable for effectively utilizing control memory. Regarding the method.

[Conventional technology]

Conventional devices use a ROM as an instruction decoding unit, as described in Japanese Patent Laid-Open No. 56-108149, and enter the start address of a microprogram that performs undefined instruction error processing to detect undefined instruction errors. However, if ROM cannot be used, hard-wired logic must be assembled, and in this case, changing the start address or adding instructions requires changing the hardware.

[Problem that the invention seeks to solve]

The above-mentioned conventional technology does not take into consideration cases where ROM is not used or cases where an undefined number of microinstructions are added.If ROM cannot be used, undefined instructions are Attempting to perform detection requires a large amount of hardware, and adding instructions requires significant hardware modification.

An object of the present invention is to make it possible to add microinstructions without changing hardware, and to detect undefined instructions and jump errors in microprograms by adding a small amount of hardware.

[Means for solving problems]

The above purpose is to provide a bit indicating the beginning of a microinstruction in a microprogram, and a means for detecting undefined errors and jump errors in the microprogram by referring to the bit at the time of microprogram branching and instruction branching in the control unit of the instruction execution unit. This is achieved by having

[Effect]

The jump detection circuit and undefined instruction error detection circuit of the microprogram respectively detect the bit indicating the beginning of the microprogram used for control storage, the branch of the microprogram, and the information of branching to the macro instruction microprogram module. The jump error or undefined instruction error of the microprogram is detected when each AND condition is established.

〔Example〕

An embodiment of the present invention will be described below. Figure 2 shows the CPU
FIG. The CPU has an internal register group 208 . Program counter 209. AL
U (arithmetic logic unit) 205, an internal bus 210 that connects the ALU 205 and other CPU components. ROR (read data register) 201 that temporarily holds data read from main memory. Instruction decoding unit 2 that processes the read data and generates the start address of the microinstruction.
03. WOR (write data register) 20 that holds temporary data in order to write the calculated data to the main memory
6. It has a MAR (memory address register) 207 that holds the address of the main memory when accessing the main memory.

The CPU sets the contents of the program waiting to be executed program counter 209 in the MAR 207 and accesses the main memory using the address of the MAR 207.

The data taken into the RDR is used by the instruction duder 203 to generate the start address of the microprogram for the internal processing procedure corresponding to the instruction when the instruction is executed, and then sent to the control unit 204.
Outputs the start address of the microprogram. At this time, the decoder 203 does not detect an undefined instruction and the RO
The start address of the microprogram corresponding to the data in R is output. The control unit 203 performs arithmetic processing and bus control according to the processing procedure described in the microprogram starting from the first address of the microprogram.6However, if there is no microinstruction in the control unit that corresponds to the address generated by the decoder, no An error detection circuit within the control detects a definition instruction error, interrupts a series of processes, and activates an error handling microprogram. Further, even if a jump error occurs in the microprogram during execution of the microprogram, the error detection circuit in the control section detects the error and stops the series of processing.

The configuration of the control unit is 113th! The control unit shown in I is a microprogram address selector 1. Control storage address register C that temporarily holds the selected address
3AR2, partially or fully rewritable control memory 3. A microinstruction register MIR4, which temporarily holds microinstructions read out from the control memory, and a microinstruction decoder 5. Adder lNCl0e! -5-detection circuits 6, 7.
Consists of 9. MIR4 is logically "engine" and represents the start address of the microinstruction, logically "0" represents the other address, JIN bit 41, field 43 that represents the branch destination address of the microinstruction, and microprogram address control field. 44. It consists of an arithmetic/processing field 42. Signal line 11 is the branch address output from MIR4.

The signal 1114 is the address of the microinstruction currently being executed in the engineering NC 10 plus 1. The signal line 13 is the start address of the error processing microinstruction, and the signal line 21 is the start address of the microinstruction, the address of the microinstruction currently being executed. A select signal that selects either the next address or the branch destination address of the microinstruction, signal line 22
is a select signal that selects the start address of the error processing microinstruction, and a logical signal of 1 is output to the signal line 19 at the time of an instruction branch, and a logical signal of 1 is output to the signal line 16 at the time of a branch other than an instruction branch. The lj I IF signal is output. Also, the signal line 15 is a signal line that outputs the state of the JIN bit 41, and the signal lines 17 and 20 are output signal lines of the error detection circuit.In the control section having the above configuration, the macro, ) command microprogram When branching to a module, an address that is not the start address of the -7 microinstruction is connected to signal line 12.
When input from
The signal II is output, an undefined instruction error is detected by the undefined instruction detection circuit 7, and an error processing microinstruction is activated. In addition, if a branch is made to an address of a microprogram that should not be branched to when a macro instruction branches to a microprogram module, that is, an address where the JIN bit is logically 0'', the signal line 15 and signal, 1116 logically 111 I
The I signal is output, and the microprogram jump error is detected.

According to this embodiment, in order to detect microprogram erroneous jump errors and undefined instruction errors, one bit is provided in the microprogram for error detection, and two AND gates are added to detect undefined instructions in the control section. It enables detection of instruction errors and microprogram erroneous jump errors, and realizes effective use of control memory.

〔Effect of the invention〕

According to the present invention, since the detection of undefined instructions is performed using control memory, there is no need to change the undefined instruction detection logic when extending or changing the instruction system, and the instruction system can be expanded or changed without changing the hardware. Therefore, it is possible to provide processing units with the optimal instruction system for various uses using the same hardware.In addition, the undefined instruction detection logic can be used to detect undefined instructions in the instruction decoding section. Complex hard-wired logic is required, and the more complex the instruction system, the greater the number of gates required. However, when using control memory, it consists of a memory of the number of control memory words x 1 bit and at most a few ICs. This has the effect of making the hardware smaller and cheaper.

Furthermore, if an extended instruction is not used, the space for the beginning of the microprogram for that instruction is set to the JIN bit.
By doing so, it can be used for microprograms with other instructions, which has the effect of reducing the capacity of the extended instruction space in the control memory.

[Brief explanation of the drawing]

FIG. 1 shows an internal configuration diagram of a control section of a data processing apparatus according to an embodiment of the present invention, and FIG. 2 shows an internal configuration diagram of a CPU. 3... Control memory, 4... Micro instruction register, 4
1... JIN bit indicating that it is the beginning of a microinstruction, 6, 7... AND gate, 15... A signal indicating that it is not the beginning of a microinstruction, 16... Indicating a branch other than an instruction branch. Signal, 19... Signal indicating instruction branch, 17... Microprogram erroneous jump error-1 detection signal, 20... Undefined instruction detection signal.

Claims (1)

[Claims] 1. In a data processing device that executes a macroinstruction and is controlled by a microprogram, a first means having a bit in the microprogram indicating whether or not it is the beginning of the microinstruction and detecting a branch of the microinstruction; When a branch is detected by the first means, a second means refers to the bit and the branch type of the microinstruction, and detects the jump error of the microprogram if the branch is other than a branch to a macroinstruction microprogram module. and a third means for detecting an undefined macro instruction by referring to the bit when the branch is a branch to a macro instruction microprogram module.