JPS62249239A - Simulation system for actual parts interlocking logic - Google Patents

Abstract

PURPOSE:To improve the efficiency of simulation, by providing a means which finds a forecasted output vector before the next vector is generated, at an actual parts interlocking device. CONSTITUTION:A logic simulator 100, when the m-th number of input change of a chip input is detected, and it is equal to the forecasted input vector generated from the (m-1)-th number of input vector by the actual parts interlocking device, reads a forecasted output vector stored in an output latch 108, then restarts a process, and when they are not equal, the simulator sends the m-th number of input vector to the actual parts interlocking device, and waits for the appearance of the output vector at the output latch 108, and when it appears, the simulator reads the output latch 108, then restarts the process. Also, the actual parts interlocking device generates the forecasted input vector, and the forecasted output vector, in parallel with the process restarted by the simulator 100, and stores them, at an address (n+m) in a history memory, and the output latch 108, respectively.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to @embedded simulation, and in particular, a method for reducing simulation time suitable for real component-linked logic simulation in which real chips are used for simulation. Regarding.

[Conventional technology]

Regarding the real component interlocking logic simulation method that simulates using real chips.

Nikkei Electronics '84 July 50 issue 348P1
70-184, entitled "Workstation to Support System Designer's LSI Development".

[Problem that the invention seeks to solve]

With the technology described in the above literature, the logic simulation l/-p operates every time the chip input changes. Pause and input vector? The output vector is sent to the real parts interlocking device, waits for the output vector to be obtained by the real parts interlocking device, the output vector is read out from the real parts interlocking device, and the simulation process is restarted.

Therefore, after the chip input changes, does the logic simulator process the simulation? What is the time T until restarting?

T = Time the input vector reaches the real component interlocking device Time for the actual component interlocking device to obtain the output vector + Time for the output vector to be output from the real component interlocking device, but one real chip is used for this time T. The problem is that it is less efficient than a simulation method that does not use it.

The purpose of the present invention is to create a real component-linked logic simulation method that simulates using real chips. There,
The objective is to shorten the time from when the logic simulator detects a chip input change to when the simulation restarts, thereby improving the efficiency of logic simulations linked to real components. [Means for solving the problem] The above purpose is to: Before a new input vector is sent from the logic simulator, the first input vector is predicted from the past input vectors stored in the history memory and given to the real Chi Nobu to obtain the expected output vector. A new means is added to the actual parts interlocking device, and the predicted input vector is compared with the predicted input vector when the next input change occurs in the step, and if the comparison results match, the predicted input vector is This is achieved by providing the logic simulator with a control means that uses the predicted output vector based on i6 as it is.

[Effect]

The means newly added to the real parts interlocking device in the present invention are a.
Does the buried simulator process the output vector by protruding it from the actual component interlocking device? After restarting.

u. Predict the next input vector that will occur based on past input vectors stored in the history memory, apply the predicted input vector to the real chip, and obtain the predicted output vector. This operation is performed in parallel with simulation processing in the logic simulator. When the chip input actually changes and an input vector is generated, the logic simulator will
Is the predicted input vector better than the input vector that occurred in the past using the same prediction method as the actual parts interlocking device? Generate and compare with the actually generated input vector. If they are the same, the logic simulator can restart processing simply by reading out the expected output vector that has already been determined by the real component interlocking device. If different, the input vector is given to the real parts interlocking device to obtain the output vector, the output vector is read from the real parts interlocking device, and the logic simulator restarts the simulation process, as in the conventional case.

Therefore, in the present invention, the time T from when the logic simulator detects a change in chip input until it restarts processing is T.
is the same as before when the expected input vector and the actual input vector are different, but when the expected input vector and the actual input vector match.

+11 = time required to read the output vector from the real component interlocking device, so simulation efficiency can be improved compared to the conventional method.

The degree of improvement in simulation efficiency depends on the predictive value of the predicted input vector. However, expected input vectors with a high accuracy rate are often easily obtained. For example, in a microprocessor, the cloak that determines the state of the chip changes the most times, so when you compare the nth input vector or the +1st input vector, it is often the case that only the cloak signal value differs. There is a percentage elephant. .

Therefore, if the klovk signal value of the n-th input vector is 1, it is OK, and if it is o, it is possible to obtain the +1-th predicted input vector with a high accuracy rate by simply setting it to 1.

[Example] An example of the present invention will be described below with reference to FIGS. 1 and 2. In this embodiment, it is assumed that the real chip is a microprocessor.

Is Figure 1 a block diagram of the actual parts interlocking device? 100 is a logic simulator, 101 is an address register that stores the address of the history memory, 102 is a real address register buffer that saves the contents of the address register 101, and 103+t7) the contents of the "l/s" register 101. , a comparator that compares the contents of the address 1 jistaba couch 102, 104 an adder that adds +1j to the contents of the address register 101, 105 a history memory that stores the input vector sequence, and IC16 the output of the history memory 105? A latch 107 holds the real chip, a latch 108 holds the chip output, and a predicted input vector generation circuit 110 generates the predicted input vector. 100-1
08 is used in the conventional simile shiran system that interlocks with actual parts.

The simulation procedure will be explained below. Before the simulation, the logic simulator 100 stores the chip initialization input vector in the history memory 105,
The chip 107 can be initialized. Therefore, the address register 101 is reset and from address 0 to n-
Is the content of sequential address register 101 at address 1? Send input vector sequence for initialization while updating using adder 104.

It is committed to the history memory 105.

After the simulation starts, when the Y logic simulator 100 detects the first change in the chip input, the logic simulator 1
00 stops the process and sends the input vector to the real component and interlocking device. Address register 101 in the real component interlocking device
Y+ 11. The input vector is saved in the address buffer register 102, and the new input vector is written to address 1 in the history memory 105, and then the address 1/register 101 is reset.

Next, add the contents of the address register 101 to the register 104.
+1 using , address register 101 provides the contents of the history memory at the indicated address to real chip 107 through input latch 106 . Note that during the operation of giving this input vector to the real chip.

The contents of address register 101 and the contents of address register buffer 102? Does the comparator 103 check and is there a match? If detected, the operation will be stopped. When the logical simulator 100 detects the stoppage of the real component interlocking device, it reads the output vector 108) L' storing the output vector and restarts the simulator processing.

The real component interlocking device performs primary processing in parallel with the restarted simulation processing of the logic simulator 100.

First, the expected input vector generation circuit 118 selects the history memory 1 at the address (address) indicated by the address register 101.
The expected input vector is generated by taking in the contents of 05 and inverting the signal value of 9. Then, in the same manner as the above procedure, after storing the predicted input vector at address +1 of the FF history memory 105,
The content of is given to the real chip 107, and the output latch 108
Store the expected output vector in .

When the logic simulator detects a second input change in the chip input, it compares the input vector with the first input vector. The difference between the two vectors.

If it is just a clock signal value, logic simulator 10
Is 0 an input vector? Not sent to the actual parts interlocking device.

The actual component interlocking device immediately reads the output latch 108, which stores the expected output vector obtained from the expected input vector, and performs simulation processing. resume.

If the difference between the two vectors is not just the black signal value, what does the logic simulator 100 do? stops, sends the input vector to the real part interlocking device, and the real part interlocking device sends the output vector to the output latch 10 in the same way as at the time of the first input change.
Wait 7 to store in 8. And is the output vector stored in the output latch 108? When detected, output latch 1
Simulation process including osvffl? resume. In addition, in both cases, in parallel with the resumption of logic simulator processing, the actual component interlocking device generates the expected input vector and expected output vector using the same procedure as the first manual change. They are generated and stored in the output register 108 at address 1+2 of the history memory 105, respectively.

Similarly, the logic simulator 100 inputs m of the chip input.
When the actual component interlocking device detects the input change of the m-th input, if it is equal to the expected input vector generated from the m-1st input vector, the expected output vector stored in the output channel 108 is read. process? If the input vector is different, the m-th input vector is sent to the real component interlocking device, the output vector is waited for to appear on the output latch 108, and when the output vector appears, the output latch 108 is read and the process is restarted. Also.

In parallel with the restarted processing of the simulator 100, the real component interlocking device generates an expected input vector and an expected output vector. They are generated and stored at address i+m in the history memory 105 and in the output latch 10th, respectively.

Fig. 2 shows the processing of the real parts interlocking device according to the present invention? This is shown in a flowchart, and reference numeral 201 is a judgment statement that divides processing according to the requests of the logic simulator.

210 to 212 are initial input vector storage processing, 220
~226 is the process of calculating the output vector from the input vector transferred from the logic simulator, 230~235
is a process that returns an output vector to the logic simulator, generates an expected input vector, and obtains an expected output vector.

According to this embodiment, the input vector is predicted and the expected output vector is obtained before an input change occurs in the real chip, so when an input change actually occurs, the output vector is immediately available. Effective in improving simulation efficiency.

Above, we have explained the case of predicting only one person's output vector using example Y, but it is also possible to apply the same idea to 72 or more input/output vectors, and the number of vectors can be adjusted according to the characteristics of one component such as a microprocessor. If set, the effects of the present invention can be fully exhibited.

[Effects of the Invention] According to the present invention, for a chip with complicated internal logic, 1
In the real parts interlocking logic simulation system that calculates the output vector using a real chip, by providing the real parts interlocking device with a means to obtain the expected output vector before the primary input vector is generated, it is possible to actually use human labor. When a vector occurs.

If this is equal to the expected input vector, then the output vector can be calculated without giving the input vector to the actual component interlocking device. Therefore, it is effective in improving the staining efficiency.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a real component interlocking device according to an embodiment of the present invention, and FIG. 2 is a control flow diagram. -100...Logic simulator. 101...Address register. 103... Comparator. 105...History memory. 106...Input latch. 107...Real chip. 108... Dekaraguchi. 1st country

Claims (1)

[Claims] 1. A logic simulator that performs logic simulation;
In a simulation system consisting of a real component interlocking device that calculates the output vector of a chip based on the input vector from the logic simulator, the logic simulator reads the output vector from the real component interlocking device and then detects the next input change of the chip. Until then, the actual component interlocking device is equipped with a means to generate an expected output vector by predicting the next input vector from past input vectors and feeding it to the real chip. A logic simulator is provided with a control means that compares a new input vector when a change occurs with the predicted input vector, and uses the predicted output vector based on the predicted input vector as it is when the comparison results match. This is a real component-linked logic simulation method that is characterized by shortening the processing time and speeding up the process to obtain new output vectors.