CN117251118B - Virtual NVMe simulation and integration supporting method and system - Google Patents
Virtual NVMe simulation and integration supporting method and system Download PDFInfo
- Publication number
- CN117251118B CN117251118B CN202311524300.5A CN202311524300A CN117251118B CN 117251118 B CN117251118 B CN 117251118B CN 202311524300 A CN202311524300 A CN 202311524300A CN 117251118 B CN117251118 B CN 117251118B
- Authority
- CN
- China
- Prior art keywords
- nvme
- virtual
- memory
- virtual nvme
- command
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 34
- 238000004088 simulation Methods 0.000 title claims abstract description 24
- 230000010354 integration Effects 0.000 title claims abstract description 17
- 238000012545 processing Methods 0.000 claims abstract description 74
- 230000006870 function Effects 0.000 claims description 19
- 230000005540 biological transmission Effects 0.000 claims description 14
- 230000007246 mechanism Effects 0.000 claims description 12
- 230000008569 process Effects 0.000 claims description 10
- 238000013507 mapping Methods 0.000 claims description 8
- 230000003068 static effect Effects 0.000 claims description 6
- 230000000694 effects Effects 0.000 abstract description 2
- 238000011161 development Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 4
- 238000004891 communication Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0662—Virtualisation aspects
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0674—Disk device
- G06F3/0676—Magnetic disk device
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention provides a method and a system for supporting virtual NVMe simulation and integration, wherein the method comprises the following steps: step S1: constructing a virtual NVMe processor based on the virtual NVMe processor command processing flow and the virtual NVMe processor memory map; step S2: constructing a virtual NVMe disk based on the read-write of the virtual NVMe hard disk; step S3: and compiling the constructed virtual NVMe processor and the virtual NVMe disk to generate virtual NVMe, wherein the generated virtual NVMe supports the operation of the simulation system. According to the invention, the NVMe processor is realized by using software, so that the dependence on hardware is reduced as much as possible, and the technical effect of full-digital simulation NVMe is realized.
Description
Technical Field
The invention relates to the technical field of virtualization, in particular to a method and a system for supporting virtual NVMe simulation and integration.
Background
The existing virtual NVMe simulation technology generally needs to be supported by a hardware disk controller, and a firmware code accesses the hardware NVMe controller in the running process so as to realize the purpose of using virtual NVMe in a virtual system; the virtual NVMe technology related in the invention realizes the NVMe controller through software and does not depend on a hardware disk controller, compared with the prior virtual NVMe technology, the virtual NVMe technology is more flexible in actual engineering use, in certain specific scenes, parameters such as the size, the model and the like of the required NVMe controller can be flexibly set, and the virtual NVMe controller depending on hardware possibly has the problem that certain specific scenes are not satisfied.
Patent document CN115904631a (application number 202211684110.5) discloses an NVMe virtualization method, system, medium and device having an immediate processing capability, comprising: initializing a physical resource pool module; creating a plurality of kernel threads as I/O controllers; initializing a tenant management module; after the virtual machine is created, the tenant management module creates a virtual device for the virtual machine and binds the virtual device to the virtual machine; the virtual equipment is given to an I/O controller which is active at present, and information communication and setting are carried out; the I/O controller runs based on an algorithm, performs global I/O and bandwidth classification and immediate processing. The patent host is a remote server, the virtual machine is a local client, and the network transmission has performance loss, so that the performance is inferior to that of a direct data reference mode of a local application program.
Patent document CN114281252a (application No. 202111510109.6) discloses a virtualization method and device for nonvolatile high speed transmission bus NVMe device, the virtualization method comprising: acquiring a device establishment request, wherein the device establishment request is used for establishing virtual NVMe devices corresponding to the NVMe devices in the virtual machine; determining a first input/output (IO) queue for establishing virtual NVMe equipment, wherein the first IO queue corresponds to a second IO queue in the NVMe equipment; based on the first IO queue and the device establishment request, virtual NVMe devices corresponding to the NVMe devices are established in the virtual machine, and the virtual NVMe devices are used for realizing communication connection between the virtual machine and the NVMe devices. The virtual NVMe device of the patent needs real NVMe hardware to support, and needs virtualization configuration, and overall, the operation convenience is far less than that of a hot plug mode.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a method and a system for supporting virtual NVMe simulation and integration.
The method for supporting virtual NVMe simulation and integration provided by the invention comprises the following steps:
step S1: constructing a virtual NVMe processor based on the virtual NVMe processor command processing flow and the virtual NVMe processor memory map;
step S2: constructing a virtual NVMe disk based on the read-write of the virtual NVMe hard disk;
step S3: and compiling the constructed virtual NVMe processor and the virtual NVMe disk to generate virtual NVMe, wherein the generated virtual NVMe supports the operation of the simulation system.
Preferably, the step S1 employs:
step S1.1: developing a virtual NVMe processor command processing flow based on an NVMe standard protocol;
step S1.2: and storing the memory address and the data length of the command issued by the host into the linked list to finish memory mapping.
Preferably, the step S1.2 employs: when the NVMe internal data transmission mechanism is PRP, performing residual operation on the memory page size through the memory page address stored in the linked list to judge whether the current memory page is a whole page memory or a non-whole page memory; obtaining the storage data length of the non-whole page memory by making a difference, and storing the length corresponding to the address of the memory page stored in the linked list;
when the NVMe memory data transmission mechanism is SGL, the memory address and the data length issued in the command are stored in the linked list according to the standard protocol requirement.
Preferably, the step S2 employs: when the virtual machine application program runs, a virtual NVMe model is called to call hard disk read-write in the virtual machine, and a file library of the real physical machine is called through the hard disk read-write, so that the hard disk read-write processing on the host machine is realized.
Preferably, the step S3 employs: and compiling the constructed virtual NVMe processor and virtual NVMe disk according to the preset virtual simulation platform framework requirement to generate a dynamic library or a static library to obtain the virtual NVMe.
The invention provides a virtual NVMe simulation and integration supporting system, which comprises the following steps:
module M1: constructing a virtual NVMe processor based on the virtual NVMe processor command processing flow and the virtual NVMe processor memory map;
module M2: constructing a virtual NVMe disk based on the read-write of the virtual NVMe hard disk;
module M3: and compiling the constructed virtual NVMe processor and the virtual NVMe disk to generate virtual NVMe, wherein the generated virtual NVMe supports the operation of the simulation system.
Preferably, the module M1 employs:
module M1.1: developing a virtual NVMe processor command processing flow based on an NVMe standard protocol;
module M1.2: and storing the memory address and the data length of the command issued by the host into the linked list to finish memory mapping.
Preferably, the module M1.2 employs: when the NVMe internal data transmission mechanism is PRP, performing residual operation on the memory page size through the memory page address stored in the linked list to judge whether the current memory page is a whole page memory or a non-whole page memory; obtaining the storage data length of the non-whole page memory by making a difference, and storing the length corresponding to the address of the memory page stored in the linked list;
when the NVMe memory data transmission mechanism is SGL, the memory address and the data length issued in the command are stored in the linked list according to the standard protocol requirement.
Preferably, the module M2 employs: when the virtual machine application program runs, a virtual NVMe model is called to call hard disk read-write in the virtual machine, and a file library of the real physical machine is called through the hard disk read-write, so that the hard disk read-write processing on the host machine is realized.
Preferably, the module M3 employs: and compiling the constructed virtual NVMe processor and virtual NVMe disk according to the preset virtual simulation platform framework requirement to generate a dynamic library or a static library to obtain the virtual NVMe.
Compared with the prior art, the invention has the following beneficial effects:
1. according to the invention, the NVMe processor is realized by using software, so that the dependence on hardware is reduced as much as possible, and the technical effect of full-digital simulation NVMe is realized;
2. the invention realizes simulation without changing the source code of the application program of the computer system by adopting the real NVMe protocol, and is suitable for simulating NVMe parts under various computer systems; simulation development of the NVMe processor is carried out through an NVMe standard protocol, so that the current virtual NVMe can meet most scenes; for special scenes, configuration can be performed by modifying the exposed relevant hardware parameters;
3. according to the invention, the host machine file library is adopted to simulate the hard disk read-write, so that the virtual NVMe hard disk read-write function is realized;
4. according to the invention, the development process depends on the virtual development platform framework to open related hardware parameters, so that a user can configure the hardware parameters according to the system requirements in the use process, and the model perfectly fits the system requirements; the invention abstracts hardware parameters related to the real NVMe, realizes the parameters and the internal logic of the controller by a software means, exposes the parameters to a user through the frame characteristics of the corresponding simulation platform, and changes the processing logic of the controller when the user modifies the configuration parameters, thereby meeting the requirements of the user on different NVMes.
Drawings
Other features, objects and advantages of the present invention will become more apparent upon reading of the detailed description of non-limiting embodiments, given with reference to the accompanying drawings in which:
FIG. 1 is a schematic diagram of the relationship between virtual NVMe and virtual machine and the relationship between NVMe SSD and host;
fig. 2 is an NVMe command processing procedure.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the present invention, but are not intended to limit the invention in any way. It should be noted that variations and modifications could be made by those skilled in the art without departing from the inventive concept. These are all within the scope of the present invention.
Example 1
The invention provides a method and a system for supporting virtual NVMe simulation and integration, wherein the method comprises the following steps: when a computer system with an NVMe hard disk is simulated in a host, the NVMe hard disk part in a virtual computer system is simulated by utilizing the self-contained hard disk of the host in a read-write mode of the self-contained file of the host; and realizing the register and the NVMe processor part in the memory read-write simulation virtual computer system through the self-contained API of the simulation software.
Specifically, the method for supporting virtual NVMe simulation and integration includes:
step 1: developing a virtual NVMe processor command processing flow;
step 2: the memory mapping of the virtual NVMe processor is realized;
step 3: virtual NVMe hard disk reading and writing are realized;
step 4: compiling to generate virtual NVMe.
Specifically, the step 1 adopts: virtual NVMe processor command processing flows were developed based on NVMe standard protocols.
More specifically, the command processing flow to be developed includes doorbell register processing, commit queue and completion queue processing, and implementation of command processing of each level, and the flow is consistent with the NVMe standard protocol; the set of processes can enable the virtual scheme to be suitable for various operating systems;
more specifically, writing a register processing function and a commit queue processing function; writing all functions for command processing;
the implementation of each virtual command processing flow includes the same steps, including:
the commit queue acquires a section of host memory according to the head of the commit queue acquired from the doorbell register, and distinguishes an Admin queue and an IO queue through a queue ID;
filling the memory information into a contracted data structure: command structure to be processed in future;
parsing the contracted data structure: analyzing the corresponding commands according to the different required commands;
processing the command according to the structural member required by the current command;
returning a corresponding return value (error code) according to the command processing condition;
the completion queue fills the agreed data structure according to the command processing condition: the method comprises the steps of triggering interrupt by information such as command processing state, queue ID, command ID and the like;
specifically, the step 2 employs: and storing the memory address and the data length of the command issued by the host into the linked list to finish memory mapping.
More specifically, when the internal data transmission mechanism of the NVMe is PRP, performing a remainder operation on the size of the memory page through the memory page address stored in the linked list to determine whether the current memory page is a whole page memory or a non-whole page memory; obtaining the storage data length of the non-whole page memory by making a difference, and storing the length corresponding to the address of the memory page stored in the linked list;
when the NVMe memory data transmission mechanism is SGL, the memory address and the data length issued in the command are stored in the linked list according to the standard protocol requirement.
Specifically, the step 3 adopts: when the virtual machine application program runs, a virtual NVMe model is called to call hard disk read-write in the virtual machine, and a file library of the real physical machine is called through the hard disk read-write, so that the hard disk read-write processing on the host machine is realized.
More specifically, the virtual hard disk reading and writing is realized by the file reading and writing function of the host machine;
the implementation of the virtual read-write function comprises the same steps:
positioning the file read-write position through a shape parameter slba (initial logic block address);
determining the read file size through a shape parameter len (read-write content logical block length);
writing or returning the required read-write content through the shape parameter pointer buf;
specifically, the step 4 adopts: and compiling the constructed virtual NVMe processor and virtual NVMe disk according to the preset virtual simulation platform framework requirement to generate a dynamic library or a static library to obtain the virtual NVMe.
More specifically, compiling and generating virtual NVMe by using a development tool chain of a target machine to be virtualized;
the virtual machine application program can call virtual NVMe when running; in the running process of the virtual machine application program, a disk read-write condition may exist, and in this case, access of the NVMe may be involved, and at this time, the virtual system may call the virtual NVMe to ensure normal operation of the application program for ensuring normal operation of the system.
And (3) the virtual NVMe calls the hard disk read-write of the step (3) in the virtual machine through the command processing of the step (1), and calls the file library of the real physical machine so as to realize the hard disk read-write processing on the host machine.
Further comprises: open part hardware parameters depending on the virtual simulation development platform framework:
calling a virtual simulation development platform attribute registration interface;
the hardware parameters for open NVMe are as follows: NVMe SSD size; CAP (controller capability) register; a CC (controller configuration) register; a namespace related parameter; identify related parameters;
logic related to the parameters in the codes is realized, and the open parameters are related to the corresponding parameters in the actual logic according to the rules of the virtual development platform.
Specifically, the virtual NVMe emulation and integration supporting system comprises:
module 1: developing a virtual NVMe processor command processing flow;
module 2: the memory mapping of the virtual NVMe processor is realized;
module 3: virtual NVMe hard disk reading and writing are realized;
module 4: compiling to generate virtual NVMe.
Specifically, the module 1 employs: virtual NVMe processor command processing flows were developed based on NVMe standard protocols.
More specifically, the command processing flow to be developed includes doorbell register processing, commit queue and completion queue processing, and implementation of command processing of each level, and the flow is consistent with the NVMe standard protocol; the set of processes can enable the virtual scheme to be suitable for various operating systems;
more specifically, writing a register processing function and a commit queue processing function; writing all functions for command processing;
the implementation of each virtual command processing flow contains the same modules, including:
the commit queue acquires a section of host memory according to the head of the commit queue acquired from the doorbell register, and distinguishes an Admin queue and an IO queue through a queue ID;
filling the memory information into a contracted data structure: command structure to be processed in future;
parsing the contracted data structure: analyzing the corresponding commands according to the different required commands;
processing the command according to the structural member required by the current command;
returning a corresponding return value (error code) according to the command processing condition;
the completion queue fills the agreed data structure according to the command processing condition: the method comprises the steps of triggering interrupt by information such as command processing state, queue ID, command ID and the like;
specifically, the module 2 employs: and storing the memory address and the data length of the command issued by the host into the linked list to finish memory mapping.
More specifically, when the internal data transmission mechanism of the NVMe is PRP, performing a remainder operation on the size of the memory page through the memory page address stored in the linked list to determine whether the current memory page is a whole page memory or a non-whole page memory; obtaining the storage data length of the non-whole page memory by making a difference, and storing the length corresponding to the address of the memory page stored in the linked list;
when the NVMe memory data transmission mechanism is SGL, the memory address and the data length issued in the command are stored in the linked list according to the standard protocol requirement.
Specifically, the module 3 employs: when the virtual machine application program runs, a virtual NVMe model is called to call hard disk read-write in the virtual machine, and a file library of the real physical machine is called through the hard disk read-write, so that the hard disk read-write processing on the host machine is realized.
More specifically, the virtual hard disk reading and writing is realized by the file reading and writing function of the host machine;
the implementation of the virtual read-write function comprises the same modules:
positioning the file read-write position through a shape parameter slba (initial logic block address);
determining the read file size through a shape parameter len (read-write content logical block length);
writing or returning the required read-write content through the shape parameter pointer buf;
specifically, the module 4 employs: and compiling the constructed virtual NVMe processor and virtual NVMe disk according to the preset virtual simulation platform framework requirement to generate a dynamic library or a static library to obtain the virtual NVMe.
More specifically, compiling and generating virtual NVMe by using a development tool chain of a target machine to be virtualized;
the virtual machine application program can call virtual NVMe when running; in the running process of the virtual machine application program, a disk read-write condition may exist, and in this case, access of the NVMe may be involved, and at this time, the virtual system may call the virtual NVMe to ensure normal operation of the application program for ensuring normal operation of the system.
The virtual NVMe processes and calls the hard disk read-write of the module 3 through the command of the module 1 in the virtual machine, and calls the file library of the real physical machine so as to realize the hard disk read-write processing on the host machine.
Further comprises: open part hardware parameters depending on the virtual simulation development platform framework:
calling a virtual simulation development platform attribute registration interface;
the hardware parameters for open NVMe are as follows: NVMe SSD size; CAP (controller capability) register; a CC (controller configuration) register; a namespace related parameter; identify related parameters;
logic related to the parameters in the codes is realized, and the open parameters are related to the corresponding parameters in the actual logic according to the rules of the virtual development platform.
Those skilled in the art will appreciate that the invention provides a system and its individual devices, modules, units, etc. that can be implemented entirely by logic programming of method steps, in addition to being implemented as pure computer readable program code, in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers, etc. Therefore, the system and various devices, modules and units thereof provided by the invention can be regarded as a hardware component, and the devices, modules and units for realizing various functions included in the system can also be regarded as structures in the hardware component; means, modules, and units for implementing the various functions may also be considered as either software modules for implementing the methods or structures within hardware components.
The foregoing describes specific embodiments of the present invention. It is to be understood that the invention is not limited to the particular embodiments described above, and that various changes or modifications may be made by those skilled in the art within the scope of the appended claims without affecting the spirit of the invention. The embodiments of the present application and features in the embodiments may be combined with each other arbitrarily without conflict.
Claims (8)
1. A method for supporting virtual NVMe emulation and integration, comprising:
step S1: constructing a virtual NVMe processor based on the virtual NVMe processor command processing flow and the virtual NVMe processor memory map;
step S2: constructing a virtual NVMe disk based on the read-write of the virtual NVMe hard disk;
step S3: compiling the constructed virtual NVMe processor and virtual NVMe disk to generate virtual NVMe, wherein the generated virtual NVMe supports the operation of a simulation system;
the step S1 adopts:
step S1.1: developing a virtual NVMe processor command processing flow based on an NVMe standard protocol;
step S1.2: storing the memory address and the data length of the command issued by the host into a linked list to finish memory mapping;
the command processing flow to be developed comprises doorbell register processing, submitting queue and completing queue processing, and realizing command processing of each level, wherein the flow is consistent with NVMe standard protocol; the set of processes can enable the virtual scheme to be suitable for various operating systems;
comprising the following steps: writing a register processing function and a submission queue processing function; writing all functions for command processing;
the implementation of each virtual command processing flow includes the same steps, including:
the commit queue acquires a section of host memory according to the head of the commit queue acquired from the doorbell register, and distinguishes an Admin queue and an IO queue through a queue ID;
filling the memory information into a contracted data structure: command structure to be processed in future;
parsing the contracted data structure: analyzing the corresponding commands according to the different required commands;
processing the command according to the structural member required by the current command;
returning a corresponding return value according to the command processing condition;
the completion queue fills the agreed data structure according to the command processing condition: the method comprises the steps of command processing state, queue ID, command ID information and triggering interrupt.
2. The method for supporting virtual NVMe simulation and integration according to claim 1, wherein the step S1.2 employs: when the NVMe internal data transmission mechanism is PRP, performing residual operation on the memory page size through the memory page address stored in the linked list to judge whether the current memory page is a whole page memory or a non-whole page memory; obtaining the storage data length of the non-whole page memory by making a difference, and storing the length corresponding to the address of the memory page stored in the linked list;
when the NVMe memory data transmission mechanism is SGL, the memory address and the data length issued in the command are stored in the linked list according to the standard protocol requirement.
3. The method for supporting virtual NVMe simulation and integration according to claim 1, wherein the step S2 employs: when the virtual machine application program runs, a virtual NVMe model is called to call hard disk read-write in the virtual machine, and a file library of the real physical machine is called through the hard disk read-write, so that the hard disk read-write processing on the host machine is realized.
4. The method for supporting virtual NVMe simulation and integration according to claim 1, wherein the step S3 employs: and compiling the constructed virtual NVMe processor and virtual NVMe disk according to the preset virtual simulation platform framework requirement to generate a dynamic library or a static library to obtain the virtual NVMe.
5. A system for supporting virtual NVMe emulation and integration, comprising:
module M1: constructing a virtual NVMe processor based on the virtual NVMe processor command processing flow and the virtual NVMe processor memory map;
module M2: constructing a virtual NVMe disk based on the read-write of the virtual NVMe hard disk;
module M3: compiling the constructed virtual NVMe processor and virtual NVMe disk to generate virtual NVMe, wherein the generated virtual NVMe supports the operation of a simulation system;
the module M1 employs:
module M1.1: developing a virtual NVMe processor command processing flow based on an NVMe standard protocol;
module M1.2: storing the memory address and the data length of the command issued by the host into a linked list to finish memory mapping;
the command processing flow to be developed comprises doorbell register processing, submitting queue and completing queue processing, and realizing command processing of each level, wherein the flow is consistent with NVMe standard protocol; the set of processes can enable the virtual scheme to be suitable for various operating systems;
comprising the following steps: writing a register processing function and a submission queue processing function; writing all functions for command processing;
the implementation of each virtual command processing flow includes the same steps, including:
the commit queue acquires a section of host memory according to the head of the commit queue acquired from the doorbell register, and distinguishes an Admin queue and an IO queue through a queue ID;
filling the memory information into a contracted data structure: command structure to be processed in future;
parsing the contracted data structure: analyzing the corresponding commands according to the different required commands;
processing the command according to the structural member required by the current command;
returning a corresponding return value according to the command processing condition;
the completion queue fills the agreed data structure according to the command processing condition: the method comprises the steps of command processing state, queue ID, command ID information and triggering interrupt.
6. The system of claim 5, wherein the module M1.2 employs: when the NVMe internal data transmission mechanism is PRP, performing residual operation on the memory page size through the memory page address stored in the linked list to judge whether the current memory page is a whole page memory or a non-whole page memory; obtaining the storage data length of the non-whole page memory by making a difference, and storing the length corresponding to the address of the memory page stored in the linked list;
when the NVMe memory data transmission mechanism is SGL, the memory address and the data length issued in the command are stored in the linked list according to the standard protocol requirement.
7. The virtual NVMe emulation and integration supporting system of claim 5, wherein the module M2 employs: when the virtual machine application program runs, a virtual NVMe model is called to call hard disk read-write in the virtual machine, and a file library of the real physical machine is called through the hard disk read-write, so that the hard disk read-write processing on the host machine is realized.
8. The virtual NVMe emulation and integration supporting system of claim 5, wherein the module M3 employs: and compiling the constructed virtual NVMe processor and virtual NVMe disk according to the preset virtual simulation platform framework requirement to generate a dynamic library or a static library to obtain the virtual NVMe.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311524300.5A CN117251118B (en) | 2023-11-16 | 2023-11-16 | Virtual NVMe simulation and integration supporting method and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311524300.5A CN117251118B (en) | 2023-11-16 | 2023-11-16 | Virtual NVMe simulation and integration supporting method and system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN117251118A CN117251118A (en) | 2023-12-19 |
| CN117251118B true CN117251118B (en) | 2024-02-13 |
Family
ID=89137227
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311524300.5A Active CN117251118B (en) | 2023-11-16 | 2023-11-16 | Virtual NVMe simulation and integration supporting method and system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117251118B (en) |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105700826A (en) * | 2015-12-31 | 2016-06-22 | 华为技术有限公司 | Virtualization method and device |
| CN107766097A (en) * | 2016-08-16 | 2018-03-06 | 三星电子株式会社 | The electronic installation of start-up operation is performed based on the enabled instruction that end-point devices provide |
| US9952782B1 (en) * | 2014-12-30 | 2018-04-24 | Nutanix, Inc. | Method and system for accessing data between different virtual disk formats in a virtualization environment |
| CN111381926A (en) * | 2018-12-27 | 2020-07-07 | 中兴通讯股份有限公司 | Virtualization method and device |
| CN111722786A (en) * | 2019-03-21 | 2020-09-29 | 阿里巴巴集团控股有限公司 | Storage system based on NVMe equipment |
| WO2020259418A1 (en) * | 2019-06-24 | 2020-12-30 | 华为技术有限公司 | Data access method, network card and server |
| CN112673341A (en) * | 2018-08-01 | 2021-04-16 | 美光科技公司 | NVMe direct virtualization with configurable storage |
| CN114138422A (en) * | 2021-12-10 | 2022-03-04 | 上海交通大学 | Extensible NVMe storage virtualization method and system |
| US11467776B1 (en) * | 2021-06-28 | 2022-10-11 | H3 Platform Inc. | System supporting virtualization of SR-IOV capable devices |
| CN115904631A (en) * | 2022-12-27 | 2023-04-04 | 上海交通大学 | NVMe virtualization method, system, medium and device with instant processing capability |
| CN116225992A (en) * | 2023-02-24 | 2023-06-06 | 山东云海国创云计算装备产业创新中心有限公司 | NVMe verification platform and method supporting virtualized simulation equipment |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9501245B2 (en) * | 2014-05-02 | 2016-11-22 | Cavium, Inc. | Systems and methods for NVMe controller virtualization to support multiple virtual machines running on a host |
-
2023
- 2023-11-16 CN CN202311524300.5A patent/CN117251118B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9952782B1 (en) * | 2014-12-30 | 2018-04-24 | Nutanix, Inc. | Method and system for accessing data between different virtual disk formats in a virtualization environment |
| CN105700826A (en) * | 2015-12-31 | 2016-06-22 | 华为技术有限公司 | Virtualization method and device |
| CN107766097A (en) * | 2016-08-16 | 2018-03-06 | 三星电子株式会社 | The electronic installation of start-up operation is performed based on the enabled instruction that end-point devices provide |
| CN112673341A (en) * | 2018-08-01 | 2021-04-16 | 美光科技公司 | NVMe direct virtualization with configurable storage |
| CN111381926A (en) * | 2018-12-27 | 2020-07-07 | 中兴通讯股份有限公司 | Virtualization method and device |
| CN111722786A (en) * | 2019-03-21 | 2020-09-29 | 阿里巴巴集团控股有限公司 | Storage system based on NVMe equipment |
| WO2020259418A1 (en) * | 2019-06-24 | 2020-12-30 | 华为技术有限公司 | Data access method, network card and server |
| US11467776B1 (en) * | 2021-06-28 | 2022-10-11 | H3 Platform Inc. | System supporting virtualization of SR-IOV capable devices |
| CN114138422A (en) * | 2021-12-10 | 2022-03-04 | 上海交通大学 | Extensible NVMe storage virtualization method and system |
| CN115904631A (en) * | 2022-12-27 | 2023-04-04 | 上海交通大学 | NVMe virtualization method, system, medium and device with instant processing capability |
| CN116225992A (en) * | 2023-02-24 | 2023-06-06 | 山东云海国创云计算装备产业创新中心有限公司 | NVMe verification platform and method supporting virtualized simulation equipment |
Non-Patent Citations (1)
| Title |
|---|
| 高效能可调度NVMe虚拟化研究;杨铭;《中国优秀硕士学位论文全文数据库》;全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117251118A (en) | 2023-12-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI410864B (en) | Controlling instruction execution in a processing environment | |
| CN114580344B (en) | Test excitation generation method, verification system and related equipment | |
| US8296119B2 (en) | Saving and restarting discrete event simulations | |
| US20210158131A1 (en) | Hierarchical partitioning of operators | |
| CN110941934A (en) | FPGA prototype verification development board segmentation simulation system, method, medium and terminal | |
| WO2001095160A2 (en) | Accessing state information in a hardware/software co-simulation | |
| US9710575B2 (en) | Hybrid platform-dependent simulation interface | |
| US8250545B2 (en) | Associated apparatus and method for supporting development of semiconductor device | |
| KR102315102B1 (en) | Method, device, apparatus, and medium for booting a virtual machine | |
| US20080281576A1 (en) | Interface board, simulator, synchronization method, and synchronization program | |
| CN117251118B (en) | Virtual NVMe simulation and integration supporting method and system | |
| US8886512B2 (en) | Simulation apparatus, computer-readable recording medium, and method | |
| JP4020849B2 (en) | Simulation device, simulation program, recording medium, and simulation method | |
| US10445218B2 (en) | Execution of graphic workloads on a simulated hardware environment | |
| JP7101709B2 (en) | Methods, devices, devices and media for realizing simulators | |
| CN115185638A (en) | Method for acquiring call stack during simulation running of application program and computing equipment | |
| CN114564241A (en) | Hardware device access method and device, computer device and storage medium | |
| US11151294B1 (en) | Emulated register access in hybrid emulation | |
| US11192662B2 (en) | Aircraft integrated modular avionics inter-partition communications simulation modeling language extension | |
| US11719749B1 (en) | Method and system for saving and restoring of initialization actions on dut and corresponding test environment | |
| CN111046430B (en) | Data processing method and device, storage medium and electronic equipment | |
| CN111459849B (en) | Memory setting method and device, electronic equipment and storage medium | |
| JP2019016168A (en) | Simulation program, method, and device | |
| WO2021250898A1 (en) | Information processing device, information processing method, and program | |
| CN116974979A (en) | Method, system and circuit for deploying file system on embedded memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |