JPS608938A - Debugging system of microprogram - Google Patents

Abstract

PURPOSE:To execute debugging of a microprogram by simple hardware by connecting a microprogram debugging device to a CPU, so that a clock selects one of the inside and the debugging device. CONSTITUTION:A debugging device 35 is connected from the outside of a CPU1. A microprogram to be debugged is stored in a processor 36 of the debugging device 35. A switching signal for making a clock line 33 outputted from a processor 36 effective is outputted by the processor 36, to a switching signal line 34 of a selector 31 for switching a clock line 32 outputted from an OSC29 and the clock line 33 outputted from the processor 36. Thereafter, the head micro-instruction code of a microprogram to be debugged, which is stored in advance in the processor 36 is set to a CDR-B37 through a data input line 41 and a set signal line 42, and only one clock is outputted to the clock line 33. In this way, hardware 25 executes a corresponding operation once.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a micro program debugging system.

Digital electronic devices and υ-divided CPUs developed in recent years
In today's world, micro program control methods have become mainstream, and micro program debugging systems have become indispensable.

This invention uses a microprogram control method.

The present invention also relates to a debugging system for CPU micro programs that requires a reduction in the amount of hardware.

FIG. 1 is a diagram showing a conventional micro program debugging system of this type. In Figure 1, (1
) is a micro-program control type CPU, and is composed of the hardware described below. (2
) is a current address register (hereinafter referred to as CAR) that addresses the control memory that stores the microprogram. (3) is this CA
This is the control memory address signal output from R(2).

(4) is not a good idea to memorize the micro program.

It is a control memory (hereinafter referred to as C-ROM) consisting of a read-only memory element with a read-only function, and a micro-instruction code is stored at the address addressed by the address signal line (3). Output. (5) is the output line of this C-ROM+4+. Reference numeral (6) denotes a control memory (hereinafter referred to as WCM) composed of write-pull memory elements having write and read functions. (7) is SVCMt61
CP1.1 (11f7) This is an address signal line for external color addressing. (8) is a selector that switches which of this address signal line (7) and the address signal line (3) outputted from the CAR (21) is used as the address signal line of the WCM (61).

(9) is the switching signal line of this selector (8),
It is supplied from outside the CPU (11). OI is a switch that generates a switching signal to this switching signal line (9). αυ is the output of the selector (8), and the wcM
This is an address signal line for addressing f6). α
2 is the data input line of the wcMf6).

CPU fl) is supplied from outside. a3 is the above W
CM (write signal line 61, address signal line aυ for addressing 7'i)
-WCM (Write the microinstruction code sent via the data input line 0 to address 61.Q4)
is the output line of WCM+61, and the contents of the address of WCM (61) addressed by address line 0υ are output to this.09 is the control data register (09) that holds the microinstruction code currently being executed.
The microinstruction code output from the C-ROM (41) or the WCM (6) is set every moment. ae is the C-ROM (41).
) output line (5) of WCM (6) and output line α→ of CDR-A Q! This is a selector for changing whether to use it as an input line for 9. αη is this selector Qf
9 switching signal line, which is supplied from outside the CPU (1). The α mallet is a switch that generates a switching signal on the switching signal line aη. The α damage is the CDI'L-
It is the input line of A (1!9), and is connected to the C-ROM (
Either the output line (5) of 41 or the output line α of WCM+6) is selected.

The next microinstruction code to be set to CDR-A (1!9) is output to this input line α9.
9 output line. Qυ is the microinstruction code output from CDR (I!9 through its output line).

Controlled by microinstruction code] 1-A buffer gate for supplying hardware.

is the output inhibit signal line of this buffer gate.
5. It is supplied from the outside of the CPU (11). (c) is a switch that generates an inhibition signal on the output inhibition signal line of this buffer gate.
This is the output line of (c) is hardware controlled by the microinstruction code supplied via this output line c2→. (e) is the input line of the CAR (21), to which the address signal of the control memory (c-ROM f4) created by this hardware (c) or WCM f61 is output.

@ is the set permission signal line of the CAR (2), and the CAR (2) created by the hardware (c)
A set permission signal is output to this. (c) is the above C
This is the set permission signal line of DR-A9, and CDR-AQ! was created by the software (c). A set permission signal of 9 is output to this. Kan is an oscillator (hereinafter referred to as O) that creates a repetitive pulse (hereinafter referred to as clock).
SC). (To) The clock signal output from 0SC (To) is the above CA Rf2) and CDR-A.
09 and hardware (c). The setting of the control memory address signal for the CAR (2), the setting of the next microinstruction code to be executed for the CDR-Mi, and the operation of the hardware (c) are all synchronized with this clock and executed every moment. It is done.

Next, a debugging procedure in a conventional micro program debugging system will be explained. What is normal micro program debugging?

This refers to simulating by some means whether the microprogram to be stored in the C-ROM (41) is correct before storing it in the C-ROM (4). In conventional debugging systems.

First, by setting the switch (c) that creates the output prohibition signal of the buffer game (Gυ) to the prohibition side.

The operation of the hardware (c) is fixed. In addition, the switch 01 of the selector (8) is set to the CPU (
+1 external address signal line (7) is enabled.

Next, the external address signal line (7) of c p U (11) and the data input line α2 of w CM (61)
and write signal line 03 to write the microprogram to be debugged from outside the CPU (1) to the WCM (61).
Sequentially write to. When writing of the micro program to the WCM (6) is completed, set the changeover switch (Ill) of the selector αQ to the side that enables the output line α4 of the WCM (61).

Turn the selector (8) on/off switch (lI to CA)
After setting the address signal line (3) of the output of R(21) to the valid side, the switch (c) which had prohibited the output of the buffer gate 0υ is set to the enable side.As a result, the above procedure Execution of the microprogram written in advance in the WCM (6+) is started.

In this case, the execution start address of the microprogram and the first microinstruction code to be executed are:

Naturally, depending on the hardware (c), each CAR12
+ and CDR-AQ! Must be ready by 9. This means that if we assume that when the output of the buffer game 2υ is disabled, logic 10' is output to all output lines, the hardware (c) will By interpreting it as an instruction code.

This can be realized by controlling the input line (c) of the CAR (21), the set permission signal line (5) of the CAR (21), and the set permission signal line (to) of the CDR-AQ!9. For example, all logic 20' In the microinstruction code of
Output all 0'' to the input line (c) of CAR (2), and set the CAR (2+ set permission signal line punishment and CDR-AQ9
By configuring the hardware (to) so that a set permission signal is output to each of the set permission signal lines (c) in #), it is possible to start the micro program from address 0. . On the other hand, in this case, W in the above procedure
It is necessary to write the micro program to be debugged into the CM (61) starting from address 0. When the micro program to be debugged that has been started in this way has finished running successfully, check the execution results.

If there is an error in the micro program, correct the micro program written to the WCM (21) and repeat the above procedure.

Since the conventional micro program debugging system is configured as described above, is it necessary to implement WCM, which is unnecessary when the CPU is in normal use?
However, there were drawbacks such as a useless hardware configuration. The present invention was made to improve this drawback and provides a micro program debug system that does not require WCM implementation.

FIG. 2 shows a diagram of the micro program debugging system of the present invention. In fig.

(Denoted at 11 is a CPU of micro program control type, which will be explained below). (2) is a CAR that addresses the control memory that stores the micro program.

(3) is the address signal line of the control memory output from this CAR (21). (4) is the C-ROM for storing the micro program.
The address signal line (3) outputs a micro naming code stored at the atranged address. (5) This is the output line of C-ROM (4>). α
It holds the currently executing microinstruction code (C
The microinstruction code which is DR-A and is output from the t''-ROM (4) is set every moment via the output line (5) of the C-ROM (4).

■ is the output line of CDR-A (lG). Qυ is the CDR-A (lG output line)
This is a buffer gate for supplying the micro-instruction code outputted from Aα via its output line (A) to the hardware controlled by the micro-instruction code. @ is the output prohibition signal line of this buffer gate f
i, supplied from outside the CPU (1).

is the output line of the buffer gate 11υ, and in the configuration of the present invention, it is wired ORed with the output line of the buffer gate of the microinstruction code supplied from the outside of the cpU(+). (c) is hardware controlled by the microinstruction code supplied via this output line (24). (A) is the input line of the CAR (2), to which the address signal of the control memory, ie, C-ROM (4), created by this hardware (C) is output. (5) is the above CA
The set permission signal line of C A R (21) is used to output the set permission signal of C A R (2) created by the hardware (C). (C) is the set permission signal line of CDR-AQ
! The set permission signal line 9 is connected to the CDR-A (the set permission signal 151 is output to this) created by the hardware (c).
It is C. (to) is the above CAR (2) and CDI'L-A
(1!9) and the clock supply line that supplies the clock to the hardware (c). In the configuration of this invention, the clock output from the OSC wire and the CPU (4)
A clock is output to this clock supply line via a selector that selects which of the externally supplied clocks to use. (31) is a useless selector. (32) is a clock line that outputs a clock signal from the oscH, and is input to the selector (61).

(33) is a clock line for supplying a clock from the outside of the CPU Ufl, and is input to the selector (31). (34) is the switching signal line of the selector (31), which causes the 08CcA clock line (32
) and cpU (11) to select which of the external clock lines (33) to use.The above is an explanation of the configuration of the CPU (1) in this invention.In the above description of this invention, [External to cPUfl)] will be explained below. A micro program debugging device (hereinafter referred to as debugging device) is shown. (65)
is the debugging device, which is composed of the hardware described below. (36) is a general-purpose processor with various processing control functions, and the c p U (
1) function of outputting a clock from the outside to the clock line (33), the switching signal line (5) of the selector (31)
4) A function to output a switching signal to the buffer game) (211), a function to output an output prohibition signal to the output prohibition signal line 211, and a function to internally store the microprogram to be debugged by human operation. A function to modify the micro program arbitrarily by human operation, and a debug device (35) described below.
It has functions such as controlling other components of the system. (67)
is the same control data as the CDR-Aa5.
This is a register (hereinafter referred to as CDR-B). (38) is the output line of this CDR-B. (39) is a buffer gate equivalent to the buffer gate Qυ, and its output line is a wired O
R and pass. (40) is this buffer game) (39
) to which the processor (66) outputs a prohibition signal. (41) is the CDR
-B (37) data input line, the processor (
36) The data is output to this. (42) is a set signal line of the CDR-B (!+7), to which a set signal is output from the processor (36). The above is the configuration of this invention.

Next, the debugging procedure of the micro program debugging system of the present invention will be explained.

The feature of the debugging procedure of this invention is that the CPIJ (1)
A debugging device (35) is connected from the outside of the computer, and all debugging procedures are performed under the control of this debugging device (35). First, the processor (36) K7
"Store the micro program you want to bag. Next, connect the clock line (62) output from the OS CrA.
and a clock line (33) output from the processor (36).
) to switch the selector (31 power cut switch signal line (34
) to the processor (66), to the processor (36)
A switching signal is output to enable the clock line (63) output from the clock line (63). In addition, the processor (36) outputs an output prohibition signal to the output prohibition signal line (2) of the buffer game (C1υ) in the CPU (1), and the buffer game (C59) in the debug device (35) is outputted by the processor (36). The output prohibition signal i@ (40) generates a signal that enables the processor (36) to output. After that, the processor (36) inputs the data to the CDR-B (37) via the data input line (41) and the set signal line (42).
The first microinstruction code of the microprogram to be debugged is stored in the processor (36) in advance, and a clock is applied to the clock line (33).
Outputs only the output. This causes the node in cpU(1) to
Since one microinstruction code and one clock are supplied to the software T25), the software T25) performs the operation corresponding to the microinstruction code once.

Next, write the second microinstruction code of the microprogram you want to debug into CDR-B (3
7) and output one clock to clock m (33). As a result, the software (25) performs the operation corresponding to the second microinstruction code once.

Thereafter, for the third and subsequent microinstruction codes of the microprogram to be debugged, the microinstruction codes and clocks are sequentially output using the same procedure as the second one. After the output of the micro program you want to debug is completed, check the operation results of the hardware (c).

If there is an error in the micro program, the processor (6
6) Correct the stored microprogram and repeat the above procedure. Furthermore, the operation results of the microprogram can be checked each time each microinstruction code and clock output is completed, or at any arbitrary point during the microprogram.

The micro program has been debugged and the micro program has finished debugging.
At the stage when the program is stored in the C-ROM+4), the debug device (35) is disconnected from the CPU (1). In this case, the clock lines (32) (33)
The switching signal line (34) of the selector (31) is 08C.
The signal polarity selects the clock line (62) output from (29), and the buffer gate 1 in cpU (11)
For the 12υ output prohibition signal line @, select the polarity of each line so that the signal polarity is on the output permission side.

The CPU (1) operates according to the clock output from the OSC (c) and the microprogram stored in the C-ROM (4).

Since this invention has more than one configuration, its advantages include the disadvantage that it is necessary to implement WCM, which is unnecessary when the CPU is in normal use, unlike conventional micro program debugging systems. can be removed.

Nil 2 and above are described in 9 for a CPU microprogram debugging system that uses a microprogram control method and requires a reduction in the amount of hardware, but this invention is applicable not only to this type of CPU but also to ordinary microprograms.・Micro・CPU for program control and special force signal processing
It may also be used in a program-controlled processor.

As explained above, according to the present invention, a debug device having a general-purpose processor is connected from outside the CPH, a micro program to be debugged is stored in the debug device, and the micro program is controlled by the debug device. Since the system configuration is for debugging,
There is no need to implement WCM and related hardware that is normally unnecessary on the CPH (there is an advantage that the CPU hardware can be reduced).

[Brief explanation of drawings]

FIG. 1 is a diagram of an example of a conventional micro program debug system, and FIG. 2 is a diagram of a micro program debug system of the present invention. In the figure, (1) is CPU, (2) is CAR, (3)
is address signal line, (4) is C-ROM, (5) is C-
1'LOM output line. (6) is WCM, (7) is address signal line, and (8) is selector. (9) is the selector switching signal line, Ql is the switch,
U is address signal line, α is data input line, θj is WC
M write signal line, H is WCM (7) Output line, u! 9 is CDR-A. αe is the selector, αη is the selector switching signal line, α ladder is the switch, α9 is the CpR-A input line, (2I is the CD
R- person's output line, +21) is the buffer gate, (goods) is the buffer gate output inhibition signal line, (c) is the switch, (goods) is the buffer gate output line, (c) is the no.
-Doware. (c) is the CAR input line, @ is the CAR set permission signal line. The wire is the CDR-A set enable signal line, @ is osc, M is the clock supply line, (!11) is the selector, (32) (
33) is a clock line, (34) is a selector switching signal line, (35) is a debug device, (36) is a processor, (37) is CDR-B, (3B) is CDR-
(39) is a buffer gate output line, (40) is a buffer gate output inhibit signal line, (41) is a data input line, and (42) is a CDR-B cellar signal line. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa

Claims (1)

[Claims] A control memorandum for storing a microprogram, and a current address register for addressing the control memory. A control that holds the microinstruction code being executed.
A microprogram-controlled CPU consisting of a data register, an oscillator, hardware controlled by a microinstruction code and a clock output from the oscillator, and a buffer gate that supplies the microinstruction code to the hardware. In a micro program debugging system, - A micro program debugging device can be connected to the CPU, and the C
Inside the PU, a selector is provided which allows the micro program debug device to select whether to use the clock output from the oscillator or the clock supplied from the micro program debug device, and the buffer. A control that wires the microinstruction code output from the gate and the microinstruction code supplied from the microprogram debugging device, and allows the microprogram debugging device to specify which microinstruction code to use. A micro program debugging system characterized by having a line.