JPH10148660A - Loop sequencer of pattern generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the cost by using a low-speed device. SOLUTION: The sequencer has a sequencer master, and the sequencer master has a coincidence circuit between a loop counter controlled by the number of loop steps and a loop buffer register, thus generating an n-phase sequence from a control circuit controlled by LOOPEXIT that indicates the final cycle of a test pattern from an optional PG(pattern generator) 3. An n-phase sequencer slave is controlled by the sequencer master. The slave side of each phase has a start address register, a register for generating and storing a jumping address, a register for calculating and storing the start address of a next loop, and an upper address counter and a lower address register that perform load or increment operation according to the data of the registers. A data select memory is accessed by the generated addresses.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a loop sequencer for a pattern generator of an IC test apparatus.

[0002]

[Prior art]

(Conventional Example 1) This type of conventional pattern generator (hereinafter referred to as PG
1) is a sequential PG as shown in FIG.
(SQPG) 2, option PG (for example, algorithmic PG; ALPG) 3, pin-direction pattern selector 4, OR circuit 5, and the like. Sequential PG2
Indicates a test pattern in a buffer memory (pattern memory) 9
The PG is a method of outputting the contents of the buffer at a high speed to form a test pattern, and is used for a logic test. On the other hand, the option PG3 uses a built-in pattern generation operation circuit (register having an operation function) 11 to store a test pattern of an IC.
G.

In the conventional PG1, the instruction memory 8, the pattern memory 9, and the option PG of the main PG2 are used.
3 has the same address A in the instruction memory 10.
Since this is a method of giving D, it is necessary to capture the pattern generation program of option PG3 as the entire sequence. When the option PG3 is a memory test ALPG, there are patterns determined by a test method such as a marching test pattern and a galloping test pattern, and the pins of the memory under test are directly connected to the device pins Pa, Pdi, and Pc as shown in FIG. 8A. , Pdo may be left as it is, but if any interface circuits 18, 19, 20, 21 are inserted between the device pins Pi, Po and the memory 17 as shown in FIG.
It is necessary to program a pattern including the interface section. (Conventional Example 2) When individually testing a memory (FIG. 8B) or the like existing inside a device under test (hereinafter referred to as a DUT), the test pattern is obtained from an option PG (for example, ALPG) 3 which is a dedicated pattern generator. Must be processed to generate a pattern that matches the interface circuit in the DUT. The test pattern is input in a sequence determined by the DUT. In order to process a pattern generated in the ALPG 3 according to the sequence, in the example of FIG. 9, a loop sequencer 22, a data select memory 25, and a selector 26 are added to the apparatus of FIG.

The operation of decomposing the test pattern of each cycle of ALPG3 according to a predetermined sequence is performed by ALPG3.
Is repeated until all the patterns are completed. This series of repetitions is called a loop. The number indicating how many test patterns in each cycle (each loop) of the ALPG 3 are decomposed is called the number of steps. The data select memory 25 stores a select signal for selecting a test pattern generated from the option PG3 in real time for each cycle of the loop sequence, and its address is given from the loop sequencer 22.

[0005]

When testing a memory IC or the like at a high speed, the selector PG3 shown in FIG.
6, the pattern data input to the selector 6 becomes faster, and accordingly, a select signal from the data select memory 25 must be supplied to the selector at a higher speed. Therefore, the address signal given from the loop sequencer 22 to the data select memory 25 must also be high speed. As described above, the conventional loop sequencer that generates an address signal at a high speed is composed of a high-speed and expensive device such as an IC, and thus has a problem that the cost of the device is increased.

An object of the present invention is to reduce the cost of a loop sequencer that generates a high-speed address signal.

[0007]

The loop sequencer according to the present invention comprises a sequencer master and an n (2 or more integer) phase sequencer / slave. Sequencer
The master includes a loop memory for storing the number of loop steps and control bits, an address pointer for giving an address of the loop memory, a loop buffer register for loading loop information from the loop memory, and giving a condition of a loop sequence. A loop counter for generating a cycle constituting each loop, a match detection circuit for detecting a match between the output of the loop counter and the loop / step number information of the loop buffer register, and a match detection signal of the match detection circuit. A loop control circuit for controlling the address pointer, the loop counter, and the loop buffer register according to a loop exit (LOOPEXIT) signal from an external option pattern generator and a control bit of the loop buffer register; Detection signal and the A control signal loop control circuit comprises a slave control circuit for generating a control signal for sequencer slave of the n phases.

The sequencer / slave of each phase includes a start address register for storing a start address,
Calculate the jump address register that generates and stores the jump destination address and the start address of the next loop,
A next loop start address register to be stored;
An upper address counter that performs load, increment, and hold operations in accordance with a control signal of a slave control circuit of the sequencer / master, and provides an upper bit of an address of an external data select memory;
Load and load are controlled by the control signal of the master slave control circuit.
A lower address register that performs a hold operation and provides lower bits of an external data select memory, and a control signal of a slave control circuit of the sequencer / master,
A control circuit that supplies a load signal to the lower address register, the jump address register, and the next loop start address register and controls the upper address counter.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. In these figures, parts corresponding to those in FIGS. 7 and 9 are denoted by the same reference numerals. (3) A pattern generator (option PG) having an original pattern for processing a generated pattern by this sequencer and having a LOOPEXIT serving as a control signal indicating the end of pattern generation . (23) The following (31) to (3)
8). (24) Sequencer / slave, the following (41)-
(52) is provided. (25) A data select memory for storing select data (control data) for each loop step based on the address given by (42) and (43). By having data to be stored having the number of phases of the slave, the operation of the sequencer / slave and the control thereof can be simplified. (31) A register for storing the start address of the loop memory by the sequencer master. (32) An address pointer indicating the address of the loop memory. (33) The number of loop steps held as necessary information each time one sequence is generated in the sequence master,
Loop memory for storing control bits. When exiting the loop, the control bit controls whether to generate a sequence based on the next loop information, hold the current loop information and perform the same sequence generation, or retrieve the loop information that has already occurred. Have a bit to do. That is, increment, hold, jump of the address pointer 32 and load and hold of the loop buffer 35 are performed. (34) A loop counter for generating a cycle constituting each loop. (35) A loop buffer register that loads loop information from a loop memory and gives conditions for a loop sequence. (36) Loop counter and loop buffer register 35
A match detection circuit that detects a match with the loop step number information. (37) The address pointer 32, the loop counter 34, and the loop buffer register 3 are determined based on the match signal detected by the match detection circuit 36, the LOOPEXIT control signal from the option PG3, and the control bit of the loop buffer 35.
A loop control circuit for performing the control of (5). (38) A slave control circuit that generates a sequencer / slave control signal that generates a loop sequence while operating in parallel after detecting the coincidence signal detected by the coincidence detection circuit 36 and the branch timing by the loop control circuit 37 . (41) A register for storing the start address of the slave side, which takes a value different from that of (31). (42) An upper address counter that gives the upper bits of the physical address of the memory 25 and performs load, increment, and hold operations according to a control signal from the sequencer master 23. (43) A lower address register that gives a lower bit of a physical address of the memory 25 and performs a load / hold operation according to a control signal from the sequencer master 23. The load data is obtained from ADD, which indicates the order in which the n-phase sequencer / slave 24 is generated. The bit width of ADD differs for each phase. (44) Control signal JMP from sequencer master 23
A jump address register loaded into the address counter 42. This register loads the contents of the start address register 41 at the start, and loads the contents of the next loop start address register 45 in response to the control signal EXIT from the sequencer master 23. (45) Control signal JMP from sequencer master 23
Is a value obtained by adding 1 to the value of the address counter 42,
That is, a next loop start address register for generating and storing a start address of a sequence to be executed after the current loop is completed. (46) An adder that generates the next loop start address from the upper address counter 42. (47) Control signal JM from sequencer master 23
A control circuit for giving a load signal to the registers (43) to (45) and controlling the operation of the counter 42 by P and EXIT. (B) Outline of operation 1) Start address register 31, loop memory 33, option PG3, start address register 4
1. Write necessary data to the lower address register 43 and the data select memory 25, and wait for activation of the sequencer.

2) When the sequencer is started by the start signal, the contents of the start address register 31 are loaded into the address pointer 32 and the loop memory 33 is loaded.
From the loop buffer register 3
5 is stored. 3) The address pointer 32 is the loop buffer register 3
5 increments at the timing of loading the loop information, and prepares the next loop information.

4) When the loop information is stored in the loop buffer register 35, the loop counter 34 starts counting from the initial value 0 at the same timing in synchronization with the operation clock. 5) The loop counter 34 is a loop buffer register 35
The increment operation is repeated until the number of steps matches.

6) When the coincidence between the number of steps in the loop counter 34 and the number of steps in the loop buffer register 35 is detected by the coincidence detection circuit 36, the control signal LOOP from the option PG3 is output.
If no EXIT has arrived, the loop counter 34 performs zero load in the cycle following the detection of a match. 7) Loop counter 34 and loop buffer register 35
Until the control signal LOOPEXIT from the option PG3 arrives, the loop counter 34 sets 5) to
The operation of 6) is repeated, and the loop buffer register 35 holds the data.

8) Control signal LOOP from option PG3
When EXIT arrives and the number of steps in the loop counter 34 matches the number of steps in the loop buffer register 35, the loop buffer register 35 controls whether to load the next loop information or retain the current information by the control bit of this register. I do. 9) When the control bit of this register is an instruction for holding the current information, the address pointer 32 and the loop buffer register 35 are in a hold state. If the control bit is an instruction to take in the next loop information, the loop buffer register 35 loads the next loop information. The address pointer 32 is incremented, and further prepares the next loop information.

10) Regardless of the control bit, the loop counter 34 loads 0 and starts counting at the same timing as the loop information is stored in the loop buffer register 35. 11) The operations 4) to 10) are repeated until the operation clock ends. 12) Sequencer slave 24 uses JM as a control signal.
P, EXIT, and ADDn are required. The start address of the loop is loaded into the address counter 42 by JMP. The start address of the next loop is loaded into the address counter 42 by EXIT. ADDn is given as the order of the next loop. These signals are
The same loop sequence can be generated for both the master and the slave by being controlled by the occurrence of a loop on the master side.

13) The sequencer / master 23 counts the coincidence signal detected by the coincidence detection circuit 36, goes back n cycles from the time when the count value coincides with the number n of phases on the slave side, and outputs a JMP signal for n cycles. I do. 14) The EXIT signal is output from the LOOPEXIT and coincidence detection circuit 36.
N cycles from the cycle of the signal generated by the logical product with the coincidence signal detected by
An XIT signal is output. Further, the ADD signal is EXIT
The first cycle in which a signal occurs is set to 0, and
It has the value of cycle count up.

15) The signals generated in 13) and 14) are decomposed into n phases and supplied to the slave side. 16) The sequencer / slave 24 stores the start address of the start address register 41 in the address counter 42 in response to the start signal, similarly to the master side. 17) The address counter 42 counts from the start address in synchronization with the operation clock from the sequencer master 23.

18) The address given to the memory 25 is
The address counter 42 has the upper bits and the lower address register 43 together. Therefore, the address given to the memory 25 is given by + n (n phase) every time the address counter 42 is incremented. 19) The jump address register 44 stores the contents of the start address register 41 at the timing when the address counter 42 loads the start address.

20) In response to the JMP signal, the address counter 42 loads the value of the jump address register 44,
Jump to the start address of the loop. As a result, the memory 25 also reads the data at the start address of the loop. 21) The upper address counter 42 increments until a control signal comes. 22) The next loop start address register 45 is loaded with a value obtained by adding +1 to the counter value of the upper address counter 42, that is, the start address in the next loop, according to the JMP signal.

23) The EXIT signal causes the address counter 42 to move to the next loop start address register 45.
Load the value of The lower address register 43 is given the value of ADD, that is, the order of the start address of the next loop. (C) Operation of upper address and lower address and data select memory The case where the number of steps is 3 and the number of phases is n = 4 will be described as an example.

Data is stored in the data select memory 25 as shown in FIG. Here, the upper bit address is 10
bit, the lower bit address is 2 bits (the number required to operate in four phases), and the memory address is 12b
It is composed of The memory addresses accessed in each phase and the stored data are as shown in FIG. Assuming that a pattern is generated in each cycle in the order of phases, the memory address indicates addresses 0 to 11 every three cycles,
The generated data represents a pattern consisting of 3 steps as 4
Repeat several times. When this is viewed as a separate operation, the upper bit address is incremented every cycle,
The operation of returning to the initial value (start value) when the number of steps matches the number of steps in the loop is repeated. Further, the lower bit addresses are given in phase order.

This phase order does not necessarily have to coincide with the phase number. That is, since the number of each phase indicates a certain cycle that evolves in the time direction, the loop step can be started from any cycle. FIG. 6 shows an example in which the loop step is started from the second phase. Similarly, in each of these cases, a pattern is sequentially generated in each cycle. In this case, the memory address is changed from address 0 to address 11 every three cycles.
The generated data repeats a pattern composed of three steps four times. Viewing this as an operation for each phase, the upper bit address is incremented every cycle, and the operation of returning to the initial value (start value) when the number of steps matches the number of steps in the loop is repeated.

Therefore, the sequencer control on the slave side is as follows:
The control of the counter 42 for giving the upper bit address and the control of the register 43 for giving the lower bit address allow
Each phase can operate independently. (D) Conclusion A cycle corresponding to the number of steps is generated based on the number of steps of the loop stored in the loop memory 33 in advance, and a sequencer is generated by a signal indicating that the step value of the loop buffer register 35 matches the loop counter 34. Generate a control signal for the slave 24; The sequencer / slave 24 divides the operation into n phases, and each sequencer / slave 24-i generates an address of the data select memory 25-i that matches the step of the loop.

The address of the data select memory 25 includes a lower address generated by the sequencer master 23,
The lower address is composed of a value of an upper address counter 42 controlled by control signals EXIT and JMP.
It is determined by the number of n phases. Upper address counter 4
2 selects the start address register 41 in the initial condition by the clear signal, increments while there is no control signal EXIT or JMP from the sequencer master 23, and increases the jump address register 4 by JMP.
Then, the contents of the next loop start address register 45 are loaded by EXIT. The same data is stored in the data select memory 25 in the same n phases, and the same data is stored n times consecutively in one phase. As a result, the number of steps is not limited to the number n of phases, and consecutive valid cycles are generated.

[0024]

According to the present invention, the loop sequencer 22 comprises a sequencer master 23 and a sequencer slave 24, and the sequencer slaves 24-1 to 24-n.
And the sequencer / slave 24-i of each phase
More corresponding data select memory 25-i (i = 1 to
An address signal may be given to n-phase configuration with n). Control signals JMP-i, EXIT-i, ADD-i given from the sequencer master 23 to the sequencer slave 24-i
Are expanded to n clock periods. Similarly, the time length (bit length) of the address signal supplied from the sequencer / slave 24-i to the data select memory 25-i is expanded to n clock cycles. The signal processing in each sequencer slave 24-i only has to handle a low-speed signal with a bit length of n clock cycles, and can be configured at low cost using a low-speed device, thereby reducing the cost of the entire loop sequencer. Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart of the main part of FIG. 1 when three steps and n = 4 phases are used.

FIG. 3 is a timing chart subsequent to the timing chart of FIG. 2;

FIG. 4 is a diagram showing a storage state of data in a data select memory 25-i in FIG. 1 when three steps and n = 4 phases are set.

FIG. 5 is a data select memory 25-1 to 25- shown in FIG. 4;
4 is a diagram showing an example of address input and output data of FIG.

FIG. 6 shows data select memories 25-1 to 25- in FIG.
4 is a diagram showing another example of address input and output data of FIG.

FIG. 7 is a block diagram of a conventional pattern generator that does not use a loop sequencer.

FIG. 8 is a block diagram showing an internal configuration when a device under test (DUT) is a memory device.

FIG. 9 is a block diagram of a conventional pattern generator using a loop sequencer.

Claims (1)

[Claims] 1. A sequencer master comprising: a sequencer master; and a sequencer slave having n (an integer of 2 or more) phases, wherein the sequencer master stores a loop step number and control bits, and a loop memory thereof. An address pointer for giving an address of a loop memory; a loop buffer register for loading loop information from the loop memory and giving a condition of a loop sequence; a loop counter for generating a cycle constituting each loop; an output of the loop counter; A match detection circuit for detecting a match with the loop / step number information of the loop buffer register; a match detection signal of the match detection circuit; a loop exit (LOOPEXIT) signal from an external option pattern generator; The address pointer is controlled by a control bit. A loop control circuit that controls a loop counter and a loop buffer register; a match control signal of the match detection circuit; and a slave control circuit that generates a control signal of the n-phase sequencer / slave based on a control signal of the loop control circuit. The sequencer / slave of each phase includes: a start address register for storing a start address; a jump address register for generating and storing a jump destination address; and a next loop for calculating and storing a start address of a next loop. A start address register, an upper address counter that performs load, increment, and hold operations by a control signal of a slave control circuit of the sequencer master, and provides an upper bit of an address of an external data select memory; A lower address register that performs load and hold operations according to a control signal of a slave control circuit and provides lower bits of an external data select memory; and a lower address register that jumps according to a control signal of a slave control circuit of the sequencer / master. A control circuit for supplying a load signal to an address register and a next loop start address register and controlling the upper address counter.