JPS592298A - Memory tester - Google Patents

Abstract

PURPOSE:To obtain an economical memory tester which can perform a test at a high speed for a memory of a nibble mode, by delivering data in parallel from a pattern generator to hold them at a register and then converting those data in series into data signals to apply them to a memory to be tested. CONSTITUTION:An incrementer 19 holds an address 201 of a memory MN which is designated first by a pattern generator 11 in a nibble mode under the control of a test rate signal produced by a timing generator 12. Then the incrementer 19 gives +1 to the held test address as soon as a parallel-input/series-output register 18 delivers successively the data 215 which are converted in series and applied to the memory MN. Thus it is possible to always hold a test address of the memory MN. The generator 12 is just needed to produce an address data which is given to a desired memory MN in the next nibble mode during test period. Therefore the test speed can be increased greatly up to quadruple, 8 times, etc. in response to the content of the nibble mode.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory tester, and in particular, to testing nibble mode memory (one that autonomously reads a predetermined number of consecutive addresses after the specified address by specifying the first address once). The present invention relates to a memory tester suitable for testing.

First, a conventional example will be explained according to the drawings.

FIG. 1 is a block diagram of an example of a conventional memory tester.

This memory tester sends address signals 101 . A pattern generator 1 provides a data signal 102 and an address signal 101 . Data signal 102. A timing generator 2 that controls the timing of the memory control signal 111, an address formatter 3 that modulates the address signal 101 into a waveform 109 that is applied to the memory MEM, and a data formatter that modulates the data signal 102 into a waveform 110 that is applied to the memory MEM. 4, a clock formatter 5 that generates a memory control signal 111 to be given to the memory MEM, and a read value 1 of the memory MEM.
12 matches the expected value (data signal 102) created by the pattern generator 1.
and a fail memory 7 that stores an address 101 in case of non-coincidence.

First, the pattern generator 1 selects timing information and creates addresses and data to be given to the memory MEM during the previous test cycle under the control of, for example, a microprogram created by a user.

The timing information selected by the pattern generator 1 indicates all memory addresses in the timing generator 2 that have various timing information.

Memo 1) M E M After one reading and writing, the timing generator 2 must always synchronize with the pattern generator 1.
It sends a test rate signal 107 to inform that the test cycle has ended, and receives the next timing select signal 108.

The test rate generator 1 sends timing information selected during the previous test cycle to the timing generator 2 as a timing select signal 108. At the same time, pattern generator 1
sends the address 101 given to the memory IJMEM to the address formatter 3, and sends the data 102 given to the memory Mf>M to the data formatter 4. These addresses and data are created by the arithmetic processing of the pattern generator 1.

The timing generator 2 generates a timing select signal 108
is input, the timing information of the memory address in the timing generator 2 that it indicates is read out, and the address formatter 3, data formatter 4, clock formatter 5, and comparator 6 are controlled according to the timing information.

The address formatter 3 outputs a waveform 1 to be applied to the 101 addresses calculated by the turn generator 1 and the memory MEM.
09 and converts it into phase signal 1 of timing generator 2.
It is output to the memo 'J M E M under the control of 03.

The data formatter 4 converts the data 102 created by the turn generator 1 into a waveform 1 that gives the data 102 to the memo 'J M E M.
10 and converts it into phase signal 1 of timing generator 2.
The data is output to the memo IJMEM under the control of 04.

The clock formatter 5 creates a memory control signal 111 under the control of the phase signal 105 of the timing generator 2, and outputs it to the memory MEM.

Further, the comparator 6 determines whether data is correctly written in the memory MEM by giving an address and other control signals, reads out the value written in the memory MEM, and compares the written value, that is, the expected value from the pattern generator 1. It is compared with the value (data 101), and if they do not match, the memory cell is defective, and its address is written and stored in the fail memory 7.

In this way, after the test of the memory ME is completed, the contents of the fail memory 7 are read out and stored in the memory ME.
Determine whether M is good or bad.

As is clear from the above, the pattern generator 1 gives an address to the memo 'JMEM' every test cycle.

It is necessary to process and create data.

On the other hand, as memories are generally becoming larger in capacity and faster, the pattern generator 1 is required to increase the bit length of the addresses it creates and to speed up arithmetic processing. In particular, the dynamic R
,In AM, due to the constraints on the number of bins in the IC package, the mainstream address multiplexing method, in which the address is divided into two and input, is the mainstream.Since the address is input in two, the operating speed of the memory decreases. . To avoid this, various operating modes have been developed, among which the nibble mode has a function to latch the address in memory and a counter for the lower two or three bits of the address, and the counter is controlled by an external control signal. By adding +1 to the address, reading and writing to the memory can be performed autonomously by adding +1 to the address. Therefore, after specifying an address once, when reading or writing consecutive addresses, it is no longer necessary to input the address three to seven times depending on the bit length of the counter in the memory, increasing the speed of the memory. becomes possible.

However, in conventional memory testers, each time a memory is written or read, a pattern generator generates a
It was processing the addresses and data given to the memory. Therefore, in order to test nibble mode memory, the pattern generator must be faster and more sophisticated, but this requires an increase in the number of parts, a larger capacity of the device, and an increase in cost and power consumption. This led to difficulties in making it economical.

The object of the present invention is to eliminate the drawbacks of the prior art mentioned above.
An object of the present invention is to provide an economical memory tester capable of quickly testing nibble mode memory.

The configuration of the memory tester according to the present invention sequentially generates and writes patterns of addresses and data for testing even in nibble mode memory, and also reads out the garbled data and compares it with the written data. In a memory tester that has a function to memorize the address if it does not match, parallel input inputs multiple pieces of test data with pattern generation in parallel and outputs them in series. A serial output register and an incrementer that always holds the test address are added so that data from the parallel input serial output register can be sequentially written into the nibble mode memory every test cycle. This is what I did.

Embodiments of the present invention will be described below based on the drawings.

FIG. 2 is a block diagram of an embodiment of the memory tester according to the present invention, and FIG. 3 is a time chart thereof.

Here, 11 is an address signal 2 that selects a test mode such as a nibble mode or a general mode, and the timing between test signals, and gives it to the memo 'JMN of the nibble mode under test.
A pattern generator 1 that calculates 01 and simultaneously creates a large number of parallel data signals 202 to be given to the memory MN.
2 is an address signal 201. Parallel data signal 202. Serial data signal 215. a timing generator for controlling timing between test signals such as memory control signals 211;
3 is an address formatter that inputs an address signal 201 from the pattern generator 11 and modulates it into a waveform 209 to be applied to the memo 'JMN; 14 is an address formatter that inputs a serial data signal 215 from a parallel input serial output register 18 to be described later; A data formatter 15 modulates a waveform 210 to be applied to IJMN, and a memory control signal 2 that controls memory MN.
The clock formatter 16 creates the clock formatter 11, and the clock formatter 16 indicates that the read value 212 of the memory MN is the expected value (parallel data signal 2
02), a comparator for determining whether it matches or not, 17
18 is a fail memory that stores the test address of the memory MN in the case of a mismatch, and 18 is a parallel memory that inputs a large number of pieces of parallel data 202 to be given to the memory MN from the pattern generator 11 in parallel and sequentially outputs it to the data formatter 14. The input serial output register, 19, is an incrementer that always holds the test address of memory MN during nibble mode testing.

First, as shown in FIG. 3, the pattern generator 11, for example, under the control of a microprogram created by the user, during the previous test period Ts' shown in FIG.
The timing information to be used at the next test period T's in FIG. Similarly, data is created in a number corresponding to the bit length of the counter of the memory tester, ie, 4 or 8 data.

The timing information selected by the pattern generator 11 indicates a memory address in the timing generator 12 at which the timing information is stored. The pattern generator 11 receives the previous test period T from the timing generator 12 as shown in FIG. 3(g).
Test rate signal 2 in the same figure (g) that indicates the end of s'
07 is given, the previous test period T in the same figure (g)
The timing information selected during s' is sent to the timing generator 12 as a timing select signal 208.

At the same time, the pattern generator 11 outputs to the address formatter 13 the address 201 calculated during the previous test cycle Ts' shown in FIG. Output to parallel input serial output register 18 in parallel.

The timing generator 12 receives the timing select signal 208 from the pattern generator 11 and reads out the timing information of the memory address in the timing generator 12 indicated by the timing select signal 208.

In other words, this timing information is nibble mode.

It is determined which of the general modes it is in. If the first judgment bit is 1'', it is the general mode, and if it is judged to be the general mode, it is determined according to the timing information written below the judgment bit. , the timing generator 12 is controlled by the full phase signal of the following: address formatter 13, data formatter 14, clock formatter 15, parallel input serial output register 18.

When the timing information is selected in the previous test cycle Ts' in FIG. The test rate signal 207 from the generator 12 is output.

When the writing of data to the memory MN is completed under the control of each phase signal, the timing generator 12 sends a test rate signal 207 to the pattern generator 11 to notify the end of the test period Ts'. The next timing select signal 208 is input.

Next, if the determination bit is '0'', it corresponds to the nibble mode, and at this time, the timing generator 12 is continuously activated 4 times, 8 times, etc. depending on the focus length of the counter in the memory MN. It is necessary to provide timing information for the memory of

For this reason, the timing generator 12, after executing the timing information of one address of its memory, FIG.
) by generating the basic test signal 216 and incrementing the address of the memory in the timing generator 12 by 1 to advance to the next address in the memory in the timing generator 12 and store the data stored at that address. Execute timing information.

At that time, the judgment bit is It OI+, so
At the 4th or 8th time, etc., the counter in Memo'JMN completes one cycle, so the nibble mode test ends.

Therefore, the final timing information judgment bit of the nibble mode is set as It 117, and the general mode is set. After executing this timing information, the timing generator 12 then sends the test rate signal 207'' in FIG. 3(g) which tells the pattern generator 11 that the nibble mode is over.
f: Output and receive the next timing select signal 208.

In the nibble mode, the timing is determined by ANDing the judgment bit of timing information in the memory in the timing generator 12 and the basic test rate signal 216 of FIG. 3(f) actually generated by the timing generator 12. The test rate signal 207 shown in FIG. 2(g) is output from the generator 12 to the pattern generator 11.

The timing generator 12 outputs the address formatter 13 .in accordance with the timing information obtained as described above.
f-Tafohmatsuta 14. Clock Formattuta 15.
Parallel input serial output register 18, incrementer 19.
Controls comparator 16.

The parallel input serial output register 18 is connected to the pattern generator 11
The timing generator 12 generates data 215 to be given to the memo IJMN, which is serially converted under the control of the basic test rate signal 207 shown in FIG. 3(f). Output to 14.

The address formatter 13 calculates the row address 217. of FIG. Column address 218 in memory MN
The phase signal 203 generated by the timing generator 12 outputs this to the memory MN under the control of the phase signal 203 generated by the timing generator 12.

The data formatter 14 outputs the serialized data 215 from the parallel input serial output register 18 to the memory MN.
The waveform is modulated into a waveform given to , and is output to the memory MN under the control of the phase signal 205 created by the timing generator 12.

At this time, the phase signal 20 generated by the timing generator 12
4, the clock formatter 15 outputs the memory control signal 211 shown in FIG. 3(a) to the memory MN.

Memo 'JMN is controlled by this memory control signal 211 to output address signals 209 . A data signal 210 is input. In the nibble mode, the counter of the memory tester is decremented by 1 due to the fall of CAS of the memory control signal 211 in FIG. 3(b), and the address is held at launch.

Under the control of the phase signal 206 generated by the timing generator 12, the comparator 16 compares and determines the value 212 read from the memory MN with the value output by the pattern generator 11, that is, the expected value (data 215).

The incrementer 19 must always indicate the same value as the test address of the memory MN. Therefore, the incrementer 19 uses the third
Under the control of the test rate signal 216 shown in FIG. 3(f), the pattern generator 11 holds the address 201 of the memory MN that is initially specified in the nibble mode. The incrementer 19 is configured such that the parallel input serial output register 18 is connected to the memory M
At the same time as sequentially outputting the data 215 given to N, the held test address is incremented by 1. Thereby, the incrementer 19 can always hold the test address of the memory MN.

In the fail memory 17, the comparator 16 is the memory IJM.
Data 212 read from N and expected value (data 215
) is inputted from the incrementer 19, and the test address 214 of the memory MN at the time when they do not match is stored.

As is clear from the above explanation, in the conventional example mentioned above,
During the test period T6 in FIG. 3(f), addresses and data to be given to the memory MN required in the next nibble mode must be created, but the pattern generator 12 according to the present invention is not suitable for the test shown in FIG. 3(g). Since it is only necessary to create the address and data to be given to the memory MN necessary for the next nibble mode during the period Ts, the number of
It is equivalent to significantly faster speed.

As explained above in detail, according to the present invention, data can be outputted from a pattern generator in parallel, held in a register, converted into a data signal serially, and given to the memory under test. In effect, this greatly speeds up the pattern generator, making the memory tester, and ultimately the memory testing process, more economical.

Significant effects can be obtained in improving efficiency and reliability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of a conventional memory tester, FIG. 2 is a block diagram of an embodiment of a memory tester according to the present invention, and FIG. 3 is a time chart thereof. 11... Pattern generator, 12... Timing generator, 13... Address formatter, 14... Data formatter, 15... Clock formatter, 1
6... Comparator, 17... Fail memo IJ,
18...Parallel input serial output register, 19...Incrementer. Agent Patent attorney Kosaku Fukuda (and 1 other person) Kaya I Kyo 3 Kaya 2 Me 2ρ

Claims (1)

[Claims] 1. For memory in nibble mode, sequentially generate and write test address and data patterns, read the written data and compare it with the vortex written data, and if they do not match, write the corresponding data. In a memory tester that has a test function that stores addresses, there is a parallel input serial register that inputs multiple pieces of test data with pattern generation in parallel and outputs them in series, and a parallel input serial register that inputs multiple test data with pattern generation in parallel and outputs the test data in series. The memory is configured such that the data from the parallel input serial output register is sequentially written into the nibble mode memory at each test cycle, and a predetermined test can be performed. Tester.