JPH11153651A - Ic test device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten initial setting time. SOLUTION: The device comprises a per system part 2 and a per pin part 3. The per system part 2 comprises a system controller 11, a timing/waveform setting I/F13, a level setting I/F14, a pattern setting I/F15, a cycle setting I/F16, and a cycle generator 17. The per pin part 3 comprises N (the number of pins of DUT) number of channel circuits, while each channel circuit comprises a timing generator 7, a waveform control circuit 6, a D/A converter 5, a pattern generator 8, a driver 4, a comparator 9, and a waveform comparison circuit 10. The system controller 11 sequentially transfers each data, of N channels, of timing/waveform, level, and pattern, and lastly transfers the cycle data common to all channels. I/Fs13, 14, and 15 store data of N channels while read one channel by one and process for transfer to a corresponding channel circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC test apparatus, and more particularly to a technique for shortening a preparation time for a device under test (DUT) before a test, that is, an initial setting time.

[0002]

2. Description of the Related Art As shown in FIG. 5, a conventional IC testing apparatus includes a par system unit 2 and a par pin unit (also referred to as a channel unit) 3. The par pin unit 3 has N DUT pins to be tested. Then, the channel circuits CH-1,
CH-2 ..., CH-N (for example, N = 512).

Each channel circuit CH-i (i = 1 to N)
Is a driver 4 for applying a test waveform to a pin of a DUT, a D / A converter 5 for supplying a high-level voltage and a low-level voltage to a driver 4 of the driver 4 and a power supply terminal of a comparator 9 described later, and a driver 4 rising at a predetermined timing. / A waveform control circuit 6 for inputting a falling test waveform, a timing generator 7 for supplying a pattern signal to the waveform control circuit 6 at a predetermined timing, a pattern generator 8 for supplying pattern data to the timing generator 7, and an output of the DUT It comprises a comparator 9 for comparing a waveform with a reference level and a waveform comparison circuit 10 for comparing the output of the comparator 9 with expected value data.

In the par system unit 2, a timing / waveform setting I / F (interface) circuit 13 processes timing / waveform data transferred from the system controller 11 by one channel at a time via the bus 12, and obtains the obtained processing. An initialization operation such as transferring the subsequent data to the internal memories of the waveform control circuit 6, the timing generator 7, and the waveform comparison circuit 10 is performed.

A level setting I / F circuit 14 processes the level setting data transferred one channel at a time from the system controller 11, stores the processed data in an internal memory, and stores the stored data in a D / A. An initialization operation such as supplying to the converter 5 is performed. But DU
During the preparation period before the actual test of T, the supply of the voltage to the power supply terminals of the driver 4 and the comparator 9 is not performed.

Furthermore, a pattern setting I / F circuit 15
Processes the pattern data transferred one channel at a time from the system controller 11 and stores it in the internal memory of the pattern generator 8. The cycle setting I / F circuit 16 processes the cycle data common to all channels transferred from the system controller 11 and supplies the processed cycle data to the cycle generator 17. The period generator 17 simultaneously supplies the period signal RATE to the pattern generators 8 of all the channels based on the inputted period data, and simultaneously outputs the period signal RATE.
And the reference clock CLK are simultaneously supplied to the timing generators 7 of all the channels.

[0007] The pattern generator 8 inputs the pattern signal PAT to the timing generator 7. In the case where the channel circuits are not divided into groups (FIG. 6A). In FIG. 6A, pi, ri, and ti (i = 1 to N) indicate the time during which the system controller 11 transfers timing / waveform data, level data, and pattern data for one channel each. It is. qi, si, ui (i = 1 to N)
Is the time during which the timing / waveform setting I / F circuit 13, level setting I / F circuit 14, and pattern setting I / F circuit 15 process the data of one channel transferred from the system controller 11, respectively. v is the time during which the system controller 11 transfers the cycle data, and w is the time during which the cycle setting I / F circuit 16 processes the data transferred from the system controller 11.

Pi + qi is the setting time of timing / waveform data of each channel, ri + si is the setting time of level data of each channel, ti + ui is the setting time of pattern data of each channel, and v + w is the setting time of periodic data common to all channels. Say .., pN are set equal to p. The other ri and ti are similarly set as r and t. Separate processing is performed for each channel, but for simplicity it is assumed that the processing time is equal, q
Put i = q, si = s, ui = u.

P = N × p, R = N × r, T = N × t (1) represents a data transfer time for N channels. Q = N × q, S = N × s, U = N × u (2) represents the processing time for N channels. All data setting time T
T is TT = P + Q + R + S + T + U + v + w (3) When grouping channel circuits N (for example, 512) pins of the DUT are replaced with n (for example, 12)
8) Each group is divided into m groups (for example, four groups of A, B, C, and D), and the corresponding per-pin portions 3 are similarly grouped into A, B, C, and D to correspond to the groups. As shown, for example, in setting of timing / waveform data, A
Data transfer and processing for n = 128 channels of the group are performed for each channel. Similarly, data transfer and processing are sequentially performed for each group of B, C, and D one channel at a time. When the setting of timing / waveform data for N channels of all groups is completed in this way, the setting of N channels of all groups of the next level data is performed, and the setting of N channels of pattern data is performed. First, set the cycle data common to all channels. Also in this case, the relations of the expressions (1), (2), and (3) hold as they are.

[0010]

SUMMARY OF THE INVENTION In a conventional test signal generator, timing / waveform data, level data,
Since the transfer of the pattern data and the cycle data from the system controller 11 and the data processing in each I / F circuit are performed in series, there is a disadvantage that the total set time TT becomes long.

Further, if a trouble occurs in data processing of a certain function (for example, timing or waveform) of a certain channel and the processing time is extended, the total set time TT is extended by the extended time. was there. The present invention aims to overcome these disadvantages.

[0012]

Means for Solving the Problems (1) The invention of claim 1 relates to an IC test apparatus comprising a par system section and a par pin section (also called a channel section). The par system section includes a system controller and a timing / waveform setting I.
/ F circuit, level setting I / F circuit, and pattern setting I / F circuit
/ F circuit, a cycle setting I / F circuit, and a cycle generator. The par pin section is composed of N (N is the number of pins of the DUT) channel circuit, and each channel circuit includes a timing generator, a waveform control circuit, a D / A converter, a pattern generator, a driver, A comparator,
And a waveform comparison circuit.

The system controller sequentially transfers N channels of timing / waveform data, N channels of level data, N channels of pattern data, cycle data, and cycle data common to all channels. The timing / waveform setting I / F circuit stores the N-channel timing / waveform data transferred from the system controller in the form of a FIFO memory, and reads out and processes the data in the FIFO memory one channel at a time. The circuit comprises a waveform control circuit, a timing generator, and an I / F circuit with a controller for transferring to a waveform comparison circuit.

The level setting I / F circuit includes a FIFO memory for storing the level data of N channels transferred from the system controller, and reads and processes the data of the FIFO memory for each channel, and processes the corresponding channel circuit. And an I / F circuit with a controller for sending to the D / A converter. The pattern setting I / F circuit includes a FIFO memory for storing the pattern data of N channels transferred from the system controller, and a FIFO memory for the FIFO memory.
An I / F circuit with a controller for reading data from the memory for each channel, processing the data, and transferring the processed data to the pattern generator of the corresponding channel circuit. Period setting I / F
The circuit includes a memory for storing the cycle data common to all channels transferred from the system controller, and an I / F circuit with a controller for reading the data from the memory, processing the data, and transferring the data to the cycle generator.

(2) The device according to the second aspect of the present invention comprises a par system section and a par pin section (also called a channel section).
The par system section includes a system controller, a decoder, and a group for the first to m-th groups (where N is the number of pins of the DUT, N = m × n; m and n are plural).
A level pattern setting I / F circuit, a period setting I / F circuit common to each group, and a period generator are included. The per pin section includes an N-channel channel circuit, and each of the channel circuits is a timing generator. , A waveform control circuit, a D / A converter, a pattern generator, a driver, a comparator, and a waveform comparison circuit.

The system controller converts the timing / waveform data for N channels, the level data for N channels, and the pattern data for N channels from the first group (for n channels) to the m-th group (for n channels). , And then transfer periodic data common to all channels. The decoder uses the data transferred from the system controller to determine the timing, waveform, level,
The pattern data is extracted and transferred to the first to m-th group timing / waveform / level / pattern setting I / F circuits, and the pin numbers (channel numbers) included in the data are decoded to obtain the first to m-th groups. Each of the m groups is identified and transferred to the timing / waveform / level / pattern setting I / F circuit of the corresponding group.

The timing / waveform / level / pattern setting I / F circuit for the i-th (i = 1 to m) group is used for timing / waveform data (or level data or pattern data) for n channels transferred from a decoder. And an I / F circuit with a controller for reading data from the FIFO memory for one channel, processing the data, and transferring the processed data to the corresponding channel circuit.

The cycle setting I / F circuit includes a memory for storing the cycle data transferred from the system controller, an I / F circuit with a controller for reading the data from the memory, processing the data, and transferring the processed data to the cycle generator. Become.

[0019]

(Embodiment 1) In the embodiment of the first aspect of the present invention, parts corresponding to those shown in FIGS. 1 and 2 and FIGS. 5 and 6 are denoted by the same reference numerals, and redundant description will be omitted. Considering the test preparation period of the conventional IC test apparatus, if significant design changes of the system controller 11 and the bus 12 are not performed, timing / waveform data, level data, pattern data, and cycle data are transferred simultaneously. It is not possible to do so, and except for the periodic data, the data must be cascaded one channel at a time.

However, each of the I / F circuits 13, 14,
The fifo memories 13b, 1
4b and 15b, and when the transferred data is stored therein, as shown in FIG.
When N channels of data are started to be stored in the FIFO memories 13b, 14b, and 15b independently of each other, 3c, 14c, and 15c can read the data one channel at a time and perform processing for N channels. . Since the transfer and processing of the periodic data need only be performed once for all channels, it can be performed within the pattern processing time U. FIG.
Is the processing time required after the timing / waveform data for N channels is transferred to the FIFO memory 13b. As shown by the dotted line in FIG. 2, the processing is started in the order of the input channels during the transfer of the timing / waveform data. The same applies to the processing of other level and pattern data.

The total set time TT is: TT = P + R + T + U (4) Since the processing of the pattern data of each channel can be performed at the same time, TT 'can be determined by either of the following equation (5) or (6). Or the larger one. Here, u is the pattern processing time for one channel.

TT ′ = P + R + T + u (5) TT ′ = P + R + T + v + w (6) Note that the memory 16 b of the cycle setting I / F circuit 16 has a FiF
oNot necessarily a memory. (Embodiment 2) N (for example, 512) channel circuits are set to n
M (for example, 128) circuits (for example, A, B,
(4 groups of C and D), and data transfer and data processing can be performed for each group. FIGS. 3 and 4 are diagrams showing an embodiment of claim 2, wherein the setting of timing / waveform data, level data, and pattern data is performed in groups, and the setting of periodic data is performed in groups. This is a case where the processing is performed in the same manner as in FIG.

For this reason, in this example, the decoder 20, which is common to each group, and the timing, waveform,
Level / pattern setting I / F circuits 21a, 21b, 21
c, 21d are provided. The system controller 11 first transfers the timing / waveform data for N channels to the decoder 20 in the order of the groups A, B, C, and D, then transfers the level data for N channels, and then transfers the pattern data for N channels. The data is transferred to the decoder 20. Finally, the cycle data is transferred to the cycle setting I / F circuit 16. Each transfer time is as shown in FIG.

The decoder 20 receives the data transferred from the system controller 11, checks the type of the data, and decodes the pin number (channel number) included in the data if the data is timing / waveform data. In the case of the A group, the write signal W is sent to the corresponding timing / waveform / level / pattern setting I / F circuit 21a. Further, it sends timing / waveform data to the data line 22.

The I / F circuit 21a includes a FIFO memory 24a
When the write signal W is applied from the decoder 20 to the write enable (Write enable) terminal WE of the FIFO memory 24a, the input data is written to the FIFO memory 24a. Start operation. When the transfer of data for n channels of the A group is started, the Fifo memory 24a stores
An H level not-empty signal is sent to the controller-equipped I / F circuit 25a. In the controller-equipped I / F circuit 25a, the read (Rea) signal is supplied while the not-empty signal is supplied to the start (Start) terminal.
d) Send the signal R to the Fifo memory 24a. FiF
In the memory 24a, while the read signal R is being supplied to the read enable terminal, the written data is sent to the I / F circuit with controller 25a in the order of writing. The controller-equipped I / F circuit 25a processes the received data, and transfers the processed data to the corresponding group A channel circuits CH-1 to CH-n. This transfer operation is performed until the not empty signal becomes L level.

Each channel circuit CH-i (i = 1 to n) is constructed in the same manner as in FIG. 1, and the built-in waveform control circuit 6, timing generator 7, and waveform comparison circuit 10 have their own channel numbers (pin numbers). ) Is detected and the memory 6
a, 7a and 10a respectively. In this manner, when the data processing of the group A of the timing waveform data (the processing time after the data transfer is Qa) is completed, the I / F circuit with controller 25a outputs a ready signal to the system controller 11 via the decoder 20. Send to

Similarly, the timing / waveform data of the n-channels of the B group is converted into the corresponding timing / waveform data.
When writing to the FIFO memory 24b of the level / pattern setting I / F circuit 21b starts, the I / F with controller is started.
After the transmission and reception of the not empty signal and the read signal R with the circuit 25b, the same data processing as described above is performed. In this way, data processing of all groups of timing / waveform data is performed.

The data processing of each group of the level data and the pattern data is performed in the same manner as in the case of the timing / waveform data described above. The processing of the cycle data is the same as in the first embodiment. As is clear from FIG. 4, the total data setting time TT in the second embodiment is the larger of the following expressions (7) and (8).

TT = P + R + T + v + w (7) TT = P + R + T + Ud (8) If processing of pattern data of n channels in each group is the same, n channels can be performed at the same time. The time TT is the larger of the following expressions (9) and (10).

TT ′ = P + R + T + u (9) TT ′ = P + R + T + v + w (10) The expressions (9) and (10) are the same as the expressions (5) and (6) in the first embodiment, respectively.

[0031]

According to the conventional technique, the data transfer from the system controller 11 to the par system unit 2 and the data processing of the par system unit 2 are performed in series for each channel. A FIFO memory is provided on the input side of the plurality of data setting I / F circuits,
The plurality of Fifo memories (13b, 14b, 15b)
Alternatively, since data is sequentially transferred from the system controller 11 to 24a to 24d), data processing can be started in order from the channel to which data transfer has been completed. In other words, data processing can be performed in parallel during data transfer from the system controller,
As a result, data setting for initialization can be performed in a shorter time than before.

In the present invention, a plurality of data setting I /
F circuit (13, 14, 15, 16 or 21a ... 21)
In d), since data processing can be performed in parallel, the entire data setting time can be shortened accordingly. Data setting I / F circuit 1 for data processing near the end
Except for 5 and 16, one data setting I / F circuit (for example, 13 or 21a) has a trouble in data processing of a certain function (for example, timing / waveform relation) of a certain channel, and the processing time is extended by ΔT time. However, other data setting I / F circuits (14, 15, 16) for processing data in parallel
Or 21b, 21c, 21d) does not affect the data processing, so that the total data set time TT is not immediately extended by ΔT time, and in many cases, processing can be performed without extending the entire data set time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart of FIG.

FIG. 3 is a block diagram showing an embodiment of the invention of claim 2;

FIG. 4 is a timing chart of FIG. 3;

FIG. 5 is a block diagram of a conventional test signal generator.

FIG. 6 is a timing chart of FIG. 5;

Claims (2)

[Claims] 1. A par system unit and a par pin unit (also referred to as a channel unit). The par system unit includes a system controller, a timing / waveform setting I / F circuit, a level setting I / F circuit, and a pattern. A setting I / F circuit, a cycle setting I / F circuit, and a cycle generator, wherein the per-pin section includes a channel circuit of N (N is the number of pins of the DUT) channel, and each of the channel circuits has a timing A generator, a waveform control circuit, a D / A converter, a pattern generator, a driver, a comparator,
A waveform comparison circuit, wherein the system controller comprises N channels of timing / waveform data, N channels of level data,
The pattern data for the channels and the cycle data common to all the channels are sequentially transferred, and the timing / waveform setting I / F circuit includes a Fifo memory for storing the timing / waveform data for the N channels transferred from the system controller. , Its FiF
and a controller I / F circuit for reading and processing data from the memory one channel at a time for each channel, and transferring the read data to a corresponding channel control circuit, timing generator, and waveform comparison circuit. The F circuit includes a FIFO memory that stores the level data of N channels transferred from the system controller, and stores the data of the FIFO memory in one memory.
I / O with controller that reads and processes each channel and sends it to the D / A converter of the corresponding channel circuit
The pattern setting I / F circuit stores a pattern data for N channels transferred from the system controller, and reads and processes the data of the FIFO memory for each channel. , I with controller to transfer to the pattern generator of the corresponding channel circuit
/ F circuit, wherein the cycle setting I / F circuit reads a memory for storing cycle data common to all channels transferred from the system controller, and reads and processes the data in the memory.
An IC test apparatus comprising: an I / F circuit with a controller for transferring to the cycle generator. 2. A par system unit and a par pin unit (also referred to as a channel unit). The par system unit includes a system controller, a decoder, and a first to m-th group (the number of pins of the DUT is N).
Where N = m × n; m and n are plural) a timing / waveform / level / pattern setting I / F circuit, and a cycle setting I / F circuit and a cycle generator common to each group. The par pin section includes an N-channel circuit, and each channel circuit includes a timing generator, a waveform control circuit, a D / A converter, a driver, a comparator, and a waveform comparison circuit. Are timing / waveform data for N channels, level data for N channels,
The pattern data for each channel is transferred in order from the first group (for n channels) to the m-th group (for n channels), and thereafter, the periodic data common to all channels is transferred. Timing / waveform / level / pattern data is extracted from the data transferred from the controller and transferred to the timing / waveform / level / pattern setting I / F circuits for the first to m-th groups, and the pins included in the data are extracted. Number (channel number)
To determine which of the first to mth groups it belongs to, and transfer it to the timing / waveform / level / pattern setting I / F circuit of the corresponding group. ) Group timing, waveform,
The level / pattern setting I / F circuit stores an n-channel timing / waveform data (or level data or pattern data) transferred from the decoder.
an iFo memory; and an I / F circuit with a controller for reading, processing, and transferring data of the Fifo memory for each channel, and transferring the processed data to a corresponding channel circuit. An IC test apparatus comprising: a memory for storing the transferred cycle data; and an I / F circuit with a controller for reading, processing, and transferring the data from the memory to the cycle generator.