JPH06119169A - Microcomputer - Google Patents

Abstract

PURPOSE:To accelerate instruction execution speed when another processing is performed by interrupting the execution of a program by a specific address and afterwards, an interrupted program is restored again. CONSTITUTION:When another processing is performed by interrupting the execution of the program by the specific address, the instruction execution speed of a microcomputer which employs pipeline processing can be accelerated by saving the address information of an instruction to be executed when it is restored and the information of an instruction itself to a stack 1, and taking out saved address information and instruction information from the stack 1 when the interrupted program is restored again.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operation in the case where a microcomputer suspends execution of a program at a specific address to perform other processing, and then tries to return to the suspended program again. .

[0002]

2. Description of the Related Art In recent years, microcomputer instruction control processes reading and decoding of instructions in parallel with instruction execution.
The mainstream is pipeline processing in which the next instruction is executed at the same time when the execution of the instruction is completed.

The structure of the conventional microcomputer shown in FIG. 5 will be described below. The program counter 3 is connected to the ROM 2 and the stack 1, and the ROM 2 is connected to the instruction queue 5 and the instruction register 4.
The instruction queue 5 is also connected to the instruction register 4.

The stack 1 is a LIFO (Last In Fast Ou).
t) type memory, and the ROM 2 is a memory in which a program is recorded. Program counter 3 is ROM
2 is a register for designating an address of an instruction to be read from the program counter 3, and an address signal is stored in the program counter 3. When the address is specified by the program counter 3, the ROM 2 sends the corresponding instruction to the instruction queue 5
It is a memory to read. The instruction register 4 is a memory that stores an instruction to be executed next by the microcomputer.

Next, the operation of the conventional microcomputer when a normal program is being executed will be described. When the program counter 3 specifies the address of the instruction to be read from the ROM 2, the ROM 2 reads the instruction corresponding to the specified address into the instruction queue 5. The instruction is temporarily stored in the instruction queue 5, and then transferred from the instruction queue 5 to the instruction register 4. These operations are operations when an instruction to be executed next is already stored in the instruction register 4, and are called instruction prefetch. On the other hand, when the instruction to be executed next is not stored in the instruction register 4, the instruction read from the ROM 2 is directly read to the instruction register 4.

When the execution of the program in the conventional microcomputer is interrupted midway, the address signal of the instruction to be executed first when returning to the program is written from the program counter 3 to the stack 1. Get caught. This is address saving.

On the other hand, when returning to the interrupted program, the saved address signal is read from the stack 1 and stored in the program counter 3. Then, the program counter 3 specifies the address of the ROM 2, and the instruction corresponding to the specified address is read from the ROM 2. The instruction to be executed next is not yet stored in the instruction register 4, and the instruction read from the ROM 2 is directly read to the instruction register 4.

[0008]

However, in the conventional configuration, the ROM is not restored after the interrupted program is restored.
At the time when the first instruction read from 2 is stored in the instruction register 4, the instruction queue 5 is in an empty state. Therefore, if the instruction immediately after the return is of a type that requires the data in the instruction queue 5, the phenomenon that the instruction cannot be executed until the data is stored in the instruction queue 5 (waiting for queue) occurs, This will reduce the instruction execution speed of the microcomputer.

The present invention is intended to solve the above problems,
The purpose is to improve the instruction execution speed of a microcomputer without causing queue waiting.

[0010]

In order to achieve the above object, the present invention is, in the first invention, a memory for storing an instruction, a program counter for designating an address to the memory, the memory or the memory. Execution of the program was interrupted, having a stack for storing the output from the program counter, a queue for storing the output from the memory, and a register for storing the output from the memory or the stack or the queue When the program returns to the program, the first instruction to be executed first is saved from the memory or the register to the stack, and the second instruction to be executed next to the first instruction is saved. When the data related to the instruction is saved from the program counter to the stack and returned to the program, the first Cycle, the data related to the second instruction is read from the stack to the program counter, the first instruction is read from the stack to the register in the next cycle, and the data related to the second instruction is read according to the data. And a means for reading the second instruction addressed by the program counter from the memory into the queue.

In the second invention, a memory for storing an instruction, a program counter for designating an address to the memory, and a control circuit for controlling and outputting an input from the memory or the program counter. Having a stack for storing the output from the control circuit, a queue for storing the output from the memory, and a register for storing the output from the memory or the control circuit or the queue, and the execution of the program is interrupted When executed, the first to be executed first when returning to the program
Is input to the control circuit from the memory or the register, and data related to a second instruction to be executed next to the first instruction is input from the program counter to the control circuit, and the control is performed. When the circuit determines whether to save the data related to the second instruction to the stack together with the first instruction, and determines to save the data related to the second instruction, and returns to the program Reads data relating to the second instruction from the stack to the program counter via the control circuit in the first cycle, and reads the first instruction from the stack via the control circuit into the register in the next cycle. Read out and addressed by the program counter in response to data relating to the second instruction When it is determined that the stored second instruction is read from the memory to the queue and the data related to the second instruction is not saved, and when the program is restored, the control is performed from the stack in the first cycle. Outputting data relating to the first instruction to the program counter via a circuit, and in the next cycle,
It is characterized in that it has means for outputting the first instruction addressed by the program counter from the memory to the instruction register according to the data relating to the first instruction.

[0012]

According to the present invention, when the program is resumed after the execution of the program is interrupted,
In the first cycle, the data related to the second instruction is read from the stack to the program counter, in the next cycle, the first instruction is output from the stack to the register, and the data related to the second instruction is output. Accordingly, it has means for outputting the second instruction addressed by the program counter from the memory to the queue, thereby suppressing the occurrence of queue waiting at the time of return after the execution of the program is interrupted. Is something that can be done.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of a microcomputer according to the first embodiment of the present invention will be described with reference to FIG.

As shown in FIG. 1, the program counter 3 is connected to the ROM 2 and the stack 1 as in the prior art, and the ROM 2 includes the instruction queue 5 and the instruction register 4.
Connected with. The instruction queue 5 is connected to the instruction register 4. The difference from the conventional technique is that the stack 1 is connected to the ROM 2 and the instruction register 4 in addition to the program counter 3.

The instruction register 4 is a first memory for storing an instruction to be executed next by the microcomputer. The instruction queue 5 is a second memory for prefetching instructions read from the ROM 2, and in this embodiment, a one-stage instruction queue is used. The stack 1 is a third memory in the LIFO format, and the ROM 2 is a memory for reading an instruction corresponding to an address designated by the program counter 3 into the instruction queue 5, and stores a program. The program counter 3 is a register for designating an address of an instruction read from the ROM 2, and the program counter 3 stores an address signal.

The operation during execution of a normal program in the microcomputer of the present invention configured as described above is the same as that of the prior art.

Next, the operation when the execution of the program is interrupted will be described. When the execution of the program is interrupted midway, the program counter 3 designates in the ROM 2 the address A1 of the instruction to be executed first when returning to the program, and the instruction (opcode) D1 corresponding to the address A1 It is read from the ROM2. The read instruction D1 is saved in the stack 1 as an instruction to be executed first when returning to the program. Then, the address signal of the address A2 (the address of the instruction to be executed next to the instruction D1 corresponding to the address A1) obtained by incrementing the address A1 up to that time by 1 is written from the program counter 3 to the stack 1.

When returning to the interrupted program, the address signal of the address A2 is read from the stack 1 to the program counter 3 prior to the instruction D1, and the program counter 3 specifies the address of the ROM 2 ( First machine cycle). The ROM 2 receives the designation of the address A2, and receives the instruction D corresponding to the address A2.
2 is read into the instruction queue 5. The instruction D1 is read from the stack 1 to the instruction register 4 following the address signal of the address A2 and stored therein. This reading of the instruction D1 is processed in parallel within the same machine cycle (second machine cycle) as when the ROM 2 reads the instruction D2 into the instruction queue 5. Therefore, the instruction queue 5 and the instruction register 4 are already in a state of storing data when the next machine cycle (third machine cycle) is started. Therefore, queue waiting that occurs to store data in the instruction queue 5 cannot occur, the execution of instructions can be efficiently processed, and the instruction execution speed can be improved.

Next, the structure of the microcomputer according to the second embodiment of the present invention will be described with reference to FIG.

The first embodiment shown in FIG. 1 is such that the control circuit 6 is interposed between the program counter 3 and the stack 1, between the ROM 2 and the stack 1, and between the instruction register 4 and the stack 1. The control circuit 6 is added to the example. The control circuit 6 determines the information to be saved in the stack 1 based on the opcode of the first instruction executed when returning.

The operation during normal program execution in the second embodiment constructed as described above is the same as in the prior art.

Next, the operation when the execution of the program is interrupted will be described. When the execution of the program is interrupted, the program counter 3 designates in the ROM 2 the address A1 of the instruction to be executed first when returning to the program, and the instruction (opcode) D1 corresponding to the designated address A1. Is read from the ROM 2.
The read instruction D1 is input to the control circuit 6 as an instruction to be executed first when returning to the program. Therefore, the address signal and instruction (opcode) of address A2, which is obtained by incrementing address A1 by 1 in stack 1,
It is determined whether the process of saving both D1 or the process of saving only the address signal of the address A1 is performed.

When the process of saving both the address signal of the address A2 and the operation code D1 is selected, the same operation as in the first embodiment is performed and the interrupted program is restored.

On the other hand, when the process of saving only the address signal of the address A1 is selected, the address of the address A1 of the instruction to be executed first when returning to the program is executed as in the conventional technique. Only signals are saved to stack 1. When returning to the interrupted program, the saved address signal of the address A1 is read from the stack 1 to the program counter 3, and the program counter 3 specifies the address A1 of the ROM 2. The specified address A from ROM2
The instruction D1 corresponding to 1 is read into the instruction register 4,
Program execution resumes.

Next, the structure of the microcomputer according to the third embodiment of the present invention will be described with reference to FIG.

As in the first embodiment, as shown in FIG. 3, the program counter 3 is connected to the ROM 2 and the stack 1, and the ROM 2 is connected to the instruction queue 5 and the instruction register 4. The instruction queue 5 is connected to the instruction register 4. The instruction register 4 is connected to the stack 1. The difference from the first embodiment is that the stack 1 is not connected to the ROM 2 and the program counter 3
And the instruction register 4 only.

The operation during execution of a normal program in the third embodiment configured as described above is the same as in the first embodiment.

Next, the operation when the execution of the program is interrupted will be described. When the execution of the program is interrupted, the instruction D1 stored in the instruction register 4 is saved in the stack 1 as the instruction to be executed first when returning to the program. Then, the address signal of the address A2 obtained by incrementing the address A1 corresponding to the instruction D1 by 1 is transferred from the program counter 3 to the stack 1
Written in.

When returning to the interrupted program, since the stack 1 is a memory formed by LIFO as in the first embodiment, the address signal of the address A2 is transferred from the stack 1 to the program counter before the instruction D1. Three
, And the program counter 3 specifies the address of the ROM 2. The subsequent operation is exactly the same as in the first embodiment. Therefore, at the same time that the instruction D1 is read from the stack 1 to the instruction register 4, the instruction D2 to be executed next to the instruction D1 is read from the ROM 2 to the instruction queue 5, so that the instruction queue 5 is generated to store data. The queue waiting that occurs cannot occur, the execution of the instruction can be efficiently processed, and the instruction execution speed can be improved.

Next, the structure of the microcomputer according to the fourth embodiment of the present invention will be described with reference to FIG.

The control circuit 6 is added to the third embodiment shown in FIG. 3 so that the same control circuit 6 is interposed between the program counter 3 and the stack 1 and between the instruction register 4 and the stack 1. It is a thing. The control circuit 6 determines the information to be saved in the stack 1 based on the opcode of the first instruction executed when returning.

The operation during normal program execution in the fourth embodiment constructed as described above is the same as that in the first embodiment.

Next, the operation when the execution of the program is interrupted will be described. When the execution of the program is interrupted, the instruction D1 stored in the instruction register 4 is saved in the control circuit 6 as an instruction to be executed first when returning to the program. Therefore, it is determined whether the process of saving both the address signal of the address A2 and the instruction (opcode) D1 obtained by incrementing the address A1 by 1 in the stack 1 or the process of saving only the address signal of the address A1 is performed. To be done.

When the process of saving both the address signal of the address A2 and the operation code D1 is selected, the same operation as in the third embodiment is performed, and the interrupted program is restored.

On the other hand, when the processing of saving only the address signal of the address A1 is selected, the address of the address A1 of the instruction to be executed first when returning to the program is selected as in the conventional technique. Only signals are saved to stack 1. When returning to the interrupted program, the saved address signal of the address A1 is read from the stack 1 to the program counter 3, and the program counter 3 specifies the address A1 of the ROM 2. The specified address A from ROM2
The instruction D1 corresponding to 1 is read into the instruction register 4,
Program execution resumes.

In the first to fourth embodiments described above, the ROM 2 is incorporated in the data processing flow, but the ROM does not necessarily have to exist inside the microcomputer, and the input is not necessary. It is only necessary to be connected to the device that outputs the command corresponding to the generated address signal. Further, it is needless to say that the number of stages of the instruction queue 5 can be one or more, and the number of instructions and addresses to be saved does not have to be limited to the number of this embodiment. Further, in the above-mentioned embodiment, the number of steps of the instruction queue is set to one, so the instruction to be saved is treated as an operation code. However, when the number of steps is expanded, it is possible to save the operand. On the other hand, the address to be saved does not need to be the address A2 which is incremented by 1 to the address A1 of the instruction executed first when returning to the interrupted program, and may be the address of the instruction executed first when returning to the interrupted program. It only needs to include data about the address.

[0037]

As is apparent from the above embodiments, according to the present invention, it is possible to suppress the occurrence of queue waiting at the time of returning to the interrupted program, so that the instruction execution speed of the microcomputer can be improved. However, the processing time of the program can be shortened, and particularly in the case of a program that uses a lot of subroutines and interrupts, it is possible to provide a microcomputer that produces a great effect.

[Brief description of drawings]

FIG. 1 is a block diagram of a microcomputer according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a microcomputer according to a second embodiment of the present invention.

FIG. 3 is a block diagram of a microcomputer according to a third embodiment of the present invention.

FIG. 4 is a block diagram of a microcomputer according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram of a conventional microcomputer.

[Explanation of symbols]

 1 stack 2 ROM 3 program counter 4 instruction register 5 instruction queue 6 control circuit

Claims (2)

[Claims] 1. A memory for storing instructions, a program counter for designating an address to the memory, a stack for storing an output from the memory or the program counter, and a queue for storing an output from the memory. And a register for storing the output from the memory or the stack or the queue, and when the execution of the program is interrupted, the first instruction to be executed first when returning to the program is executed. While saving from the memory or the register to the stack,
When the data related to the second instruction to be executed next to the first instruction is saved from the program counter to the stack and the program is returned to, the data related to the second instruction from the stack is returned in the first cycle. Reading data to the program counter, reading the first instruction from the stack to the register in the next cycle, and the second address addressed by the program counter in response to data relating to the second instruction. A means for reading instructions from the memory to the queue. 2. A memory for storing an instruction, a program counter for designating an address to the memory, a control circuit for controlling and outputting an input from the memory or the program counter, and a control circuit from the control circuit. A stack for storing an output, a queue for storing an output from the memory, and a register for storing an output from the memory, the control circuit, or the queue, and when the execution of the program is interrupted, Data relating to a second instruction to be executed next to the first instruction while inputting the first instruction to be executed first when returning to the program from the memory or the register to the control circuit From the program counter to the control circuit, and the control circuit together with the first instruction,
When it is determined whether to save the data related to the second instruction to the stack, and when it is determined to save the data related to the second instruction, and when the program is returned to, the stack is removed from the stack in the first cycle. Data relating to the second instruction is read to the program counter via the control circuit, the first instruction is read from the stack to the register via the control circuit in the next cycle, and the second instruction is read. When the second instruction addressed by the program counter in accordance with the instruction data is read from the memory into the queue and it is determined that the data regarding the second instruction is not saved, the program is returned to. In the first cycle, from the stack to the first instruction via the control circuit. Means for outputting data to the program counter, and in the next cycle, outputting a first instruction addressed by the program counter from the memory to the instruction register in accordance with data relating to the first instruction. Microcomputer having.