JPH0225933A - Data processor - Google Patents

Abstract

PURPOSE:To assure the recovery time for a peripheral device with use of a program by adding a command which stops temporarily the pipeline processing action to an instruction which gives an access to the peripheral device requiring the recovery time. CONSTITUTION:When an instruction 1 is decoded at a D stage 2, the information showing a specific stage that is stopped together with its subsequent stages is sent to an A stage 3 as a stop stage designation code 7 concurrently with the decoding result of the instruction 1. If the code 7 obtained by the instruction 1 shows the stage 3, an operand address related to the instruction 1 is calculated. Then the processing is temporarily stopped and an instruction 2 is not processed at the stage 3. Then an E stage 5 informs the end of the writing the instruction 1 to each stage with a temporary stop instruction executing end signal 8. Thus the stage 3 restarts the interrupted processing and starts the calculation of the operand access of the instruction 2. Thus it is possible to assure the recovery time on a program to a peripheral device aquiring the recovery time.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a data processing device that performs pipeline processing, and more specifically, data processing that guarantees recovery time for various devices accessed from this device. It is related to the device.

[Conventional technology]

FIG. 3 is a block diagram showing pipeline processing of a conventional data processing device. In the figure, 1 is an instruction fetch stage (hereinafter referred to as IP stage) that issues an access request to an external bus interface unit (hereinafter referred to as bus I/F unit) 6 to be described later and fetches an instruction code from memory. The instruction decode stage (hereinafter referred to as D stage) 2 decodes the instruction code, and the operand address calculation stage (hereinafter referred to as A stage) calculates the effective address of the operand specified in the decoded instruction code.
stage) 3, an operand fetch stage (hereinafter referred to as F stage) 4 which fetches operands from memory, and an instruction execution stage (hereinafter referred to as E stage) 5 which executes operations specified in the instruction code on the operands. It is connected to the. In addition, the bus I/F unit 6, which is an interface with external devices, is [F stage 1,
It is connected to A stage 3, F stage 4 and E stage 5.

Next, the operation will be explained.

The 1F stage 1 issues an access request to the bus I/F unit 6, fetches the instruction code from the memory, and outputs it to the D stage 2. The D stage 2 decodes the instruction code output from the IF stage 1 and outputs the decoding result to the A stage 3. The A stage 3 calculates the effective address of the operand specified in the instruction code. If necessary, it issues an access request to the spring 1/F unit 6, performs indirect address reference, and sends the calculated operand address to the F stage 4. Output to. The F stage 4 operates the bus I/F section 6 according to the operand address input from the A stage 3.
Issues an access request to and fetches the operand from memory. The fetched operands are output to the l system stage. The E stage 5 executes the operation specified in the instruction code on the operand input from the F stage 4. Furthermore, if necessary, an access request is issued to the bus I/F section 6, and the result of the calculation is stored in the memory. Bus I
When there is no access request from the A, F, or E stage, the /F unit 6 performs a pre-fetch of an instruction in response to an access request from the IP stage 4.

Through the pipeline processing described above, the process specified by each instruction is broken down into five processes, and by sequentially executing the five processes, the specified process is completed. Each of the five processes can be operated in parallel for different instructions, and ideally, five instructions can be processed simultaneously using the five-stage pipeline process described above, compared to the case without pipeline processing. , it is possible to obtain a data processing device having up to five times the processing capacity.

[Problem to be solved by the invention]

Pipeline processing has the potential to significantly improve the processing capacity of data processing devices as described above, and is widely used in high-speed data processing devices. However, one of the problems with pipeline processing is that
Since the pre-fetch in the previous stage of the pipeline is performed independently of instruction execution, there is a problem in that the recovery time of peripheral devices cannot be guaranteed. −
Generally, some peripheral devices used in combination with data processing equipment require a recovery time of about 250 ns, such as the I10 controller, after the bus cycle ends, and the same device cannot be accessed continuously. Then, this condition cannot be satisfied.

FIG. 4 is a conceptual diagram illustrating the operation of a conventional data processing device when instructions for accessing a peripheral device are consecutively issued in a program including operand fetch for accessing a peripheral device mapped on a memory space. At this time, the peripheral device to be accessed requires recovery time.

In FIG. 4, instruction 1 is an instruction to write to the control register of a peripheral device, and instruction 2 is an instruction to read data from the peripheral device. By the time instruction 1 is executed in E stage 5, instruction 2 has progressed to F stage 4 and accesses the peripheral devices accordingly. At this time, if instruction 1 writes to the peripheral device in E stage 5, the write access is followed by the operand fetch access of instruction 2, causing a problem that recovery time for the peripheral device cannot be secured.

This invention was made to solve this problem, and by providing a command to temporarily suspend the operation of pipeline processing in an instruction that accesses a peripheral device that requires recovery time, the number of stages of pipeline processing can be reduced. It is an object of the present invention to provide a data processing device that can easily cope with the increase in data processing speed and that can guarantee the recovery time of peripheral devices through a program.

[Means to solve the problem]

In the data processing device according to the present invention, a first instruction for accessing a peripheral device requiring recovery time is provided with a command to temporarily stop the operation of pipeline processing, and the processing of the first instruction is for a first instruction for accessing a peripheral device. means for suspending the processing of subsequent instructions when the first instruction is started at a predetermined second stage;
- Means for restarting subsequent commands that have been stopped.

[Effect]

In this invention, once the processing of the first instruction that accesses a peripheral device that requires recovery time begins in the first stage that accesses the peripheral device, subsequent instructions:
The processing is paused and the first instruction is in the second stage,
When the processing is completed, the processing of the commands that were stopped after the time is resumed, so that the recovery time of the peripheral device can be guaranteed.

〔Example〕

The present invention will be explained below based on drawings showing embodiments thereof.

FIG. 1 is a block diagram showing pipeline processing of a data processing device according to the present invention. In the figure, 1 is an external bus interface section (hereinafter referred to as bus I/F section) 6, which will be described later.
The IF stage 1 is an instruction fetch stage (hereinafter referred to as IP stage) that issues an access request to an instruction code and fetches an instruction code from memory, and the IF stage 1 is an instruction decode stage (hereinafter referred to as D stage) 2 that decodes an instruction code, The operand address calculation stage (which calculates the effective address of the operand specified in
The instruction execution stage (hereinafter referred to as E) executes the operation specified in the instruction code on the operand through the operand stage (hereinafter referred to as F stage) 4, which fetches the operand from memory (hereinafter referred to as A stage). stage) 5. In addition, the bus I/F unit 6, which is an interface with external devices, has IF stage 1, A stage 3, F stage 4, and E stage 5.
It is connected to the.

IF stage 1 issues an access request to bus I/F section 6, fetches an instruction code from memory, and outputs it to D stage 2. The D stage 2 decodes the instruction code output from the IF stage 1 and outputs the decoding result to the A stage 3. S stage 3 calculates the effective address of the operand specified in the instruction code, issues an access request to bus I/F unit 6 if necessary, performs indirect address reference, and sends the calculated operand address to F stage 4. Output. The F stage 4 issues an access request to the bus I/F unit 6 in accordance with the operand address input from the A stage 3, and fetches the operand from the memory. The fetched operand is output to the E stage. The E stage 5 executes the operation specified in the instruction code on the operand input from the F stage 4. Furthermore, if necessary, an access request is issued to the bus I/F section 6, and the result of the calculation is stored in the memory. Bus I/F
If there is no access request from the A, F, or E stages, the unit 6 performs a brief fetch of instructions based on the access request from the IF stage 4.

Further, when a command including a temporary stop command is processed in the D stage 2, a stop stage designation code 7 is sent from the D stage 2 to the A stage 3, F stage 4, and E stage 5. Then, when the processing of that instruction is completed at E stage 5, E
A temporary stop command completion signal 8 is sent from stage 5 to F stage 4, A stage 3, and D stage 2, and subsequent commands are processed in D stage 2.

FIG. 2 shows the operation of the data processing apparatus of the present invention shown in FIG. 1 when instructions for accessing peripheral devices are consecutive in a program including operand fetch that accesses peripheral devices mapped in the memory space. FIG. 2 is a conceptual diagram of instruction execution.

In FIG. 2, instruction 1 is an instruction to write to a control register of a device, and instruction 2 is an instruction to read data from a peripheral device. When the instruction 1 is decoded in the D stage 2, information on which stage to stop is sent as a stop stage designation code 7 to the A stage 3 at the same time as the decoding result of the instruction 1. In parallel with calculating the operand address of instruction 1 in A stage 3, D
In stage 2, instruction 2 is decoded. Peripheral device access by instruction l is performed in E stage 5, but in order to ensure that other stages do not access external devices by instructions after instruction 2, stop stage designation code 7 by instruction l indicates A stage 3. , Therefore, after performing operand address calculation for instruction 1, A stage 3 suspends processing and does not process instruction 2. After processing in the A stage 3, the instruction 1 reaches the E stage 5 via the F stage 4 and executes writing to the peripheral device. During this time, instruction 2 is waiting to be manually input to A stage 3 in a decoded state. The E stage 5 notifies each stage in the pipeline of the completion of writing of the instruction 1, that is, the completion of the execution of the instruction 1, by means of a pause instruction execution completion signal 8. - The A stage 3 that receives the stop instruction execution completion signal 8 resumes the suspended process and starts operand access calculation for the instruction 2. Thereafter, the pipeline processes as usual, and instruction 2 executes operand reading from the peripheral device in F stage 4.

If only the recovery time is guaranteed, it is possible to provide a period of no access before and after the actual access as a function of instruction 10, but this method monopolizes the external bus for longer than the time required to execute instruction 1. . As a result, the time that the external bus can be used for instruction prefetching, etc., decreases.
Although this will degrade the performance of the data processing apparatus, according to the present invention, execution is interrupted only for the process of accessing the device to be accessed, so that no unnecessarily degraded performance occurs.

By providing a command to temporarily stop the pipeline in this way, it is possible to guarantee the recovery time in the program for peripheral devices that require recovery time. In addition, since the stage in the pipeline to be stopped is determined when the instruction set of the data processing device is determined, even if the number of stages in the pipeline increases and the processing is subdivided, it can be easily handled.

〔Effect of the invention〕

As explained above, according to the present invention, in a data processing device equipped with a pipeline mechanism, it is possible to specify in a program regarding the access that needs to guarantee recovery time, and the pipeline Thus, it is possible to obtain a data processing device that can realize processing including temporary suspension of the process.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing pipeline processing of a data processing device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing pipeline processing of a data processing device according to an embodiment of the present invention. Conceptual diagram of instruction execution. Figure 3 is a block diagram showing vibe line processing in a conventional data processing device. Figure 4 is an instruction in a program that continuously accesses peripheral devices that require recovery time in a conventional data processing device. It is an execution conceptual diagram. 1... Instruction fetch stage 2... Instruction decode stage 3... Operand address calculation stage 4
...Operand fetch stage 5.Instruction execution stage 6.Bus interface circuit 7.Stop stage designation code 8..-Stop instruction execution completion signal In the figures, the same reference numerals indicate the same or A considerable portion is shown. IF Instruction 1 Trunk 2 Trunk 3 Instruction 3 Special 3 Instruction 4
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Claims (1)

[Claims] 1. In a data processing device that sequentially processes instructions in a first stage and a second stage by pipeline processing, processing of a first instruction including a command to temporarily stop the operation of pipeline processing. means for suspending the processing of subsequent instructions in the first stage when the instruction starts in the first stage; and means for resuming processing of the subsequent instructions in the first stage when processing of the first instruction ends in the second stage. A data processing device comprising: