JPH0652086A - Channel command prefetch control system - Google Patents

Abstract

PURPOSE:To control the chain data regardless of the data transfer performance ratio set between an I/O bus and a system bus and the transfer data quantity and to improve the data transfer performance in a channel command prefetch control system. CONSTITUTION:A channel device 1 fetches and analyzes the CCW that is pointed by the access originating side and successively carries out the start of transfer of the data on the system side and the I/O side. If the data transfer of the system side is not complete yet, the device 1 prefetches and analyzes the next CCW and stores the CCWs until a CCW prefetch buffer 3 is filled with the CCWs. Then the CCW prefetched in the buffer 3 are taken out when the data transfer of the system side is complete and the transfer of data is started at the system side based on the taken-out CCW.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a channel command prefetch control system for controlling channel command prefetch.

[0002]

2. Description of the Related Art Conventionally, a channel device is provided with a controller for each of an I / O bus and a system bus, and transfers data bidirectionally via a data buffer.

Since the I / O bus transfer performance is much slower than the system bus transfer performance, the chain data control is performed by utilizing the data transfer time difference between the I / O bus and the system bus. In this control method, there is a performance ratio between the I / O bus and the system bus (I / O bus >> system bus), and if the transfer data amount is appropriate, the chain data processing appears within the data transfer time. As a whole, the transfer performance almost equal to the I / O bus transfer performance was obtained in the entire system.

[0004]

However, in recent years, I / O
The data transfer performance of the bus has improved and is almost the same as the system bus. Therefore, the data transfer time difference between the I / O bus and the system bus is almost eliminated, and in the conventional transfer control method, the chain data processing time appears in the data transfer time as shown in FIGS.
There is a problem that the transfer performance of the entire system is reduced as compared with the data transfer performance of both the bus and the system bus. The operation of the configuration shown in FIGS. 6 and 7 will be briefly described below.

FIG. 6 shows an explanatory view of the prior art. FIG. 6A shows an example of the CCW pattern. Here, CCW
1 is a pattern in which CCW2 and CCW3 are issued consecutively and an access request is made. The chain data processing sequence when this CCW pattern is a write is shown in FIG. 6B, and the chain data processing when a read is performed. The sequence is shown in FIG. Here, in order to simplify the explanation, it is assumed that: System bus transfer rate = I / O bus transfer rate. That is, the I / O bus transfer rate is high and the same as the system bus transfer rate.

FIG. 6B shows an example of a chain data processing sequence at the time of writing. (1) CCW1 fetch, CCW1 analysis, system transfer activation (representing system bus data transfer activation, hereinafter the same), and I / O transfer activation (representing I / O bus data transfer activation, hereinafter the same) are sequentially executed. This makes CC
W1 system bus data transfer is performed, followed by CCW1 I / O bus data transfer, and data transfer from the main memory to the I / O device (write).

(2) After the system bus data transfer is completed, CCW2 fetch, CCW2 analysis, and system transfer start are sequentially executed. This makes CCW
2 system bus data transfer is performed, followed by CCW2 I / O bus data transfer, and data transfer to the I / O device (write).

(3) Similarly, after the system bus data transfer is completed, CCW3 fetch, CCW3 analysis, and system transfer start are sequentially executed. This makes CCW
3 system bus data transfer is performed, followed by CCW3 I / O bus data transfer, and data transfer to the I / O device (write).

(4) Then, when the system bus data transfer ends and the I / O bus data transfer ends, a series of processing of CCW1, CCW2, and CCW3 ends. Here, when it is described as a loss time of, in the figure, even though the I / O bus data transfer ends and the next system bus data transfer can be started, it cannot be started.
There was a problem that it became a loss time and the overall data transfer speed decreased. In order to eliminate these loss times, CCW prefetch, CCW analysis, etc. are performed at the position described as idle time to prevent the idle time of I / O bus data transfer from occurring, and as a result, the overall data transfer rate of the channel device. Is desired to be improved.

FIG. 7C shows an example of a chain data processing sequence at the time of reading. (1) CCW1 fetch, CCW1 analysis, system transfer start, and I / O transfer start are sequentially executed. This allows
CCW1 system bus data transfer with
The CW1 I / O bus data is transferred, and the data is transferred from the I / O device to the main memory (read).

(2) After the system bus data transfer is completed, CCW2 fetch, CCW2 analysis, and system transfer start are sequentially executed. This makes CCW
2 system bus data transfer is performed.

(3) Similarly, after the system bus data transfer is completed, CCW3 fetch, CCW3 analysis, and system transfer start are sequentially executed. This makes CCW
3 system bus data transfer is performed. In these cases, I
In the / O bus data transfer, the I / O transfer is activated at the time of (1), and the I / O bus data transfer is continuously performed like CCW1, CCW2, and CCW3.

(4) Here, the I / O bus data transfer is completed by sequentially performing three CCW1, CCW2, and CCW3. On the other hand, system bus data transfer is
CCW1, CCW for system bus data transfer
2. Since CCW fetch, CCW analysis, and system transfer start are performed every time CCW3 ends, there is a problem that a loss time occurs and the overall data transfer time is reduced. In order to eliminate this loss time, CCW prefetch, CC at the position described as idle time
It is desired to perform W analysis or the like to prevent the idle time of the system bus data transfer from occurring and consequently improve the overall data transfer rate of the channel device.

The present invention solves these problems by
The purpose is to improve the data transfer performance by performing chain data control without being affected by the data transfer performance ratio of the I / O bus and the system bus and the transfer data amount.

[0015]

[Means for Solving the Problems] Means for solving the problems will be described with reference to FIG. In FIG. 1, a channel device 1 is provided between a system bus and an I / O bus to mutually transfer data, and is provided with a CCW prefetch buffer 3 and the like.

The CCW prefetch buffer 3 stores the prefetched C
This is a buffer for storing CW (channel command word).

[0017]

According to the present invention, as shown in FIG.
Fetches, analyzes the CCW specified by the access source,
After the system side data transfer start and the I / O side data transfer start are sequentially executed, the end of the system side data transfer is monitored, and when it is not completed, the next CCW is prefetched, analyzed, and the CCW prefetch buffer 3 is full. Until the end of the data transfer on the system side, this CC
The prefetched CCW is fetched into the W prefetch buffer 3, and the system side data transfer is started based on this.

At this time, as the CCW prefetch buffer 3,
A CCW prefetch buffer 3 is provided for each CCW write and read, and after the I / O side data transfer is activated and before the system side data transfer ends (idle time), the next CCW is prefetched, analyzed, and the corresponding write is performed. Alternatively, the read CCW prefetch buffer 3 is stored until it is full, and at the end of the data transfer on the system side, the prefetched CCW is taken out,
Based on this, the system side data transfer is activated.

Therefore, regardless of the data transfer performance ratio of the I / O bus and the system bus and the amount of transfer data, CCW prefetch and CCW analysis are performed during idle time to perform CCW.
By storing the data in the prefetch buffer 3 and controlling the data transfer based on this prefetched CCW, the overall data transfer performance of the channel device 1 can be improved.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the construction and operation of an embodiment of the present invention will be described in detail with reference to FIGS.

FIG. 1 shows a block diagram of an embodiment of the present invention.
In FIG. 1, the channel device 1 includes a system bus and I / O.
It is provided between the bus and the O bus to mutually transfer data, and is composed of the memory 2, the data buffer 6, the system bus controller 7, the I / O bus controller 8, and the like.

The memory 2 stores various data, is provided with a buffer, and the like.
A CW prefetch buffer 3, a CCW-SYS buffer 4, a CCW-I / O buffer 5 and the like are provided.

The CCW prefetch buffer 3 is a buffer for storing prefetched CCW. CCW-SYS
The buffer 4 is a buffer that stores the current CCW for starting the system bus controller 7 (see (c) of FIG. 5).

The CCW-I / O buffer 5 is a buffer for storing a current CCW for starting the I / O bus controller 8 (see (d) of FIG. 5). Data buffer 6
Is a buffer for temporarily storing data to be transferred.

The system bus controller 7 controls the system bus data transfer and is composed of a control register 71, an MS address 72, a data counter 73 and the like.

The control register 71 is a register for storing various control data for controlling system bus data transfer. The MS address register 72 is a register that stores the MS address.

The data counter 73 is a counter that counts the number of data to be transferred in the system bus. I
The / O bus controller 8 controls the I / O bus data transfer, and is composed of a control register 81, a data count 82, and the like.

The control register 81 is a register for storing various control data for controlling the I / O bus data transfer. The data counter 73 is a counter that counts the number of pieces of data transferred in the I / O bus data.

The MPU 9 is a microprocessor that performs various controls. Main memory (MS) 10
Is the main memory of the computer system. I / O
An input / output device 11 is, for example, a magnetic disk device.

Next, the operation of the configuration of FIG. 1 will be described in detail according to the order shown in the flow charts of FIGS.
In FIG. 2, S1 performs CCW fetch.

In step S2, CCW analysis is performed. In S3, the system side data transfer is activated. S4 starts data transfer on the I / O side. These S1 to S4 are, for example, CCW1 fetch, CCW1 analysis, and system transfer activation in FIG. 4B in the case of a write (write instruction) CCW, and in FIG. 4 () in the case of a read (read instruction) CCW. c) CCW
1 fetch, CCW1 analysis, and system transfer start.

In step S5, it is monitored whether the transfer on the system side is completed. In the case of YES, the process of starting the system bus data transfer of the next CCW that has been preempted is performed in S6 to S9. On the other hand, if NO, the process proceeds to S10.

In S10, when the transfer on the system side is not completed, it is monitored whether or not the transfer on the next I / O side is completed. If YES, the next CCW that has been prefetched through S11 to S15.
I / O system bus activation processing. On the other hand, NO
In the case of, the process proceeds to S16 of FIG.

In S16 of FIG. 3, when the transfer on the system side and the transfer on the I / O side are not completed, it is monitored whether the CCW prefetch is completed. If YES, S16 to S24
Therefore, CCW is pre-empted. On the other hand, if NO, the process proceeds to S25.

In step S25, it is determined whether the system has stopped. In the case of YES, it is further determined whether it is the I / O side stop, the process ends when YES, and returns to S5 when NO.
On the other hand, if NO, the process returns to S5. The details will be described below.

(1) When the system side transfer is completed (S
If YES in 5): In S6, it is determined whether the CDF (chain data flag) is on. Here, turning on the CDF is
It is determined whether the chain data flag is set to ON in the CCW-SYS buffer 4 of FIG. 5C and the next CCW is prefetched in the CCW prefetch buffer 3. Y
In the case of ES, the process proceeds to S7 and S8. On the other hand, in the case of NO, the system side STOP is set in S9 (thus, YES is obtained in S25).

In step S7, a CCW-SYS buffer is created (expanded from the CCW prefetch buffer 3). More specifically, the CDF of the CCW-SYS buffer 4 in S6.
Since the (chain data flag) is on, the next CCW is fetched from the next CCW address, the CCW fetched is expanded, and the system side data transfer start preparation is made.

In step S8, the system side data transfer is activated. Regarding YES in S5 and S6 to S8 described above, FIG.
The explanation will be as follows according to the configuration of.

When the system bus data transfer is completed, a system side transfer completion report is sent from the system bus controller 7, so the micro (MPU 9 micro) detects it (YES in S5) and executes the system bus data transfer processing in S6 and thereafter. To do. At this time, if there is a chain data instruction in the completed system bus data transfer (CDF is on, YES in S6), the next CCW is taken out from the CCW prefetch buffer 3 (if prefetch is not in time, next Fetch CCW and perform chain data processing), create CCW-SYS (system current CCW), and activate the next system bus data transfer (S7, S8). On the other hand, when there is no chain data instruction (CDF is off, S6 is NO), SYS-
The STOP flag is set (this causes Y in S25).
ES).

(2) When the transfer on the I / O side is completed (S1
(YES in 0): In S11, it is determined whether the CCW is WRITE. If YES, the process proceeds from S11 to S14. On the other hand, in the case of NO, since the CCW of READ is found, the I / O side STOP is set in S15 (therefore, YES in S26).

In step S12, it is determined whether the CDF is on. Here, when the CDF is turned on, it is determined whether the chain data flag is set to on in the CCW-I / O buffer 4 of FIG. 5C and the CCW of the next write is prefetched in the CCW prefetch buffer 3. If YES, S1
3. Go to S14. On the other hand, if NO, then in S15 I
Set STOP on the / O side (this causes Y in S26
ES).

In step S13, a CCW-I / O buffer is created (expanded from CCW-SYS). S14 is I /
Start O side data transfer.

YES in S10, S11 to S15
The above will be described in accordance with the configuration of FIG. 1 as follows. When data transfer on the I / O bus ends, I / O
Since the I / O side transfer end report is sent from the bus controller 8, the micro (micro of MPU 9) detects (S1
(YES of 0), the I / O bus data transfer process after S11 is executed. At this time, if the completed I / O bus data transfer is a write transfer and there is a chain data instruction (S11 YES and S12 YES), the system current CCW (CCW-SYS) changes to the I / O current CC.
W (CCW-I / O) is created and the next I / O bus data transfer is activated (S13, S14). On the other hand, lead C
I / O if there is no CW or chain data instruction
-The STOP flag is set (this causes YES in S26).

(3) Prefetching when the CCW prefetching is not completed (when the CCW-PF-END flag is not set) and the CCW prefetching buffer 3 is not FULL (YES in S16, NO in S17) Case): In S18, CCW prefetch is performed.

In step S19, it is determined whether a fetch error has occurred. If YES, error processing is performed. In the case of NO, since the CCW was successfully prefetched, S20
Proceed to.

In step S20, CCW analysis is performed. In S21, it is determined whether or not there is a parameter error. If YES, error processing is performed. If NO, the process proceeds to S22.

In S22, the CCW BUF (CCW prefetch buffer 3) is registered. S23 is CDF OFF
It is determined whether or not the chain data flag is off, that is, the next CCW is not set. If YES, it is determined that there is no next CCW, so the CCW prefetch is ended in S24. On the other hand, in the case of NO, since there is the next CCW, it is repeated.

In the case of YES in S16 and NO in S17, the CCW prefetching process of S17 to S24 will be described below in accordance with the configuration of FIG. CCW preemption is not completed (CCW-PF-EN
When the D flag is not set) and the CCW prefetch buffer 3 is FULL (not full) (Y in S16)
In the case of S and NO in S17), the CCW fetch address is extracted from the next CCW address of the CCW prefetch buffer control table (CCW BUF) of FIG. 5A, the CCW prefetch and the CCW analysis are performed, and the CCW to which the buffer write pointer points Prefetch buffer 3 (CCW
This CCW data is registered in BUF) (S22), and the next CCW address and buffer write pointer are updated. At this time, the chain data flag is off in the pre-fetched CCW (when there is no chain data instruction)
, A CCW-PF-END flag is set, and pre-fetch end is set (hereinafter, NO in S16).

(4) When data transfer is completed (YES in S25 and YES in S26): Data transfer monitoring loop (S5, S10, S16, S17, S25, S)
26) and the series of data transfer ends.

FIG. 4 shows an example of the chain data processing sequence of the present invention. Where system bus transfer rate = I /
O bus transfer rate. FIG. 4A shows a CCW pattern. This shows a pattern for continuous data transfer with CCW1, CCW2, and CCW3. The chain data processing sequence at the time of writing in this pattern is shown in FIG. 4B, and the chain data processing at the time of reading is shown. The sequence is shown in FIG.

FIG. 4B shows an example of a chain data processing sequence at the time of writing. Where A, B, B ',
C, C ′, D, D ′, E and F correspond to the processing of the parts described in FIGS. 2 and 3. The operation will be described below.

(1) CCW1 fetch, CCW1 analysis, system transfer start (system bus data transfer start), and I / O transfer start (I / O bus data transfer start) are sequentially executed. As a result, the CCW1 system bus data transfer is performed at, and the CCW1 I /
O bus data transfer is performed, and data transfer from the main memory to the I / O device is started (A in FIG. 2 at the time of writing).

(2) Then, following the I / O transfer activation of (1), CCW2 fetch (prefetch of CCW2) and CCW2 analysis are performed and registered in the CCW prefetch buffer 3 (B in FIG. 3).

Since the system bus data transfer of CCW1 in (3) is completed, CCW2 prefetch in B, C
The CW2 is analyzed and the CCW2 registered in the CCW prefetch buffer 3 is taken out, and the system transfer is activated based on this (C in FIG. 2). As a result, the CCW2 system bus data transfer is performed.

Since the I / O bus data transfer of CCW1 of (4) is completed, the I / O transfer is activated at D. As a result, the CCW2 I / O bus data transfer is performed. (5) Then, following the I / O transfer activation of (4), CC
W3 fetch (prefetch of CCW3) and CCW3 analysis are performed and registered in the CCW prefetch buffer 3 (B 'in FIG. 3).

Since the system bus data transfer of CCW2 in (6) is completed, CCW3 prefetch at B ',
CCW3 is analyzed, CCW2 registered in CCW prefetch buffer 3 is taken out, and system transfer is started based on this (C 'in FIG. 2). As a result, the CCW3 system bus data transfer is performed.

Since the I / O bus data transfer of CCW2 in (7) is completed, the I / O transfer is activated at D '. As a result, the CCW3 I / O bus data transfer is performed. When the system bus data transfer of CCW3 of (8) is completed and the I / OB bus data transfer of CCW3 is completed, a series of data transfer is completed.

In the above chain data processing sequence at the time of writing, CCW prefetch and CCW analysis are performed at B and B ', that is, at idle time (idle time from activation of I / O transfer to activation of next system transfer). 6 to perform CCW fetching and CCW prefetching buffer 3, fetching the CCW prefetching buffer 3 to start system bus data transfer, and performing CCW fetch and CCW analysis after the completion of I / O bus data transfer. It is possible to solve the problem in the processing sequence and improve the overall data transfer rate of the channel device, and FIG. 4C shows an example of a chain data processing sequence at the time of reading. Where A, B, B ', C, C',
E and F correspond to the processing of the parts described in FIGS. 2 and 3. The operation will be described below.

(1) CCW1 fetch, CCW1 analysis, system transfer start (system bus data transfer start), and I / O transfer start (I / O bus data transfer start) are sequentially executed. As a result, CCW1 system bus data transfer is performed at, and then CCW1 + CC
I / O bus data transfer of W2 + CCW3 is performed, and data transfer from the main memory to the I / O device is started (A at the time of reading in FIG. 2).

(2) Then, following the I / O transfer activation of (1), CCW2 fetch (prefetch of CCW2), CCW2 analysis, CCW3 fetch, CCW3 analysis are performed and registered in the CCW prefetch buffer 3 (see FIG. 3). B, B ').

Since the system bus data transfer of CCW1 in (3) is completed, CCW2 prefetch, C
The CW2 is analyzed and the CCW2 registered in the CCW prefetch buffer 3 is taken out, and the system transfer is activated based on this (C in FIG. 2). As a result, the CCW2 system bus data transfer is performed.

Since the system bus data transfer of CCW2 in (4) is completed, the CCW prefetch buffer 3 is sent at C '.
The CCW3 registered in (1) is taken out, and the system transfer is activated based on this (C 'in FIG. 2). This gives C
Performs CW3 system bus data transfer.

CCW1 + CCW2 + CCW of (5)
Since the I / O bus data transfer of No. 3 is completed, it ends (F in FIG. 2). Since the system bus data transfer of CCW3 in (6) is completed, it ends (E in FIG. 2).

In the above chain data processing sequence at the time of reading, CCW prefetch and CCW analysis are performed at B and B ', that is, at idle time (idle time from activation of I / O transfer to activation of next system transfer). Is performed to register in the CCW prefetch buffer 3, fetch it, and activate the system bus data transfer to perform CCW fetch and CCW analysis after the end of the I / O bus data transfer. FIG. 5 shows an example of the table / buffer of the present invention, which can solve the problems in the processing sequence and improve the overall data transfer rate of the channel device.

FIG. 5A shows an example of the CCW prefetch buffer control table. The CCW prefetch buffer control table is here: buffer write pointer: CCW prefetch buffer write address buffer read pointer: CCW prefetch buffer read address buffer counter: CCW number registered in CCW prefetch buffer buffer control flag: CCW prefetch Buffer information-End flag for prefetching all CCWs (CCW-PF-END
Flag), CCW prefetch buffer full flag, etc. • Next CCW address: Set the CCW address to be prefetched next.

FIG. 5B shows the CCW prefetch buffer 3
For example: The CCW prefetch buffer 3 has a write buffer and a read buffer, and points from the CCW prefetch buffer control table. The CCW prefetch buffer 3 is here: CCW: MS address Transfer data byte count Next CCW address Transfer control information: Chain data flag (CDF) Data transfer activation information: In SYS bus controller Control register Set data (write / read, start) -CCW analysis information: -Set CCW parameter check error information (MS address boundary error).

FIG. 5C shows an example of the CCW-SYS buffer 4. In the CCW-SYS buffer 4, here are set: CCW: MS address transfer byte count transfer control information (chain data flag, CDF) next CCW address.

FIG. 5D shows an example of the CCW-I / O buffer 5. In the CCW-I / O buffer 4, here are set: CCW: MS address transfer byte number transfer control information (chain data flag, CDF) next CCW address.

[0069]

As described above, according to the present invention,
The channel device 1 fetches and analyzes the instructed CCW,
After the system side data transfer start and the I / O side data transfer start are sequentially executed, the end of the system side data transfer is monitored and the next CC
W is prefetched, analyzed, stored in the CCW prefetch buffer 3 until it is full, and at the end of the system side data transfer, the prefetched CCW is taken out and the system side data transfer is started based on this. Since the configuration is adopted, the overall data transfer performance of the channel device 1 can be improved. Particularly, when the system bus transfer rate is substantially equal to or slower than the I / O bus transfer rate, the chain data processing can be prevented from appearing within the data transfer time, and as a result, the overall data transfer rate can be improved. Further, in chain data processing including a CCW with a small data transfer amount, the system side data transfer can be started immediately after taking out the CCW prefetched into the CCW prefetch buffer 3, and the overall data transfer speed can be improved.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a flowchart explaining the operation of the present invention.

FIG. 3 is a flowchart for explaining the operation of the present invention.

FIG. 4 is an example of a chain data processing sequence of the present invention.

FIG. 5 is an example table / buffer of the present invention.

FIG. 6 is an explanatory diagram of a conventional technique.

FIG. 7 is an explanatory diagram of a conventional technique.

[Explanation of symbols]

 1: Channel device 2: Memory 3: CCW prefetch buffer 4: CCW-SYS buffer 5: CCW-I / O buffer 6: Data buffer 7: System bus controller 8: I / O bus controller 9: MPU 10: Main memory ( MS) 11: I / O

Claims (2)

[Claims] 1. In a channel command prefetch control method for controlling channel command prefetch, a C storing a prefetched CCW (channel command word).
Channel device (1) provided with CW prefetch buffer (3)
Is placed between the system bus and the I / O bus, and the channel device (1) is CCW instructed by the access source.
Fetch, parse, system side data transfer start and I
After the start of the data transfer on the / O side in sequence, when the end of the data transfer on the system side is monitored and not completed, the next C
The CW is prefetched, analyzed, stored in the CCW prefetch buffer (3) until it is full, and the CCW prefetched to the CCW prefetch buffer (3) is taken out at the end of the system side data transfer, and the system is based on this. A channel command prefetch control method characterized by being configured to activate data transfer on the side. 2. The CCW prefetch buffer (3),
A CCW prefetch buffer (3) is provided for each CCW write and read, and the next CCW is prefetched and analyzed until the system side data transfer is completed after the I / O side data transfer is activated (idle time). The channel command prefetch control method according to claim 1, wherein the CCW prefetch buffer (3) for the corresponding write or read is stored until it is full.