JPS57162034A - Data processing system - Google Patents
Data processing systemInfo
- Publication number
- JPS57162034A JPS57162034A JP56047480A JP4748081A JPS57162034A JP S57162034 A JPS57162034 A JP S57162034A JP 56047480 A JP56047480 A JP 56047480A JP 4748081 A JP4748081 A JP 4748081A JP S57162034 A JPS57162034 A JP S57162034A
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- return address
- executing
- register
- jump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
- G06F9/4482—Procedural
- G06F9/4484—Executing subprograms
- G06F9/4486—Formation of subprogram jump address
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
Abstract
PURPOSE:To remove a blank of 1 machine cycle in case when a return address is executed, by providing an instruction stack, fetching an instruction of the return address in parallel when a jump instruction is executed, and holding the return address of a data bus. CONSTITUTION:To a data bus of a processor for executing the data processing, a program counter 2, a register group 8 and an instruction stacker 4 are connected. Also, an address counter 3 for inputting an output of the counter 2, an instruction buffer register 5, an instruction register 6, a data register 7, an operating device ALU1 for executing the program processing, etc. are provided. In this state, an instruction of a return address is fetched in parallel with execution of a jump instruction, the return address of the data bus is held in the stacker 4, a blank of 1 machine cycle in the course of executing the return address is removed, and a speed for executing the instruction containing a jump is increased.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56047480A JPS57162034A (en) | 1981-03-31 | 1981-03-31 | Data processing system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56047480A JPS57162034A (en) | 1981-03-31 | 1981-03-31 | Data processing system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57162034A true JPS57162034A (en) | 1982-10-05 |
| JPS6132699B2 JPS6132699B2 (en) | 1986-07-29 |
Family
ID=12776292
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56047480A Granted JPS57162034A (en) | 1981-03-31 | 1981-03-31 | Data processing system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57162034A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6254342A (en) * | 1985-08-30 | 1987-03-10 | アドバンスト・マイクロ・デイバイシズ・インコ−ポレ−テツド | Digital instruction processor |
| JPH06119169A (en) * | 1992-10-06 | 1994-04-28 | Matsushita Electric Ind Co Ltd | Microcomputer |
-
1981
- 1981-03-31 JP JP56047480A patent/JPS57162034A/en active Granted
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6254342A (en) * | 1985-08-30 | 1987-03-10 | アドバンスト・マイクロ・デイバイシズ・インコ−ポレ−テツド | Digital instruction processor |
| JPH09171463A (en) * | 1985-08-30 | 1997-06-30 | Advanced Micro Devicds Inc | Method for processing of interrupt routine by digital instruction processor controller |
| JPH06119169A (en) * | 1992-10-06 | 1994-04-28 | Matsushita Electric Ind Co Ltd | Microcomputer |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6132699B2 (en) | 1986-07-29 |
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