JPS54122040A - Electronic computer - Google Patents

Electronic computer

Info

Publication number
JPS54122040A
JPS54122040A JP2940178A JP2940178A JPS54122040A JP S54122040 A JPS54122040 A JP S54122040A JP 2940178 A JP2940178 A JP 2940178A JP 2940178 A JP2940178 A JP 2940178A JP S54122040 A JPS54122040 A JP S54122040A
Authority
JP
Japan
Prior art keywords
instruction
word
memory
buffer register
control part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2940178A
Other languages
Japanese (ja)
Inventor
Yukiro Shiraokawa
Keizo Aoyanagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP2940178A priority Critical patent/JPS54122040A/en
Publication of JPS54122040A publication Critical patent/JPS54122040A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To perform definitely an operand data process at an address boundary with a high-speed instruction-word read from a main memory unit, by leading the output bus of an instruction buffer register to various registers required for instruction excution inside of an arithmetic processor.
CONSTITUTION: In arithmetic controller 3 which constitutes an instruction executed, after being read out from memory board 1 by way of memory board 1, main memory unit, stored with instruction and data word by word and memory board control part 2, as long as the length obtained by multiplying a half word, word-unit instructions read out from memory board 1 are stored temporarily in an instruction buffer register inside of memory data control part 6. Then, the output of this instruction buffer register is made into the half-word bus constitution. Under the control of the instruction address register inside of memory address control part 3, the output bus of the instruction buffer register is led to various registers required for instruction execution in the arithmetic controller.
COPYRIGHT: (C)1979,JPO&Japio
JP2940178A 1978-03-15 1978-03-15 Electronic computer Pending JPS54122040A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2940178A JPS54122040A (en) 1978-03-15 1978-03-15 Electronic computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2940178A JPS54122040A (en) 1978-03-15 1978-03-15 Electronic computer

Publications (1)

Publication Number Publication Date
JPS54122040A true JPS54122040A (en) 1979-09-21

Family

ID=12275109

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2940178A Pending JPS54122040A (en) 1978-03-15 1978-03-15 Electronic computer

Country Status (1)

Country Link
JP (1) JPS54122040A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61214029A (en) * 1985-03-18 1986-09-22 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Command forestalling buffer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61214029A (en) * 1985-03-18 1986-09-22 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Command forestalling buffer

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