JPS6418843A - Cache memory device - Google Patents

Cache memory device

Info

Publication number
JPS6418843A
JPS6418843A JP62176363A JP17636387A JPS6418843A JP S6418843 A JPS6418843 A JP S6418843A JP 62176363 A JP62176363 A JP 62176363A JP 17636387 A JP17636387 A JP 17636387A JP S6418843 A JPS6418843 A JP S6418843A
Authority
JP
Japan
Prior art keywords
address
instruction
access
cache memory
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62176363A
Other languages
Japanese (ja)
Inventor
Yuzo Omori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62176363A priority Critical patent/JPS6418843A/en
Publication of JPS6418843A publication Critical patent/JPS6418843A/en
Pending legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)

Abstract

PURPOSE:To increase the working speed and the hardware quantity of a processor by using a 1st cache memory for access of operands and branch instructions and a 2nd cache memory for access of instructions. CONSTITUTION:A instruction is prefetched by an instruction address stored in an advance instruction address register 7 in parallel with execution of an instruction carried out by an instruction execution control part 12. A logical address of the register 7 is converted into a real address by an instruction address converting buffer 9. This real address gives an access to a 2nd cache memory 4. The contents of the register 7 are replaced by a counter with an instruction access request and the next instruction access address is shown. At the same time, an operand address is produced by an operand address production circuit 10 and converted into a real address by an operand address converting buffer 11. Then an access is given to the 1st cache memory 3.
JP62176363A 1987-07-14 1987-07-14 Cache memory device Pending JPS6418843A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62176363A JPS6418843A (en) 1987-07-14 1987-07-14 Cache memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62176363A JPS6418843A (en) 1987-07-14 1987-07-14 Cache memory device

Publications (1)

Publication Number Publication Date
JPS6418843A true JPS6418843A (en) 1989-01-23

Family

ID=16012304

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62176363A Pending JPS6418843A (en) 1987-07-14 1987-07-14 Cache memory device

Country Status (1)

Country Link
JP (1) JPS6418843A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102013220536A1 (en) 2012-12-03 2014-06-05 Suzuki Motor Corp. Resin front end part structure for use in vehicle, has reinforcement support and blocking parts fastened to each other in direction from front side to rear side of vehicle in overlapping condition, where support is arranged in arms
US10802712B2 (en) 2015-10-13 2020-10-13 Axell Corporation Information processing apparatus and method of processing information

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102013220536A1 (en) 2012-12-03 2014-06-05 Suzuki Motor Corp. Resin front end part structure for use in vehicle, has reinforcement support and blocking parts fastened to each other in direction from front side to rear side of vehicle in overlapping condition, where support is arranged in arms
US10802712B2 (en) 2015-10-13 2020-10-13 Axell Corporation Information processing apparatus and method of processing information

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